*** empty log message ***

diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
index a208338298f92da94b4edde6e348e6a227107ecd..3d952c050fdcfa53ecd313d9cd74535eb291f79c 100755 (executable)
--- a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd
@@ -599,7 +599,7 @@ refclk2core_out <= refck2core;
 
 -- Instantiation of serdes module
 
-  gen_serdes_0_ext_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_NO generate
+  gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_NO generate
     THE_SERDES: serdes_gbe_0_extclock
       port map(
         refclkp                => SD_REFCLK_P_IN,
@@ -645,7 +645,7 @@ refclk2core_out <= refck2core;
         );
   end generate;
 
-  gen_serdes_0_ext : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_YES generate
+  gen_serdes_0_ext_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_YES and USE_200_MHZ = c_YES generate
     THE_SERDES: serdes_gbe_0_200_ext
       port map(
         refclkp                => SD_REFCLK_P_IN,
@@ -691,7 +691,7 @@ refclk2core_out <= refck2core;
         );
   end generate;
 
-  gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate
+  gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate
     THE_SERDES: serdes_gbe_0
       port map(
         core_txrefclk          => clk,
@@ -737,7 +737,7 @@ refclk2core_out <= refck2core;
         );
   end generate;
 
-  gen_serdes_0 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate
+  gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate
     THE_SERDES: serdes_gbe_0_200
       port map(
         core_txrefclk          => clk,