testbanches for dataSender simulation in modelsim (with calibration)

diff --git a/src/testbench/dataSender_tb.vhd b/src/testbench/dataSender_tb.vhd
new file mode 100644 (file)
index 0000000..765666d
--- /dev/null
+++ b/src/testbench/dataSender_tb.vhd
@@ -0,0 +1,216 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dataSender_tb is
+end dataSender_tb;
+
+architecture Behavioral of dataSender_tb is
+
+signal CLK, CLK_inv,RESET : std_logic := '0';
+signal data_in, data_out : std_logic_vector(15 downto 0);
+signal cal_active, dready_in, dready_out, eod_in, eod_out : std_logic;
+signal pack_num_in, pack_num_out : std_logic_vector(2 downto 0);
+
+constant CLK_PERIOD : time := 10 ns;
+
+signal BUS_RX : CTRLBUS_RX;
+signal BUS_TX : CTRLBUS_TX;
+
+begin
+
+   THE_CRI_DATA_SENDER :  entity work.cri_data_sender
+      port map(
+        --  Misc
+        CLK                      => CLK,
+        RESET                    => RESET,
+        CLK_EN                   => '1',
+    
+        ENABLE_TRANSPORT         => '1',--dbg_start_data_send,
+        
+        -- Port to API           
+        API_DATA_OUT             => open,
+        API_PACKET_NUM_OUT       => open,
+        API_DATAREADY_OUT        => open,
+        API_READ_IN              => '1',
+        API_SHORT_TRANSFER_OUT   => open,
+        API_DTYPE_OUT            => open,
+        API_ERROR_PATTERN_OUT    => open,
+        API_SEND_OUT             => open,
+        -- Receiver port         
+        API_DATA_IN              => x"1234",
+        API_PACKET_NUM_IN        => "000",
+        API_TYP_IN               => "000",
+        API_DATAREADY_IN         => '0',
+        API_READ_OUT             => open,
+        -- APL Control port      
+        API_RUN_IN               => '1',
+        API_SEQNR_IN             => (others => '0'),
+        API_LENGTH_OUT           => open,
+        MY_ADDRESS_IN            => x"1234",
+
+        CTS_NUMBER_IN            => (others => '0'),
+        CTS_CODE_IN              => (others => '0'),
+        CTS_INFORMATION_IN       => (others => '0'),
+        CTS_READOUT_TYPE_IN      => (others => '0'),
+        CTS_START_READOUT_IN     => '1',
+        CTS_READ_IN              => '1',
+        CTS_DATA_OUT             => open,
+        CTS_DATAREADY_OUT        => open,
+        CTS_READOUT_FINISHED_OUT => open,
+        CTS_LENGTH_OUT           => open,
+        CTS_ERROR_PATTERN_OUT    => open,
+        -- Data from Frontends
+        FEE_DATA_IN              => data_in,
+        FEE_DATAREADY_IN         => dready_in,
+        FEE_READ_OUT             => open,
+        FEE_BUSY_IN              => '1',
+        FEE_STATUS_BITS_IN       => (others => '0'),
+        
+        BUS_CALIBRATON_RX        => BUS_RX,
+        BUS_CALIBRATON_TX        => BUS_TX,
+        
+        DEBUG_OUT                => open
+        );
+    
+
+  CLK_PROC : process is
+  begin
+     CLK <= '1';
+     CLK_inv <= '0';
+     wait for CLK_PERIOD / 2;
+     CLK_inv <= '1';
+     CLK <= '0';
+     wait for CLK_PERIOD / 2;
+  end process;
+  
+  
+  proc_Cal : process is
+    begin
+      wait for 10 ns;
+      RESET <= '1';
+      wait for 20 ns;
+      RESET <= '0';
+      wait for 50 ns;
+      dready_in  <= '0';
+      cal_active <= '1';
+      data_in    <= x"1234";
+      eod_in     <= '0';
+      wait for 20 ns;
+      data_in     <= x"1234";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"5678";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0004";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"8202";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"7200";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"2000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"9601";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000"; --Trailer
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"1234";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"7201";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+
+      wait for 10 ns;
+      data_in     <= x"2000";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"9600";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"4567";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"8202";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0123";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"4567";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0001";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"5555";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0001";
+      eod_in      <= '1';
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      eod_in      <= '0';
+--      pack_num_in <= "010";
+      dready_in   <= '0';
+      cal_active  <= '0';
+      wait for 500 ns; 
+    end process;
+
+
+end Behavioral;
\ No newline at end of file

diff --git a/src/testbench/dataSender_tdc_cal_tb.vhd b/src/testbench/dataSender_tdc_cal_tb.vhd
new file mode 100644 (file)
index 0000000..ec441ee
--- /dev/null
+++ b/src/testbench/dataSender_tdc_cal_tb.vhd
@@ -0,0 +1,179 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dataSender_tdc_cal_tb is
+end dataSender_tdc_cal_tb;
+
+architecture dataSender_tdc_cal_tb_arch of dataSender_tdc_cal_tb is
+
+signal CLK, CLK_inv : std_logic := '0';
+signal data_in, data_out : std_logic_vector(15 downto 0);
+signal cal_active, dready_in, dready_out, eod_in, eod_out : std_logic;
+signal pack_num_in, pack_num_out : std_logic_vector(2 downto 0);
+
+constant CLK_PERIOD : time := 10 ns;
+
+signal BUS_RX : CTRLBUS_RX;
+signal BUS_TX : CTRLBUS_TX;
+
+begin
+
+  THE_CAL : entity work.cbm_rich_calib
+   port map(
+      CLK                    => CLK,
+      RESET                  => '0',
+
+      CRI_CAL_ACTIVE         => cal_active,
+      
+      CRI_APL_DATA_IN        => data_in,
+      CRI_APL_PACKET_NUM_IN  => pack_num_in,
+      CRI_APL_DATAREADY_IN   => dready_in,
+      CRI_CALIB_EOD_IN       => eod_in,
+                             
+      CRI_APL_DATA_OUT       => data_out,
+      CRI_APL_PACKET_NUM_OUT => pack_num_out,
+      CRI_APL_DATAREADY_OUT  => dready_out,
+      CRI_CALIB_EOD_OUT      => eod_out,
+      
+      BUS_RX                 => BUS_RX,
+      BUS_TX                 => BUS_TX
+   );
+    
+
+  CLK_PROC : process is
+  begin
+     CLK <= '1';
+     CLK_inv <= '0';
+     wait for CLK_PERIOD / 2;
+     CLK_inv <= '1';
+     CLK <= '0';
+     wait for CLK_PERIOD / 2;
+  end process;
+  
+  
+  proc_Cal : process is
+    begin
+      wait for 10 ns;
+      dready_in  <= '0';
+      cal_active <= '1';
+      data_in    <= x"1234";
+      eod_in     <= '0';
+      wait for 20 ns;
+      data_in     <= x"1234";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"5678";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0004";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"8202";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"7200";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"2000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"9601";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000"; --Trailer
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"1234";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"7201";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+
+      wait for 10 ns;
+      data_in     <= x"2000";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"9600";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"4567";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0002";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"8202";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0123";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"4567";
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0001";
+      pack_num_in <= "000";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"5555";
+      pack_num_in <= "001";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      pack_num_in <= "010";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0001";
+      eod_in      <= '1';
+      pack_num_in <= "011";
+      dready_in   <= '1';
+      wait for 10 ns;
+      data_in     <= x"0000";
+      eod_in      <= '0';
+--      pack_num_in <= "010";
+      dready_in   <= '0';
+      cal_active  <= '0';
+      wait for 500 ns; 
+    end process;
+
+
+end dataSender_tdc_cal_tb_arch;
\ No newline at end of file