added module configuration to CTS prj-file: All include-statements from config.vhd...

diff --git a/cts/compile_constraints.pl b/cts/compile_constraints.pl
index 1aa1f020f3613c61aa802320dc11562d561e2727..943660365143b99287e0e222b8493390f7a0776a 100755 (executable)
--- a/cts/compile_constraints.pl
+++ b/cts/compile_constraints.pl
@@ -10,6 +10,28 @@ my $workdir = './workdir';
 my $script_dir = dirname(realpath(__FILE__));
 $workdir = $ARGV[0] if (@ARGV);
 
+
+# get activated modules
+open(CONFIG, 'config.vhd');
+my $config = "#!!! This file was compiled using compile_contraints.pl.\n#!!! DO NOT EDIT AS ALL CHANGES WILL BE OVERRIDEN\n\n";
+print "The following module configuration was derived from config.vhd:\n";
+while(my $line = <CONFIG>) {
+   if ($line =~ /(INCLUDE_\S+).*:=.*c_(yes|no)/i) {
+      my $mod = uc $1;
+      my $ena = (lc $2) eq 'yes' ? 1 : 0;
+      
+      my $conf = "set $mod $ena\n";
+      print ' ' . $conf;
+      $config .= $conf;
+   }
+}
+close(CONFIG);
+
+open TCLCONF, '>', $TOPNAME . '_prjconfig.tcl';
+print TCLCONF $config;
+close TCLCONF;
+
+
 die("workdir has to be relative to compile_constraints.pl") if $workdir =~ m/^\//;
 die("workdir must not contain ..") if $workdir =~ m/\.\./;
 $workdir =~ s/(\.\/|\/$)//g; # remove ./ and trailing slash
@@ -35,4 +57,6 @@ system ("ln -sfT $back/../tdc_release/Adder_304.ngo $workdir/Adder_304.ngo");
 system("cp ../base/trb3_central_cts.lpf $workdir/$TOPNAME.lpf");
 system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf");
 system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf");
-system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' $workdir/$TOPNAME.lpf");
\ No newline at end of file
+system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' $workdir/$TOPNAME.lpf");
+
+

diff --git a/cts/config_default.vhd b/cts/config_default.vhd
index 07cc1dd9f0bf0e82bbdc765f4875f7810409724a..96567b0642b4f8450cf373ac4450f425c8078a58 100644 (file)
--- a/cts/config_default.vhd
+++ b/cts/config_default.vhd
@@ -4,20 +4,24 @@ use ieee.numeric_std.all;
 use work.trb_net_std.all;
 
 package config is
-
-
 ------------------------------------------------------------------------------
 --Begin of configuration
 ------------------------------------------------------------------------------
 
+   constant INCLUDE_CTS : integer range c_NO to c_YES := c_YES;
+   constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_NO;
+
 --include TDC for all four trigger input lines
     constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO;
     constant TDC_CHANNEL_NUMBER : integer := 5;
+
 --Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels
     constant USE_64_FIFO : integer := c_YES;
 
+--Define ringbuffer size for TDC channels: 32-64-128
+    constant RING_BUFFER_SIZE : integer range 32 to 128 := 32;
     
---use all four SFP (1-4) as downlink to other boards.     
+--use all four SFP (1-4) as downlink to other boards (only w/o CBMNET)
     constant USE_4_SFP   : integer range c_NO to c_YES := c_NO;
 
     
@@ -29,7 +33,7 @@ package config is
     
     
 --Which external trigger module (ETM) to use?
-    type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2);
+    type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET);
     constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
     
 ------------------------------------------------------------------------------

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 945c1f15f77310d97391f1ff67a15cd31f5de7bd..1faeba05bea47711d2b4ea383387c451d67fe841 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -1,3 +1,5 @@
+# load configuration derived from config.vhd by compile_constraints.pl
+source trb3_central_prjconfig.tcl  
 
 # implementation: "workdir"
 impl -add workdir -type fpga
@@ -240,47 +242,136 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
 
+
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib work "../base/cores/pll_in125_out20.vhd"
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-add_file -vhdl -lib work "source/cts_pkg.vhd"
-add_file -vhdl -lib work "source/cts_fifo.vhd"
-add_file -vhdl -lib work "source/cts_trg_input.vhd"
-add_file -vhdl -lib work "source/cts_trg_coin.vhd"
-add_file -vhdl -lib work "source/cts_trg_pseudorand_pulser.vhd"
-add_file -vhdl -lib work "source/cts_trigger.vhd"
-add_file -vhdl -lib work "source/cts.vhd"
-
-###############
-#Change path to tdc release also in compile script!
-###############
-# don't use vhd but link Adder_304.ngo to workdir!
-#add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
-#add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd"
-#add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
-#add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "tdc_release/FIFO_32x32_OutReg.vhd"
-#add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd"
-#add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
-##add_file -vhdl -lib "work" "tdc_release/ROM_FIFO.vhd"
-#add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
-#add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
-#add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"
-#add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd"
-#add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
-#add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd"
-#add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
-#add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
-#add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd"
-#add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
 
+add_file -vhdl -lib work "source/cts_pkg.vhd"
+add_file -vhdl -lib work "source/cbmnet_dlm_etm.vhd"
+if {$INCLUDE_CTS == 1} {
+   add_file -vhdl -lib work "source/cts_fifo.vhd"
+   add_file -vhdl -lib work "source/cts_trg_input.vhd"
+   add_file -vhdl -lib work "source/cts_trg_coin.vhd"
+   add_file -vhdl -lib work "source/cts_trg_pseudorand_pulser.vhd"
+   add_file -vhdl -lib work "source/cts_trigger.vhd"
+   add_file -vhdl -lib work "source/cts.vhd"
+}
+
+if {$INCLUDE_TDC == 1} {
+   ###############
+   #Change path to tdc release also in compile script!
+   ###############
+   # don't use vhd but link Adder_304.ngo to workdir!
+   #add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
+   add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd"
+   add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
+   add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
+   add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
+   add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
+   add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd"
+   add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
+   #add_file -vhdl -lib "work" "tdc_release/FIFO_32x32_OutReg.vhd"
+   add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
+   add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
+   #add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd"
+   #add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd"
+   add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
+   #add_file -vhdl -lib "work" "tdc_release/ROM_FIFO.vhd"
+   add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
+   add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
+   add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"
+   add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd"
+   add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
+   add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd"
+   add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
+   add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
+   add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd"
+   add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
+}
+
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_interface_pkg.vhd"
+add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_pkg.vhd"
+if {$INCLUDE_CBMNET == 1} {
+   set_option -include_path {../cbmnet/cbmnet/cores/CBMnet/includes/}
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_2c.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w2r_1c.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_1c.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_2rw_2c.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/rams/ram_1w1r_1c_enable.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fast_fifo.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_ram.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fast_fifo/fifo_reg.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_fwft_fifo.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/spec_standard_fifo.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_spec_so.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/empty_logic_wo_spec.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_wo_spec.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/fwft_fifo_spec/full_logic_spec_si_all.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/async_fifo.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/async_standard_fifo.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_r2w.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_w2r.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/sync_w2r_hs.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic_spec_shift_out.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/empty_logic_spec_shift_out_1_inc.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic_spec_shift_in.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/cores_fpga/common/async_fifo/full_logic_spec_shift_in_1_inc.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_barrel_shifter.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_rx_pcs_init_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_rx_pcs_wrapper.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_init_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_tx_pcs_wrapper.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/pcs_init/cn_async_input_sync.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/dlm_reflect.v"
+
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_top.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_arbiter_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_crc_generator.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_in.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_dlm_out.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_in_decode.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_init_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_init.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_in.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_out.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_packet_gen.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_buffer.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_receive_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_service_ctrl.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_service.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_slave_top.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_rx_top.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_send_buffer.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_send_fsm.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v"
+   add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v"
+
+   add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd"
+   add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_rx_gear.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_tx_gear.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3.vhd"
+   
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_fifo.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_tx_fsm.vhd"
+   add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout.vhd"
+
+
+}
 
 add_file -vhdl -lib work "./trb3_central.vhd"
 #add_file -fpga_constraint "./cts.fdc"