DDMTD continued

diff --git a/special/ddmtd.vhd b/special/ddmtd.vhd
index 1f1d35e592a3c07b4e686c8e87e7ef73d6d3b49f..c5c3add922e6a32defc95bcc29f85c6e42f51184 100644 (file)
--- a/special/ddmtd.vhd
+++ b/special/ddmtd.vhd
@@ -13,9 +13,10 @@ port(
   PING_OUT         : out std_logic; -- stretched TX_K signal\r
   PONG_OUT         : out std_logic; -- stretched RX_K signal\r
   START_PING_OUT   : out std_logic; -- rising edge of stretched TX_K signal\r
-  START_PONG_OUT   : out std_logic; -- rising edge of stretched RX_K signal \r
-  TOGGLE_OUT       : out std_logic;\r
-  BEAT_OUT         : out std_logic\r
+  START_PONG_OUT   : out std_logic; -- rising edge of stretched RX_K signal\r
+  DELAY_VALUE_OUT  : out std_logic_vector(15 downto 0);\r
+  DELAY_VALID_OUT  : out std_logic;\r
+  TOGGLE_OUT       : out std_logic  -- for checking by scope\r
 );\r
 end entity ddmtd;\r
 \r
@@ -23,12 +24,16 @@ architecture ddmtd_arch of ddmtd is
 \r
   signal ping_q        : std_logic_vector(2 downto 0);\r
   signal pong_q        : std_logic_vector(2 downto 0);\r
-  signal beat_xor_x    : std_logic;\r
-  signal beat_xor_q    : std_logic;\r
   signal toggle_q      : std_logic;\r
   signal start_ping_i  : std_logic;\r
   signal start_pong_i  : std_logic;\r
   \r
+  signal delay_ce      : std_logic;\r
+  signal delay_rst     : std_logic;\r
+  signal delay_ctr     : unsigned(9 downto 0);\r
+  signal delay_store   : std_logic;\r
+  signal delay_valid   : std_logic;\r
+  signal delay_data    : std_logic_vector(15 downto 0);\r
 \r
   attribute HGROUP : string;\r
 --  attribute BBOX   : string;\r
@@ -48,7 +53,6 @@ begin
     ping_q        <= ping_q(1 downto 0) & PING_IN;\r
     pong_q        <= pong_q(1 downto 0) & PONG_IN;\r
     -- register stages\r
-    beat_xor_q    <= beat_xor_x;\r
   end if;\r
 end process THE_SAMPLER_PROC;\r
 \r
@@ -70,8 +74,46 @@ port map(
   START_OUT  => start_pong_i\r
 );\r
 \r
--- XOR of both stretched signals\r
-beat_xor_x <= ping_q(1) xor pong_q(1);\r
+-- delay counter\r
+THE_DELAY_CTR_PROC: process( AUXCLK, RESET )\r
+begin\r
+  if   ( RESET = '1' ) then\r
+    delay_ctr <= (others => '0');\r
+  elsif( rising_edge(AUXCLK) ) then\r
+    if   ( delay_rst = '1' ) then\r
+      delay_ctr <= (others => '0');\r
+    elsif( delay_ce = '1' ) then\r
+      delay_ctr <= delay_ctr + 1;\r
+    end if;\r
+  end if;\r
+end process THE_DELAY_CTR_PROC;\r
+\r
+delay_rst   <= start_pong_i;\r
+delay_store <= start_pong_i;\r
+\r
+THE_DELAY_CE_PROC: process( AUXCLK, RESET )\r
+begin\r
+  if   ( RESET = '1' ) then\r
+    delay_ce <= '0';\r
+  elsif( rising_edge(AUXCLK) ) then\r
+    if   ( (start_ping_i = '1') and (start_pong_i = '0') ) then\r
+      delay_ce <= '1';\r
+    elsif( (start_pong_i = '1') ) then\r
+      delay_ce <= '0';\r
+    end if;\r
+  end if;\r
+end process THE_DELAY_CE_PROC;\r
+\r
+THE_DELAY_STORE_PROC: process( AUXCLK, RESET )\r
+begin\r
+  if   ( RESET = '1' ) then\r
+    delay_data <= (others => '0');\r
+  elsif( rising_edge(AUXCLK) ) then\r
+    if( delay_store = '1' ) then\r
+      delay_data <= b"000000" & std_logic_vector(delay_ctr);\r
+    end if;\r
+  end if;\r
+end process THE_DELAY_STORE_PROC;\r
 \r
 -- toggle bit for clock check\r
 THE_TOGGLE_PROC: process( AUXCLK, RESET )\r
@@ -87,8 +129,8 @@ PING_OUT        <= ping_q(1);
 PONG_OUT        <= pong_q(1);\r
 START_PING_OUT  <= start_ping_i;\r
 START_PONG_OUT  <= start_pong_i;\r
-\r
+DELAY_VALUE_OUT <= delay_data;\r
+DELAY_VALID_OUT <= delay_valid;\r
 TOGGLE_OUT      <= toggle_q;\r
-BEAT_OUT        <= beat_xor_q;\r
 \r
 end architecture;\r

diff --git a/special/deglitch.vhd b/special/deglitch.vhd
index d2ba61bac72896164e6eab56f089233baf365f05..3931f054df5005ba838748b07223b1be4288c722 100644 (file)
--- a/special/deglitch.vhd
+++ b/special/deglitch.vhd
@@ -54,8 +54,8 @@ begin
   end if;\r
 end process THE_UP_DOWN_COUNTER_PROC;\r
 \r
-ctr_up_x    <= '1' when ( (SIGNAL_IN = '1') and (deglitch_q(7) = '0') ) else '0';\r
-ctr_down_x  <= '1' when ( (SIGNAL_IN = '0') and (deglitch_q(7) = '1') ) else '0';\r
+ctr_up_x    <= '1' when ( (SIGNAL_IN = '1') and (deglitch_q(7) = '0') and (counter < 8) ) else '0';\r
+ctr_down_x  <= '1' when ( (SIGNAL_IN = '0') and (deglitch_q(7) = '1') and (counter > 0) ) else '0';\r
 \r
 --start_x <= '1' when ( counter = x"4" ) else '0';\r
 start_x <= '1' when ( (counter = x"3") and (ctr_up_x = '1') ) else '0';\r