signal ram_read_addr1 : std_logic_vector(2 downto 0);
signal ram_read_addr2 : std_logic_vector(2 downto 0);
signal buf_API_READ_OUT, next_API_READ_OUT : std_logic;
-signal write_UNIQUE_ID : std_logic;
+signal read_UNIQUE_ID : std_logic;
-type state_t is (IDLE, SEND1, SEND2, SEND3, SEND_UNIQUE_ID);
+type state_t is (IDLE, SEND1, SEND2, SEND3);
signal next_state, state : state_t;
+signal next_read_uid_1, read_uid_1 : std_logic;
+signal next_read_uid_2, read_uid_2 : std_logic;
begin
buf_API_READ_OUT <= '1';
write_ADDRESS <= '0';
ADDRESS_REJECTED <= '0';
+ read_UNIQUE_ID <= '0';
if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' then
buf_API_READ_OUT <= '0';
ram_read_addr1 <= ram_read_addr1 + 1;
+ if API_DATA_IN = READ_ID then
+ read_UNIQUE_ID <= '1';
+ end if;
if API_DATA_IN = ram_read_dout then
matching_counter <= matching_counter + 1;
end if;
end if;
end process;
- send_ack : process(write_ADDRESS, state, API_READ_IN, ram_read_dout)
+ send_ack : process(write_ADDRESS, state, API_READ_IN, ram_read_dout, read_uid_1, read_uid_2, read_UNIQUE_ID)
begin
next_state <= state;
API_DATAREADY_OUT <= '0';
API_PACKET_NUM_OUT <= "01";
API_DATA_OUT <= ram_read_dout;
ram_read_addr2 <= "000";
+ next_read_uid_1 <= read_uid_1;
+ next_read_uid_2 <= read_uid_2;
case state is
when IDLE =>
if write_ADDRESS = '1' then
ram_read_addr2 <= "111";
next_state <= SEND1;
- elsif write_UNIQUE_ID = '1' then
+ elsif read_UNIQUE_ID = '1' then
ram_read_addr2 <= "001";
- next_state <= SEND_UNIQUE_ID;
+ next_read_uid_1 <= '1';
+ next_state <= SEND1;
end if;
when SEND1 =>
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "01";
- ram_read_addr2 <= "111";
+ if read_uid_1 = '1' then
+ ram_read_addr2 <= "001";
+ elsif read_uid_2 = '1' then
+ ram_read_addr2 <= "100";
+ else
+ ram_read_addr2 <= "111";
+ end if;
+
if API_READ_IN = '1' then
- ram_read_addr2 <= "101";
+ if read_uid_1 = '1' then
+ ram_read_addr2 <= "010";
+ else
+ ram_read_addr2 <= "101";
+ end if;
next_state <= SEND2;
end if;
when SEND2 =>
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "10";
- ram_read_addr2 <= "101";
+ if read_uid_1 = '1' then
+ ram_read_addr2 <= "010";
+ else
+ ram_read_addr2 <= "101";
+ end if;
if API_READ_IN = '1' then
- ram_read_addr2 <= "110";
+ if read_uid_1 = '1' then
+ ram_read_addr2 <= "011";
+ else
+ ram_read_addr2 <= "110";
+ end if;
next_state <= SEND3;
end if;
when SEND3 =>
API_DATAREADY_OUT <= '1';
API_PACKET_NUM_OUT <= "11";
- ram_read_addr2 <= "110";
- if API_READ_IN = '1' then
- next_state <= IDLE;
- ram_read_addr2 <= "000";
- end if;
- when SEND_UNIQUE_ID =>
- API_DATAREADY_OUT <= '1';
- API_PACKET_NUM_OUT <= "01";
- ram_read_addr2 <= "001";
+ if read_uid_1 = '1' then
+ ram_read_addr2 <= "011";
+ else
+ ram_read_addr2 <= "110";
+ end if;
if API_READ_IN = '1' then
- ram_read_addr2 <= ram_read_addr2 + 1;
- if ram_read_addr2 = "110" then
+ if read_uid_1 = '1' then
+ next_state <= SEND1;
+ ram_read_addr2 <= "100";
+ next_read_uid_1 <= '0';
+ next_read_uid_2 <= '1';
+ else
next_state <= IDLE;
+ ram_read_addr2 <= "000";
+ next_read_uid_2 <= '0';
end if;
end if;
end case;
process(CLK)
begin
if rising_edge(CLK) then
- state <= next_state;
+ if RESET = '1' then
+ read_uid_1 <= '0';
+ read_uid_2 <= '0';
+ else
+ state <= next_state;
+ read_uid_1 <= next_read_uid_1;
+ read_uid_2 <= next_read_uid_2;
+ end if;
-- buf_API_READ_OUT <= next_API_READ_OUT;
end if;
end process;
signal reset_timecounter : std_logic;
signal send_bit, next_send_bit : std_logic;
signal recv_bit,next_recv_bit : std_logic;
- signal recv_bit_ready : std_logic;
+ signal recv_bit_ready, next_recv_bit_ready : std_logic;
signal output_tmp, next_output_tmp : std_logic;
signal word : std_logic_vector(15 downto 0);
signal ram_addr : std_logic_vector(2 downto 0);
signal reading_temp, next_reading_temp : std_logic;
signal skip_rom, next_skip_rom : std_logic;
signal buf_TEMP_OUT : std_logic_vector(11 downto 0);
-
+ signal buf_STAT : std_logic;
begin
ONEWIRE <= '0' when output = '0' else 'Z';
inc_bitcounter <= '0';
next_send_bit <= send_bit;
next_recv_bit <= '0';
- recv_bit_ready <= '0';
+ next_recv_bit_ready <= '0';
next_send_rom <= send_rom;
next_conv_temp <= conv_temp;
next_reading_temp <= reading_temp;
next_skip_rom <= not send_rom and not bitcounter_vector(3);
inc_bitcounter <= '1';
next_state <= WRITE_START;
-
+
if send_rom = '1' then
next_send_bit <= not bitcounter_vector(1); --this is x33, lsb first
else
reset_timecounter <= '1';
if send_rom = '1' or skip_rom = '1' then
next_state <= SEND_ROM_COMMAND;
--- elsif skip_rom = '1' then
--- next_state <= SEND_SKIP_ROM;
elsif conv_temp = '1' then
next_state <= SEND_CONV_TEMP;
elsif reading_temp = '1' then
end if;
if is_time_reached(timecounter,10000,CLK_PERIOD) = '1' then
next_recv_bit <= input;
- recv_bit_ready <= '1';
+ next_recv_bit_ready <= '1';
next_state <= READ_WAIT;
end if;
when READ_WAIT =>
output_tmp <= '0';
recv_bit <= '0';
else
+ recv_bit_ready <= next_recv_bit_ready;
state <= next_state;
send_bit <= next_send_bit;
output <= next_output;
if rising_edge(CLK) then
ram_wr <= '0';
if recv_bit_ready = '1' and (send_rom = '1' or reading_temp = '1') then
+ buf_STAT <= not buf_STAT;
ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4));
ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4));
word(14 downto 0) <= word(15 downto 1);
ram_wr <= '1';
end if;
if bitcounter_vector(3 downto 0) = "1100" and reading_temp = '1' then
- buf_TEMP_OUT <= recv_bit & word(14 downto 4);
+ buf_TEMP_OUT <= recv_bit & word(15 downto 5);
end if;
end if;
end if;
end process;
---saving temperature
- -- process(CLK)
- -- begin
- -- if rising_edge(CLK) then
- -- if recv_bit_ready = '1' and reading_temp = '1' then
- -- temp_shift(10 downto 0) <= temp_shift(11 downto 1);
- -- temp_shift(11) <= recv_bit;
- -- if bitcounter_vector(3 downto 0) = "1100" then
- -- buf_TEMP_OUT <= temp_shift;
- -- end if;
- -- end if;
- -- end if;
- -- end process;
-
ADDR_OUT <= ram_addr;
DATA_OUT <= word;
WRITE_OUT <= ram_wr;
STAT(4) <= skip_rom;
STAT(5) <= conv_temp;
STAT(6) <= reading_temp;
- STAT(7) <= '0';
+ STAT(7) <= buf_STAT;
STAT(11 downto 8) <= bitcounter_vector(3 downto 0);
STAT(31 downto 12) <= (others => '0');
jspc29 / trbnet.git / commitdiff