remove hidden files

diff --git a/._s1.clpf b/._s1.clpf
deleted file mode 100644 (file)
index e86ce85..0000000
--- a/._s1.clpf
+++ /dev/null
@@ -1,18 +0,0 @@
-U trig_gate0 110 244 73
-U tdc_ch0 247 119 138
-U tdc2 66 26 255
-U tdc0 115 59 252
-U tdc22 101 224 55
-U gate2 238 76 83
-U tdc3 112 247 17
-U trig3 53 219 7
-U dec3 86 255 151
-U tdc0_neg 170 243 245
-U hades_trig 216 167 1
-U hades_tdc_pos 224 5 46
-U hades_tdc_neg 0 76 253
-U hades_dec_pos 122 134 206
-U hades_dec_neg 57 6 226
-U lvl1_dec 47 253 157
-U lvl1_pad 249 5 48
-U lvl1_tdc 253 230 130

diff --git a/.floorplanner.ini b/.floorplanner.ini
deleted file mode 100644 (file)
index bb36624..0000000
--- a/.floorplanner.ini
+++ /dev/null
@@ -1,14 +0,0 @@
-[General]
-showNCD=true
-showPgroups=true
-showCongestion=false
-showConnsSelect=true
-showConnsBetween=true
-showConnsOutside=true
-showLPF=true
-showREGIONs=true
-showUGROUPs=true
-showPARITIONs=true
-showLogicalConnections=false
-dontShowBBoxOverlapWarning=false
-sceneInViewRect=@Variant(\0\0\0\x14\0\0\0\0\0\0\0\0@\xf1\x63\xce\xc1%a\xc2@\xfa! X\n8N@\xe6\x42PSc\f~)

diff --git a/.recovery b/.recovery
deleted file mode 100644 (file)
index c259e92..0000000
--- a/.recovery
+++ /dev/null
@@ -1,82 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="s1" device="LFE5UM5G-45F-8BG381C" default_implementation="impl1">
-    <Options/>
-    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb5_tb" top="top_tf"/>
-        <Source name="top.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="pll0/pll0.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="pll1/pll1.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="fifo32dc/fifo32dc.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/intface.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/modem.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/rxcver.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/txmitt.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/uart_top.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../multipll/uart/source/UART_VerilogWrapper_TOP.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="pll8/pll8.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="pll_random/pll_random.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="modules.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="modules2.v" type="Verilog" type_short="Verilog">
-            <Options>
-                <Option name="include path" value="tdc_channel_fifo_out"/>
-            </Options>
-        </Source>
-        <Source name="fifo_colector.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="fifo40_dc/fifo40_dc.sbx" type="sbx" type_short="SBX">
-            <Options/>
-        </Source>
-        <Source name="top2.v" type="Verilog" type_short="Verilog">
-            <Options top_module="top_tf"/>
-        </Source>
-        <Source name="trb5_tb.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="endp_dummy.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="endp_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="hades_modules.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="hades_modules2.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="hades_colector.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="s1.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="s11.sty"/>
-</BaliProject>

diff --git a/.run_manager.ini b/.run_manager.ini
deleted file mode 100644 (file)
index 06e8e36..0000000
--- a/.run_manager.ini
+++ /dev/null
@@ -1,9 +0,0 @@
-[Runmanager]
-Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\x1f\0\0\x1\x1c\0\0\0\xf3\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
-windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
-headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
-
-[impl1%3CStrategy1%3E]
-isChecked=false
-isHidden=false
-isExpanded=false

diff --git a/.setting.ini b/.setting.ini
deleted file mode 100644 (file)
index 8ba7e6f..0000000
--- a/.setting.ini
+++ /dev/null
@@ -1,5 +0,0 @@
-[General]
-PAR.auto_tasks=PARTrace, IOTiming
-Map.auto_tasks=MapTrace
-Export.auto_tasks=TimingSimFileVlg, TimingSimFileVHD
-AutoAssign=true

diff --git a/.spread_sheet.ini b/.spread_sheet.ini
deleted file mode 100644 (file)
index 6c511f4..0000000
--- a/.spread_sheet.ini
+++ /dev/null
@@ -1,3 +0,0 @@
-[General]
-COLUMN_POS_INFO_NAME_-1_0=Prioritize
-COLUMN_POS_INFO_NAME_-1_1=PIO Register

diff --git a/.spreadsheet_view.ini b/.spreadsheet_view.ini
deleted file mode 100644 (file)
index 9e5c03f..0000000
--- a/.spreadsheet_view.ini
+++ /dev/null
@@ -1,78 +0,0 @@
-[General]
-pin_sort_type=0
-pin_sort_ascending=true
-sig_sort_type=0
-sig_sort_ascending=true
-active_Sheet=Port Assignments
-
-[Port%20Assignments]
-Name="296,0"
-Group%20By="72,1"
-Pin="69,2"
-BANK="55,3"
-BANK_VCC="76,4"
-VREF="51,5"
-IO_TYPE="151,6"
-PULLMODE="99,7"
-DRIVE="57,8"
-SLEWRATE="91,9"
-CLAMP="60,10"
-OPENDRAIN="83,11"
-DIFFRESISTOR="94,12"
-DIFFDRIVE="76,13"
-HYSTERESIS="84,14"
-TERMINATION="90,15"
-Outload%20%28pF%29="88,16"
-MaxSkew="70,17"
-Clock%20Load%20Only="103,18"
-SwitchingID="85,19"
-Ground%20plane%20PCB%20noise%20%28mV%29="166,20"
-Power%20plane%20PCB%20noise%20%28mV%29="159,21"
-SSO%20Allowance%28%25%29="113,22"
-sort_columns="Name,Ascending"
-
-[Pin%20Assignments]
-Pin="92,0"
-Pad%20Name="77,1"
-Dual%20Function="184,2"
-Polarity="65,3"
-BANK="0,4"
-BANK_VCC="76,5"
-IO_TYPE="151,6"
-Signal%20Name="323,7"
-Signal%20Type="111,8"
-sort_columns="Pin,Ascending"
-
-[Clock%20Resource]
-Clock%20Type="100,ELLIPSIS"
-Clock%20Name="100,ELLIPSIS"
-Selection="100,ELLIPSIS"
-Quadrant="100,ELLIPSIS"
-
-[Global%20Preferences]
-Preference%20Name="241,ELLIPSIS"
-Preference%20Value="268,ELLIPSIS"
-
-[Cell%20Mapping]
-Type="100,ELLIPSIS"
-Name="100,ELLIPSIS"
-Din\Dout="100,ELLIPSIS"
-PIO%20Register="100,ELLIPSIS"
-
-[Route%20Priority]
-Type="100,ELLIPSIS"
-Name="100,ELLIPSIS"
-Prioritize="100,ELLIPSIS"
-
-[Timing%20Preferences]
-Preference%20Name="168,ELLIPSIS"
-Preference%20Value="88,ELLIPSIS"
-Preference%20Unit="79,ELLIPSIS"
-
-[Group]
-Group%20Type\Name="689,ELLIPSIS"
-Value="177,ELLIPSIS"
-
-[Misc%20Preferences]
-Preference%20Name="207,ELLIPSIS"
-Preference%20Value="84,ELLIPSIS"

diff --git a/ctdc_enc.v b/ctdc_enc.v
deleted file mode 100644 (file)
index c94be35..0000000
--- a/ctdc_enc.v
+++ /dev/null
@@ -1,129 +0,0 @@
-module ctdc_enc_neg(
-                                                                       clk,
-                                                                       in,\r
-                                                                       in_valid,
-                                                                       out,
-                                                                       out_valid
-                                                                       ) /* synthesis syn_preserve= 1*/;
-
-input wire clk;
-input wire [7:0]in;\r
-input wire in_valid;
-output reg [2:0]out /*synthesis syn_preserve=1*/;
-output reg out_valid /*synthesis syn_preserve=1*/;
-
-
-       always @ (posedge clk)begin\r
-               if(in_valid)begin
-               case (in)       
-                               8'b11111110 : begin
-                        out <= 3'b000;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11111100 : begin
-                        out <= 3'b001;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11111000 : begin
-                        out <= 3'b010;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11110000 : begin
-                        out <= 3'b011;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11100000 : begin
-                        out <= 3'b100;
-                        out_valid <= 1'b1;
-                        end
-                               8'b11000000 : begin
-                        out <= 3'b101;
-                        out_valid <= 1'b1;
-                        end
-                               8'b10000000 : begin
-                        out <= 3'b110;
-                        out_valid <= 1'b1;
-                        end
-                               8'b00000000 : begin
-                        out <= 3'b111;
-                        out_valid <= 1'b1;
-                        end
-                       default   :  begin
-                                               out <=3'b000;
-                                               out_valid <= 1'b0;
-                                               end
-                       endcase
-               end else begin
-                       out <=3'b000;
-                       out_valid <= 1'b0;
-               end
-       end
-
-
-endmodule\r
-\r
-module ctdc_enc_pos(
-                                                                       clk,
-                                                                       in,
-                                                                       in_valid,
-                                                                       out,
-                                                                       out_valid
-                                                                       ) /* synthesis syn_preserve= 1*/;
-
-input wire clk;
-input wire [7:0]in;
-input wire in_valid;
-output reg [2:0]out /*synthesis syn_preserve=1*/;
-output reg out_valid /*synthesis syn_preserve=1*/;
-
-
-       always @ (posedge clk)begin
-               if(in_valid)begin
-               case (in)       
-                               //8'b11111110 : begin\r
-                               ~8'b11111110 : begin
-                        out <= 3'b000;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11111100 : begin
-                        out <= 3'b001;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11111000 : begin
-                        out <= 3'b010;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11110000 : begin
-                        out <= 3'b011;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11100000 : begin
-                        out <= 3'b100;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b11000000 : begin
-                        out <= 3'b101;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b10000000 : begin
-                        out <= 3'b110;
-                        out_valid <= 1'b1;
-                        end
-                               ~8'b00000000 : begin
-                        out <= 3'b111;
-                        out_valid <= 1'b1;
-                        end
-                       default   :  begin
-                                               out <=3'b000;
-                                               out_valid <= 1'b0;
-                                               end
-                       endcase
-               end else begin
-                       out <=3'b000;
-                       out_valid <= 1'b0;
-               end
-       end
-
-
-endmodule
-

diff --git a/release.v b/release.v
deleted file mode 100644 (file)
index 56699fc..0000000
--- a/release.v
+++ /dev/null
@@ -1,226 +0,0 @@
-/*\r
-COMPONENT ctdc_channel_raw_out is PORT
-                                                                               (
-                                                                               reset_in:       IN STD_LOGIC;   --active high
-                                                                               pll_clks_in: IN STD_LOGIC_VECTOR(3 downto 0);   -- 0, 45, 90, 135 phase shifted
-                                                                               coarse_reset_in:        IN STD_LOGIC;   --active rising edge 
-                                                                               signal_in:      IN STD_LOGIC;                           --idle low
-                                                                               data_out:       OUT STD_LOGIC_VECTOR(23 downto 0);      --output on rising edge of pll_clks_in[0] 
-                                                                               data_valid_out: OUT STD_LOGIC   --active high; output on rising edge of pll_clks_in[0] 
-                                                                               pos_ready:      OUT STD_LOGIC;                          --debug; leave open
-                                                                               neg_ready:      OUT STD_LOGIC;                          --debug; leave open
-                                                                               coarse: OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               buf_pos:        OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               buf_neg:        OUT STD_LOGIC_VECTOR(8 downto 0);       --debug; leave open
-                                                                               );
-END COMPONENT; \r
-\r
-\r
-\r
-\r
-*/\r
-\r
-module ctdc_channel_raw_out (
-                                                                               reset_in, 
-                                                                               pll_clks_in, 
-                                                                               coarse_reset_in, 
-                                                                               signal_in,
-                                                                               data_out,
-                                                                               data_valid_out,\r
-                                                                               pos_ready,\r
-                                                                               neg_ready,\r
-                                                                               coarse,\r
-                                                                               buf_pos,
-                                                                               buf_neg
-                                                                               );
-                                                       
-       parameter COARSE_WIDTH = 9;
-       parameter TDC_WIDTH = 3;
-
-       input wire reset_in;
-       input wire [3:0]pll_clks_in;
-       input wire signal_in;
-       input wire coarse_reset_in;\r
-       output wire pos_ready;\r
-       output wire neg_ready;
-       \r
-       output reg [COARSE_WIDTH-1:0]coarse;\r
-\r
-       reg coarse_reset_dl;\r
-       assign coarse_reset_rising = ~coarse_reset_dl & coarse_reset_in;\r
-
-       wire [7:0]tdc_single;\r
-       wire tdc_single_valid;
-       output reg [(COARSE_WIDTH+TDC_WIDTH)*2-1 : 0]data_out;
-       output reg data_valid_out;
-       wire [1:0]raw_valid_vect;
-       
-       wire signal_gate /* synthesis syn_preserve= 1*/;
-       assign signal_gate = ~signal_in;
-       wire signal_gate_neg /* synthesis syn_preserve= 1*/;\r
-       \r
-       wire [2:0]enc_neg_out;
-       wire [2:0]enc_pos_out;\r
-       \r
-       output wire [8:0]buf_pos;\r
-       output wire [8:0]buf_neg;\r
-       
-        
-       ctdc_inv ctdc_inv_inst1(
-                                                       .in(signal_gate),
-                                                       .out(signal_gate_neg)
-       ) /* synthesis syn_black_box */;\r
-\r
-ctdc4ddr_dev ctdc_dev(
-                                               .trig(signal_gate_neg), 
-                                               .clks(pll_clks_in),
-                                               //.out_multi(tdc_multi),
-                                               //.out_half(tdc_half),
-                                               .out_single(tdc_single),
-                                               .out_single_valid(tdc_single_valid)
-                                                               ) /* synthesis syn_preserve= 1*/;
- ctdc_enc_neg ctdc_enc_neg_inst(
-                                                                       .clk(pll_clks_in[0]),
-                                                                       .in(tdc_single),
-                                                                       .in_valid(tdc_single_valid),
-                                                                       .out(enc_neg_out),
-                                                                       .out_valid(enc_neg_out_valid)
-                                                                       ) /* synthesis syn_preserve= 1*/;
-                                                                       
-ctdc_enc_pos ctdc_enc_pos_inst(
-                                                                       .clk(pll_clks_in[0]),
-                                                                       .in(tdc_single),
-                                                                       .in_valid(tdc_single_valid),
-                                                                       .out(enc_pos_out),
-                                                                       .out_valid(enc_pos_out_valid)
-                                                                       ) /* synthesis syn_preserve= 1*/;\r
-\r
-\r
-
-
-               
-        
-        reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_positive;
-        reg [COARSE_WIDTH+TDC_WIDTH-1:0]buf_negative;
-        reg buf_positive_ready;
-        reg buf_negative_ready;
-        //assign raw_valid_vect = {buf_positive_ready, buf_negative_ready};\r
-        \r
-       assign pos_ready = buf_positive_ready;
-       assign neg_ready = buf_negative_ready;
-
-       assign buf_pos = buf_positive[11:3];
-       assign buf_neg = buf_negative[11:3];\r
-        \r
-       always @(posedge pll_clks_in[0])begin\r
-               coarse_reset_dl <= coarse_reset_in;\r
-       end\r
-        \r
-        always @(posedge pll_clks_in[0])begin
-               if(reset_in | coarse_reset_rising)begin
-                       coarse <= 'b0;
-               end else begin\r
-                       coarse <= coarse +1;\r
-               end\r
-       end
-       
-       always @(posedge pll_clks_in[0])begin
-               if(reset_in)begin
-                       data_out <= 'b0;
-                       data_valid_out <= 'b0;
-               end else begin
-                       if(enc_pos_out_valid)begin
-                               buf_positive <= {coarse, enc_pos_out};
-                               buf_positive_ready <= 'b1;\r
-                               //data_out <= {'b00110010, coarse, enc_pos_out}; //temporary
-                       end else begin
-                               //
-                       end
-                       if(enc_neg_out_valid && buf_positive_ready)begin
-                               buf_negative <= {coarse, enc_neg_out};
-                               buf_negative_ready <= 'b1;
-                       end else begin
-                               //
-                       end
-                       if(buf_positive_ready && (buf_positive[COARSE_WIDTH-1 + TDC_WIDTH -: COARSE_WIDTH]) == coarse +'b1)begin
-                               buf_positive_ready <= 'b0;
-                       end
-                       if(buf_negative_ready && (buf_negative[COARSE_WIDTH-1 + TDC_WIDTH -: COARSE_WIDTH]) == coarse +'b1)begin
-                               buf_negative_ready <= 'b0;
-                       end
-                       if(buf_negative_ready & buf_positive_ready)begin
-                               buf_negative_ready <= 'b0;
-                               buf_positive_ready <= 'b0;
-                               data_out <= {buf_negative, buf_positive};
-                               data_valid_out <= 'b1;
-                       end else begin
-                               data_valid_out <= 'b0;
-                       end
-               end
-end
-
-endmodule\r
-\r
-\r
-\r
-module ctdc4ddr_dev(trig, clks, out_multi, out_half, out_single, out_single_valid) /* synthesis syn_useioff=0*/; 
-       input wire trig;
-       input wire[3:0]clks;
-       output wire [7:0]out_single /*synthesis syn_preserve= 1*/;\r
-       output wire [7:0]out_half /*synthesis syn_preserve= 1*/;\r
-       output wire [7:0]out_multi /*synthesis syn_preserve= 1*/;
-       output wire out_single_valid;\r
-       reg [7:0]multi /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;
-       reg [7:0]half_half /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;\r
-       reg [7:0]single /*synthesis syn_preserve=1 synthesis syn_useioff=0*/;
-       \r
-       wire single_half_change; \r
-       assign out_single_valid = single[0] ^ half_half[0];\r
-       
-       assign out_half = half_half;\r
-       assign out_multi = multi;\r
-       assign out_single = single;\r
-\r
-       ctdc_inv ctdc_inv_inst1(
-                                                       .in(trig),
-                                                       .out(trigger)
-       ) /* synthesis syn_black_box */;
-       generate
-               genvar i;
-               for(i=0;i<4;i=i+1)begin
-
-                       always @(posedge clks[i])begin
-                               multi[i] <= trigger /*synthesis syn_preserve= 1*/;
-                       end
-                       always @(negedge clks[i])begin
-                               multi[4+i] <= trigger /*synthesis syn_preserve= 1*/;
-                       end\r
-                       always @(posedge clks[0])begin\r
-                               half_half[i] <= multi[i];\r
-                       end\r
-                       always @(negedge clks[0])begin\r
-                               half_half[4+i] <= multi[4+i];
-                       end\r
-                       always @(posedge clks[0])begin\r
-                               single[i] <= half_half[i];\r
-                               single[4+i] <= half_half[4+i];\r
-                       end
-                       
-               end
-       endgenerate
-endmodule\r
-\r
-\r
-
-
-
-
-module ctdc_inv(in,out) /* synthesis syn_preserve=1 */;
-input wire in /* synthesis syn_keep=1 */;
-output wire out /* synthesis syn_keep=1 */;
-
-assign out = ~ in /* synthesis syn_keep=1 */;
-
-endmodule\r
-\r
-\r