statebits also to ADC clock domain

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index dc8d58ec5c52359e4391e8518c2d68b1b46f65e4..00a58763e3c7d09a74273f554318e2854e7029f4 100644 (file)
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -107,7 +107,7 @@ begin
   READOUT_TX.data_write <= RDO_write_main when rising_edge(CLK_SYS);
   READOUT_TX.data       <= RDO_data_main when rising_edge(CLK_SYS);
   readout_reset         <= CONTROL(12) when rising_edge(CLK_SYS);
-  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8));
+  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC);
 
   proc_readout : process
     variable channelselect : integer range 0 to 3;