USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
--standard values for output registers
REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
IPU_DATA_OUT : out std_logic_vector (31 downto 0);
IPU_DATAREADY_OUT : out std_logic;
IPU_READ_IN : in std_logic;
+ IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
IPU_BUSY_OUT : out std_logic;
- IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency
TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
TIMER_US_TICK_OUT : out std_logic; --1 tick every microsecond
-
STAT_DEBUG_1 : out std_logic_vector(31 downto 0);
- STAT_DEBUG_2 : out std_logic_vector(31 downto 0)
+ STAT_DEBUG_2 : out std_logic_vector(31 downto 0)
);
-end entity;
+end trb_net16_endpoint_hades_cts;
architecture trb_net16_endpoint_hades_cts_arch of trb_net16_endpoint_hades_cts is
signal MY_ADDRESS : std_logic_vector(15 downto 0);
signal STAT_MPLEX : std_logic_vector(31 downto 0);
-signal CTRL_MPLEX : std_logic_vector(31 downto 0);
+signal CTRL_MPLEX : std_logic_vector(31 downto 0):=(others => '0');
signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
begin
+
-------------------------------------------------------------------------------
--Media Interface Signals
-------------------------------------------------------------------------------
APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
-- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
-- Status and control port
CTRL_SEQNR_RESET => buf_REGIO_COMMON_CTRL_REG_OUT(10),
STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
-- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_SLAVE_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
-- Status and control port
CTRL_SEQNR_RESET => buf_REGIO_COMMON_CTRL_REG_OUT(10),
STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
buf_APL_PACKET_NUM_IN(5 downto 3) <= (others => '0');
buf_APL_DATAREADY_IN(1) <= '0';
buf_APL_SHORT_TRANSFER_IN(1) <= '1';
+ buf_APL_READ_IN(1) <= IPU_READ_IN;
buf_APL_SEND_IN(1) <= IPU_SEND_IN;
buf_APL_DTYPE_IN(7 downto 4) <= IPU_TYPE_IN;
buf_APL_ERROR_PATTERN_IN(47 downto 32) <= IPU_NUMBER_IN;
+
begin
+<<<<<<< trb_net16_hub_base.vhd
+ component trb_net16_iobuf is
+ generic (
+ IBUF_DEPTH : integer range 2 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT : out std_logic;
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_INIT_READ_IN : in std_logic;
+ MED_REPLY_DATAREADY_OUT : out std_logic;
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_REPLY_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);
+ -- Internal direction port
+ INT_INIT_DATAREADY_OUT : out std_logic;
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_IN : in std_logic;
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
+ -- Status and control port
+ STAT_GEN : out std_logic_vector (31 downto 0);
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
+ CTRL_GEN : in std_logic_vector (31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
+ );
+ end component;
+=======
---------------------------------------------------------------------
--Generate various reset signals
---------------------------------------------------------------------
reset_i <= RESET;
end if;
end process;
+>>>>>>> 1.57
gen_internal_reset : for i in 0 to MII_NUMBER-1 generate
type tlk_state_t is (RESETTING, WAIT_FOR_RX_LOCK, WAIT_FOR_TX_ALLOW, WORKING);
signal current_state, next_state : tlk_state_t;
- signal next_tx_allow, next_rx_allow : std_logic;
+ signal next_tx_allow, next_rx_allow : std_logic:='1';
signal counter, next_counter : std_logic_vector(28 downto 0);
signal next_internal_reset : std_logic;
signal buf_MED_ERROR_OUT, next_MED_ERROR_OUT : std_logic_vector(2 downto 0);
--Sender
-------------
-U_DCM_Transmitter: DCM
- generic map(
- CLKIN_PERIOD => 10.00, -- 30.30ns
- STARTUP_WAIT => FALSE,
- PHASE_SHIFT => 0,
- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
- CLKOUT_PHASE_SHIFT => "FIXED"
- )
- port map (
- CLKIN => TLK_CLK,
- CLKFB => FB_CLK,
- DSSEN => '0',
- PSINCDEC => '0',
- PSEN => '0',
- PSCLK => '0',
- RST => RESET,
- CLK0 => CLK_FB_Out, -- for feedback
- CLK90=> open,
- LOCKED => open
- );
+U_DCM_Transmitter: DCM --no_sim--
+ generic map( --no_sim--
+ CLKIN_PERIOD => 10.00, -- 30.30ns--no_sim--
+ STARTUP_WAIT => FALSE,--no_sim--
+ PHASE_SHIFT => 0,--no_sim--
+ DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",--no_sim--
+ CLKOUT_PHASE_SHIFT => "FIXED"--no_sim--
+ )--no_sim--
+ port map (--no_sim--
+ CLKIN => TLK_CLK,--no_sim--
+ CLKFB => FB_CLK,--no_sim--
+ DSSEN => '0',--no_sim--
+ PSINCDEC => '0',--no_sim--
+ PSEN => '0',--no_sim--
+ PSCLK => '0',--no_sim--
+ RST => RESET,--no_sim--
+ CLK0 => CLK_FB_Out, -- for feedback--no_sim--
+ CLK90=> open,--no_sim--
+ LOCKED => open--no_sim--
+ );--no_sim--
--
-U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg);
-U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);
-
+U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg);--no_sim--
+U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim--
+--sim--TLK_CLK_neg <= not TLK_CLK;
FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport
generic map(
TLK_TX_ER <= '0';
- process(TLK_CLK_neg)
+ process(TLK_CLK_neg,reg_TXD,reg_TX_EN)
begin
if rising_edge(TLK_CLK_neg) then
TLK_TX_EN <= reg_TX_EN;
end if;
when WORKING =>
next_MED_ERROR_OUT <= ERROR_OK;
+ --sim-- next_tx_allow <='1';
+ --sim-- next_rx_allow <= '1';
next_internal_reset <= '0';
end case;
if reg_RX_ER = '1' and reg_RX_DV = '0' and internal_reset = '0' then
begin
if rising_edge(CLK) then
if RESET = '1' then
- current_state <= RESETTING;
+ current_state <= RESETTING;--no_sim--
+--sim-- current_state <= WORKING;
internal_reset <= '1';
buf_MED_ERROR_OUT <= ERROR_NC;
else
jspc29 / trbnet.git / commitdiff