SED and statistics logic is included

diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd
index bde75078c063bb850a891a1114944887a428577e..eae6e56cf0dddb3deff58e350e3f2f5b46d26670 100644 (file)
--- a/32PinAddOn/config.vhd
+++ b/32PinAddOn/config.vhd
@@ -19,8 +19,14 @@ package config is
     constant INCLUDE_SPI            : integer := c_YES;
 
 --Add logic to generate configurable trigger signal from input signals.
-    constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;
-    
+    constant INCLUDE_TRIGGER_LOGIC  : integer := c_NO;
+
+--Do histos of all inputs
+  constant INCLUDE_STATISTICS : integer := c_YES;
+
+--number of real inputs to the FPGA
+  constant PHYSICAL_INPUTS : integer := 32;
+
 --Run wih 125 MHz instead of 100 MHz
     constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!
     

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj
index 88505111782abfd38763dbed35125bf5b1fbba20..68f3916afd07f6dd49557f590e5d35d8541eded5 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.prj
+++ b/32PinAddOn/trb3_periph_32PinAddOn.prj
@@ -153,7 +153,6 @@ add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd"
 add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd"
 add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd"
 add_file -vhdl -lib "work" "currentRelease/Readout.vhd"
-add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd"
 add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd"
 add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib "work" "currentRelease/TDC.vhd"
@@ -161,10 +160,12 @@ add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd"
 add_file -vhdl -lib "work" "currentRelease/up_counter.vhd"
 add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
 add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/hit_inv.vhd"
+add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib "work" "../base/code/input_statistics.vhd"
+add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
 
 add_file -vhdl -lib "work" "trb3_periph_32PinAddOn.vhd"
 

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd
index c660610f8b3c1a563e7f8a3d742ad4af2a5ed156..08d89217e8a4c79e75ac39d78e7f3d2cf38a1cb6 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.vhd
+++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd
@@ -257,6 +257,24 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is
   signal trig_nack  : std_logic                     := '0';
   signal trig_addr  : std_logic_vector(15 downto 0) := (others => '0');
 
+  signal stat_out   : std_logic_vector(3 downto 0);
+  signal stat_din   : std_logic_vector(31 downto 0);
+  signal stat_dout  : std_logic_vector(31 downto 0);
+  signal stat_write : std_logic                     := '0';
+  signal stat_read  : std_logic                     := '0';
+  signal stat_ack   : std_logic                     := '0';
+  signal stat_nack  : std_logic                     := '0';
+  signal stat_addr  : std_logic_vector(15 downto 0) := (others => '0');
+
+  signal sed_error  : std_logic;
+  signal sed_din    : std_logic_vector(31 downto 0);
+  signal sed_dout   : std_logic_vector(31 downto 0);
+  signal sed_write  : std_logic := '0';
+  signal sed_read   : std_logic := '0';
+  signal sed_ack    : std_logic := '0';
+  signal sed_nack   : std_logic := '0';
+  signal sed_addr   : std_logic_vector(15 downto 0) := (others => '0');  
+
   --TDC
   signal hit_in_i         : std_logic_vector(64 downto 1);
   signal logic_analyser_i : std_logic_vector(15 downto 0);
@@ -296,7 +314,7 @@ begin
       CLKOK => clk_200_i,
       LOCK  => pll_lock
       );
-  
+
   -- internal oscillator with frequency of 2.5MHz for tdc calibration
   OSCInst0 : OSCF
     port map (
@@ -475,9 +493,15 @@ begin
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER    => 10,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0)
+      PORT_NUMBER                 => 9,
+      PORT_ADDRESSES              => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100",
+                                --5  => x"c200", 6  => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00",
+                                --10 => x"cf80", 11 => x"d500", others => x"0000"),
+                                5 => x"c800", 6 => x"cf00", 7 => x"cf80", 8 => x"d500", others => x"0000"),
+      PORT_ADDR_MASK              => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5,
+                                --5  => 7, 6  => 7, 7 => 7, 8 => 3, 9 => 6,
+                                --10 => 7, 11 => 4, others => 0)
+                                5 => 3, 6 => 6, 7 => 7, 8 => 4, others => 0)
       )
     port map(
       CLK   => clk_100_i,
@@ -554,66 +578,89 @@ begin
       BUS_WRITE_ACK_IN(4)                 => '0',
       BUS_NO_MORE_DATA_IN(4)              => '0',
       BUS_UNKNOWN_ADDR_IN(4)              => srb_invalid,
-      --Encoder Start Registers
-      BUS_READ_ENABLE_OUT(5)              => esb_read_en,
-      BUS_WRITE_ENABLE_OUT(5)             => esb_write_en,
-      BUS_DATA_OUT(5*32+31 downto 5*32)   => open,
-      BUS_ADDR_OUT(5*16+6 downto 5*16)    => esb_addr,
-      BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
+      ----Encoder Start Registers
+      --BUS_READ_ENABLE_OUT(5)              => esb_read_en,
+      --BUS_WRITE_ENABLE_OUT(5)             => esb_write_en,
+      --BUS_DATA_OUT(5*32+31 downto 5*32)   => open,
+      --BUS_ADDR_OUT(5*16+6 downto 5*16)    => esb_addr,
+      --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
+      --BUS_TIMEOUT_OUT(5)                  => open,
+      --BUS_DATA_IN(5*32+31 downto 5*32)    => esb_data_out,
+      --BUS_DATAREADY_IN(5)                 => esb_data_ready,
+      --BUS_WRITE_ACK_IN(5)                 => '0',
+      --BUS_NO_MORE_DATA_IN(5)              => '0',
+      --BUS_UNKNOWN_ADDR_IN(5)              => esb_invalid,
+      ----Fifo Write Registers
+      --BUS_READ_ENABLE_OUT(6)              => efb_read_en,
+      --BUS_WRITE_ENABLE_OUT(6)             => efb_write_en,
+      --BUS_DATA_OUT(6*32+31 downto 6*32)   => open,
+      --BUS_ADDR_OUT(6*16+6 downto 6*16)    => efb_addr,
+      --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
+      --BUS_TIMEOUT_OUT(6)                  => open,
+      --BUS_DATA_IN(6*32+31 downto 6*32)    => efb_data_out,
+      --BUS_DATAREADY_IN(6)                 => efb_data_ready,
+      --BUS_WRITE_ACK_IN(6)                 => '0',
+      --BUS_NO_MORE_DATA_IN(6)              => '0',
+      --BUS_UNKNOWN_ADDR_IN(6)              => efb_invalid,
+      ----Lost Hit Registers
+      --BUS_READ_ENABLE_OUT(7)              => lhb_read_en,
+      --BUS_WRITE_ENABLE_OUT(7)             => lhb_write_en,
+      --BUS_DATA_OUT(7*32+31 downto 7*32)   => open,
+      --BUS_ADDR_OUT(7*16+6 downto 7*16)    => lhb_addr,
+      --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open,
+      --BUS_TIMEOUT_OUT(7)                  => open,
+      --BUS_DATA_IN(7*32+31 downto 7*32)    => lhb_data_out,
+      --BUS_DATAREADY_IN(7)                 => lhb_data_ready,
+      --BUS_WRITE_ACK_IN(7)                 => '0',
+      --BUS_NO_MORE_DATA_IN(7)              => '0',
+      --BUS_UNKNOWN_ADDR_IN(7)              => lhb_invalid,
+      --TDC config registers
+      BUS_READ_ENABLE_OUT(5)              => tdc_ctrl_read,
+      BUS_WRITE_ENABLE_OUT(5)             => tdc_ctrl_write,
+      BUS_DATA_OUT(5*32+31 downto 5*32)   => tdc_ctrl_data_in,
+      BUS_ADDR_OUT(5*16+2 downto 5*16)    => tdc_ctrl_addr,
+      BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open,
       BUS_TIMEOUT_OUT(5)                  => open,
-      BUS_DATA_IN(5*32+31 downto 5*32)    => esb_data_out,
-      BUS_DATAREADY_IN(5)                 => esb_data_ready,
-      BUS_WRITE_ACK_IN(5)                 => '0',
+      BUS_DATA_IN(5*32+31 downto 5*32)    => tdc_ctrl_data_out,
+      BUS_DATAREADY_IN(5)                 => last_tdc_ctrl_read,
+      BUS_WRITE_ACK_IN(5)                 => tdc_ctrl_write,
       BUS_NO_MORE_DATA_IN(5)              => '0',
-      BUS_UNKNOWN_ADDR_IN(5)              => esb_invalid,
-      --Fifo Write Registers
-      BUS_READ_ENABLE_OUT(6)              => efb_read_en,
-      BUS_WRITE_ENABLE_OUT(6)             => efb_write_en,
-      BUS_DATA_OUT(6*32+31 downto 6*32)   => open,
-      BUS_ADDR_OUT(6*16+6 downto 6*16)    => efb_addr,
-      BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
+      BUS_UNKNOWN_ADDR_IN(5)              => '0',
+      --Trigger logic registers
+      BUS_READ_ENABLE_OUT(6)              => trig_read,
+      BUS_WRITE_ENABLE_OUT(6)             => trig_write,
+      BUS_DATA_OUT(6*32+31 downto 6*32)   => trig_din,
+      BUS_ADDR_OUT(6*16+15 downto 6*16)   => trig_addr,
       BUS_TIMEOUT_OUT(6)                  => open,
-      BUS_DATA_IN(6*32+31 downto 6*32)    => efb_data_out,
-      BUS_DATAREADY_IN(6)                 => efb_data_ready,
-      BUS_WRITE_ACK_IN(6)                 => '0',
+      BUS_DATA_IN(6*32+31 downto 6*32)    => trig_dout,
+      BUS_DATAREADY_IN(6)                 => trig_ack,
+      BUS_WRITE_ACK_IN(6)                 => trig_ack,
       BUS_NO_MORE_DATA_IN(6)              => '0',
-      BUS_UNKNOWN_ADDR_IN(6)              => efb_invalid,
-      --Lost Hit Registers
-      BUS_READ_ENABLE_OUT(7)              => lhb_read_en,
-      BUS_WRITE_ENABLE_OUT(7)             => lhb_write_en,
-      BUS_DATA_OUT(7*32+31 downto 7*32)   => open,
-      BUS_ADDR_OUT(7*16+6 downto 7*16)    => lhb_addr,
-      BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open,
+      BUS_UNKNOWN_ADDR_IN(6)              => trig_nack,
+      --Input statistics
+      BUS_READ_ENABLE_OUT(7)              => stat_read,
+      BUS_WRITE_ENABLE_OUT(7)             => stat_write,
+      BUS_DATA_OUT(7*32+31 downto 7*32)   => stat_din,
+      BUS_ADDR_OUT(7*16+15 downto 7*16)   => stat_addr,
       BUS_TIMEOUT_OUT(7)                  => open,
-      BUS_DATA_IN(7*32+31 downto 7*32)    => lhb_data_out,
-      BUS_DATAREADY_IN(7)                 => lhb_data_ready,
-      BUS_WRITE_ACK_IN(7)                 => '0',
+      BUS_DATA_IN(7*32+31 downto 7*32)    => stat_dout,
+      BUS_DATAREADY_IN(7)                 => stat_ack,
+      BUS_WRITE_ACK_IN(7)                 => stat_ack,
       BUS_NO_MORE_DATA_IN(7)              => '0',
-      BUS_UNKNOWN_ADDR_IN(7)              => lhb_invalid,
-      --TDC config registers
-      BUS_READ_ENABLE_OUT(8)              => tdc_ctrl_read,
-      BUS_WRITE_ENABLE_OUT(8)             => tdc_ctrl_write,
-      BUS_DATA_OUT(8*32+31 downto 8*32)   => tdc_ctrl_data_in,
-      BUS_ADDR_OUT(8*16+2 downto 8*16)    => tdc_ctrl_addr,
-      BUS_ADDR_OUT(8*16+15 downto 8*16+3) => open,
+      BUS_UNKNOWN_ADDR_IN(7)              => stat_nack,
+      --SEU Detection
+      BUS_READ_ENABLE_OUT(8)              => sed_read,
+      BUS_WRITE_ENABLE_OUT(8)             => sed_write,
+      BUS_DATA_OUT(8*32+31 downto 8*32)   => sed_din,
+      BUS_ADDR_OUT(8*16+15 downto 8*16)   => sed_addr,
       BUS_TIMEOUT_OUT(8)                  => open,
-      BUS_DATA_IN(8*32+31 downto 8*32)    => tdc_ctrl_data_out,
-      BUS_DATAREADY_IN(8)                 => last_tdc_ctrl_read,
-      BUS_WRITE_ACK_IN(8)                 => tdc_ctrl_write,
+      BUS_DATA_IN(8*32+31 downto 8*32)    => sed_dout,
+      BUS_DATAREADY_IN(8)                 => sed_ack,
+      BUS_WRITE_ACK_IN(8)                 => sed_ack,
       BUS_NO_MORE_DATA_IN(8)              => '0',
-      BUS_UNKNOWN_ADDR_IN(8)              => '0',
-      --Trigger logic registers
-      BUS_READ_ENABLE_OUT(9)              => trig_read,
-      BUS_WRITE_ENABLE_OUT(9)             => trig_write,
-      BUS_DATA_OUT(9*32+31 downto 9*32)   => trig_din,
-      BUS_ADDR_OUT(9*16+15 downto 9*16)   => trig_addr,
-      BUS_TIMEOUT_OUT(9)                  => open,
-      BUS_DATA_IN(9*32+31 downto 9*32)    => trig_dout,
-      BUS_DATAREADY_IN(9)                 => trig_ack,
-      BUS_WRITE_ACK_IN(9)                 => trig_ack,
-      BUS_NO_MORE_DATA_IN(9)              => '0',
-      BUS_UNKNOWN_ADDR_IN(9)              => trig_nack,
-      STAT_DEBUG                          => open
+      BUS_UNKNOWN_ADDR_IN(8)              => sed_nack,
+
+      STAT_DEBUG => open
       );
 
   PROC_TDC_CTRL_REG : process
@@ -742,6 +789,55 @@ begin
     FPGA5_COMM(10 downto 7) <= trig_out;
   end generate;
 
+---------------------------------------------------------------------------
+-- Input Statistics
+---------------------------------------------------------------------------
+  gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
+
+    THE_STAT_LOGIC : entity work.input_statistics
+      generic map(
+        INPUTS => PHYSICAL_INPUTS
+        )
+      port map(
+        CLK => clk_100_i,
+
+        INPUT => INP(PHYSICAL_INPUTS downto 1),
+
+        DATA_IN  => stat_din,
+        DATA_OUT => stat_dout,
+        WRITE_IN => stat_write,
+        READ_IN  => stat_read,
+        ACK_OUT  => stat_ack,
+        NACK_OUT => stat_nack,
+        ADDR_IN  => stat_addr
+        );
+  end generate;
+
+---------------------------------------------------------------------------
+-- SED Detection
+---------------------------------------------------------------------------
+  THE_SED : entity work.sedcheck
+    port map(
+      CLK       => clk_100_i,
+      ERROR_OUT => sed_error,
+
+      DATA_IN  => sed_din,
+      DATA_OUT => sed_dout,
+      WRITE_IN => sed_write,
+      READ_IN  => sed_read,
+      ACK_OUT  => sed_ack,
+      NACK_OUT => sed_nack,
+      ADDR_IN  => sed_addr
+      );
+
+-- THE_SED : entity work.sedcheck 
+--   port map(
+--     CLK        => clk_100_i,
+--     ERROR_OUT  => sed_error,
+--     i_rst_p    => i_rst_p,
+--     STATUS_OUT => TEST_LINE(11 downto 0)
+--     ); 
+
 ---------------------------------------------------------------------------
 -- Reboot FPGA
 ---------------------------------------------------------------------------
@@ -774,7 +870,7 @@ begin
   THE_TDC : TDC
     generic map (
       CHANNEL_NUMBER => NUM_TDC_CHANNELS,   -- Number of TDC channels
-      STATUS_REG_NR  => 20,             -- Number of status regs
+      STATUS_REG_NR  => 21,             -- Number of status regs
       CONTROL_REG_NR => 6,  -- Number of control regs - higher than 8 check tdc_ctrl_addr
       TDC_VERSION    => x"160",         -- TDC version number
       DEBUG          => c_YES,
@@ -785,7 +881,7 @@ begin
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
       HIT_IN                => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CALIBRATION       => osc_int,  -- Hits for calibrating the TDC
+      HIT_CALIBRATION       => osc_int,     -- Hits for calibrating the TDC
       TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --