merge logicbox.vhd

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index 92e9d4f81742e4408200db2f0adbeab18675035d..b59dea1266c29bd4fb6e8d1ac26b75c7af54136e 100644 (file)
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -69,7 +69,7 @@ architecture arch of logicbox is
   signal pulser_pulslength : unsigned(27 downto 0) := x"0000001";\r
   signal pulser_periodlength_buffer : unsigned(27 downto 0);\r
   signal pulser_pulslength_buffer : unsigned(27 downto 0);\r
-  \r
+\r
   --UFM\r
   -------------------------------------\r
   signal ufm_cmd : std_logic := '0'; --CMD=0 => Read; CMD=1 => Write\r
@@ -80,6 +80,7 @@ architecture arch of logicbox is
   signal ufm_bus_ready_out : std_logic;\r
   signal ufm_bus_ready_in : std_logic;\r
   signal ufm_busy : std_logic;\r
+\r
   \r
   component OSCH\r
     generic (NOM_FREQ: string := "133.00");\r
@@ -417,6 +418,21 @@ end process;
 --     DEBUG      => sed_debug\r
 --     );\r
 \r
+--   process begin\r
+--     wait until rising_edge(clk_i);\r
+--     if counter = x"40" then\r
+--       counter <= 0;\r
+--       pwm <= '1';\r
+--     else  \r
+--       counter <= counter + 1;\r
+--       pwm <= '0';\r
+--     end if; \r
+--   end process;\r
+--     \r
+--     \r
+--     OUTPUT <= '0' & pwm & '0' & pwm;\r
+--     CONTROLO <= pwm;\r
+    \r
 end architecture;\r
 \r
        \r