Revert "Refine delay"

This reverts commit cc71945c5c1013c7d2939b360715862468438c7f.

diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd
index 85b6b690515c9b6f0fadb2e23948669d3a64cd71..82980b0e51015a08a8fdef05cc9ae0114f983bab 100644 (file)
--- a/ADC/source/adc_processor_cfd_ch.vhd
+++ b/ADC/source/adc_processor_cfd_ch.vhd
@@ -78,9 +78,6 @@ architecture arch of adc_processor_cfd_ch is
   signal delay_cfd_in  : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0');
   signal delay_cfd_out : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0');
 
-  type delay_sub_t is array (1 downto 0) of subtracted_thresh_t;
-  signal delay_sub     : delay_sub_t                         := (others => subtracted_thresh_t_INIT);
-  
   signal prod, prod_invert : product_thresh_t := product_thresh_t_INIT;
   signal prod_delay        : signed(RESOLUTION_PROD - 1 downto 0) := (others => '0');
 
@@ -203,17 +200,13 @@ begin
     prod_delay   <= resize(prod_delay_s, RESOLUTION_PROD); -- get rid of extra bit again
 
     -- undelayed chain: input is subtracted signal
-    -- however, undelayed chain is also a little bit delayed
-    -- to account for in/out registers of delay chain above
-    delay_sub(0) <= subtracted;
-    delay_sub(1) <= delay_sub(0);
     mult_s      := signed(resize(CONF.CFDMult, CONF.CFDMult'length + 1)); -- add extra zero sign bit
-    prod_s      := mult_s * delay_sub(1).value;
+    prod_s      := mult_s * subtracted.value;
     prod.value  <= resize(prod_s, RESOLUTION_PROD); -- get rid of extra bit again
-    prod.thresh <= delay_sub(1).thresh;
-    
+    prod.thresh <= subtracted.thresh;
+
     -- invert
-    prod_invert.value  <= -delay_prod.value;
+    prod_invert.value  <= -prod.value;
     prod_invert.thresh <= prod.thresh;
 
     -- add both signals to generate the bipolar cfd signal