Adding the ETM to the CTS

diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd
index b20920327feaab233f637870a2dee7d3eb38b308..f7149c1f79362651aedfda96a23a5f016e4894cd 100755 (executable)
--- a/cts/source/cts_pkg.vhd
+++ b/cts/source/cts_pkg.vhd
@@ -125,6 +125,7 @@ package cts_pkg is
       --Registers / Debug    
       CONTROL_REG_IN : in  std_logic_vector(31 downto 0);
       STATUS_REG_OUT : out std_logic_vector(31 downto 0);
+      HEADER_REG_OUT : out std_logic_vector(1 downto 0);
       DEBUG          : out std_logic_vector(31 downto 0)    
       );
    end component;   
@@ -145,6 +146,7 @@ package cts_pkg is
                         FINISHED_OUT                    : out std_logic;
                         CONTROL_REG_IN          : in    std_logic_vector(31 downto 0);
                         STATUS_REG_OUT          : out std_logic_vector(31 downto 0) := (others => '0');
+                        HEADER_REG_OUT    : out std_logic_vector(1 downto 0);
                         DEBUG                                           : out std_logic_vector(31 downto 0));
         end component mainz_a2_recv;
         

diff --git a/cts/source/mainz_a2_recv.vhd b/cts/source/mainz_a2_recv.vhd
index 5eb5a7b94fef13a339689087524da0281c2561b8..1786303d0bc8668846bd9765284b0385ef6ad92b 100644 (file)
--- a/cts/source/mainz_a2_recv.vhd
+++ b/cts/source/mainz_a2_recv.vhd
@@ -33,6 +33,7 @@ entity mainz_a2_recv is
                                                                                                                                                                --Registers / Debug              
                CONTROL_REG_IN : in      std_logic_vector(31 downto 0);
                STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+               HEADER_REG_OUT    : out std_logic_vector(1 downto 0);
                DEBUG                                    : out std_logic_vector(31 downto 0)
                );
 end entity;
@@ -86,9 +87,8 @@ architecture arch1 of mainz_a2_recv is
        signal config_rdo_disable_i : std_logic;
 
 begin
-       timer_tick_1us <= TIMER_TICK_1US_IN;
-
-       reg_SERIAL_IN <= SERIAL_IN when rising_edge(CLK);
+       -- we tell the CTS that we send four words of over DATA_OUT
+       HEADER_REG_OUT <= b"10"; 
 
                                                                                                                                                                --PROC_FIRST_BITS : process
                                                                                                                                                                --begin

diff --git a/cts/source/mbs_vulom_recv.vhd b/cts/source/mbs_vulom_recv.vhd
index a5b18633d891de343bef51f790c7f1592e39420f..bcc1325ae2e3b7a642b893bad6224299235a389d 100644 (file)
--- a/cts/source/mbs_vulom_recv.vhd
+++ b/cts/source/mbs_vulom_recv.vhd
@@ -30,6 +30,7 @@ entity mbs_vulom_recv is
     --Registers / Debug    
     CONTROL_REG_IN : in  std_logic_vector(31 downto 0);
     STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+    HEADER_REG_OUT : out std_logic_vector(1 downto 0);
     DEBUG          : out std_logic_vector(31 downto 0)    
     );
 end entity;
@@ -80,6 +81,8 @@ signal config_rdo_disable_i : std_logic;
 
 begin
 
+-- we tell the CTS that we send one word of over DATA_OUT
+HEADER_REG_OUT <= b"01"; 
 
 reg_MBS_IN <= MBS_IN when rising_edge(CLK_200);
 
@@ -192,4 +195,4 @@ config_rdo_disable_i <= CONTROL_REG_IN(0);
 STATUS_REG_OUT <= error_reg & '0' & std_logic_vector(to_unsigned(bitcnt,6)) & number_reg;
 DEBUG <= x"00000000"; -- & done & '0' & shift_reg(13 downto 0);
 
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 0f11f5e0e8e9039ee6b6e4f2084dfeedcc2908ac..88e042c2f7db984c6afe41e7aa3d8f5820f1fdb0 100644 (file)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -306,6 +306,7 @@ architecture trb3_central_arch of trb3_central is
   signal cts_ext_status              : std_logic_vector(31 downto 0) := (others => '0');
   signal cts_ext_control             : std_logic_vector(31 downto 0);
   signal cts_ext_debug               : std_logic_vector(31 downto 0);
+  signal cts_ext_header                                                 : std_logic_vector(1 downto 0);
 
   signal cts_rdo_additional_data            : std_logic_vector(31+INCLUDE_TDC*32 downto 0);
   signal cts_rdo_additional_write           : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0');
@@ -430,6 +431,7 @@ begin
 
       CONTROL_REG_IN => cts_ext_control,
       STATUS_REG_OUT => cts_ext_status,
+      HEADER_REG_OUT => cts_ext_header,
       
       DEBUG => cts_ext_debug
    );
@@ -454,6 +456,7 @@ begin
 
                                CONTROL_REG_IN => cts_ext_control,
                                STATUS_REG_OUT => cts_ext_status,
+                               HEADER_REG_OUT => cts_ext_header,
                                
                                DEBUG => cts_ext_debug
                                );
@@ -482,7 +485,8 @@ begin
       
       EXT_TRIGGER_IN => cts_ext_trigger,
       EXT_STATUS_IN  => cts_ext_status,
-      EXT_CONTROL_OUT => cts_ext_control, 
+      EXT_CONTROL_OUT => cts_ext_control,
+      EXT_HEADER_BITS_IN => cts_ext_header,
       
       CTS_TRG_SEND_OUT => cts_trg_send,
       CTS_TRG_TYPE_OUT => cts_trg_type,