Changes to lpf constraint file (correcting paths)

Currently trying to get timing closure in CLK_GPLL_RIGHT.
For unknown reasons the compiler claims that this is NOT located on a dedicated clock-site and therefor get's excessive delay.
According to "LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide" page 10-38, Table 10-17, it is a preferred pad for feedback to the PLL.

Synthesys is complaining about undeclared clocks. Added soda_source_synconstraints.fdc. No success yet

diff --git a/soda_source.lpf b/soda_source.lpf
index 068461cc7fb104dd316bc612812c46357bf6ce53..1d28f36cc0d8c9aa497d5aabaef6c50d09780fe2 100644 (file)
--- a/soda_source.lpf
+++ b/soda_source.lpf
@@ -1,268 +1,220 @@
-rvl_alias "clk_raw_internal" "clk_raw_internal";
+RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
+RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
+RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
+RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
-
 #################################################################
 # Basic Settings
 #################################################################
-
 #   SYSCONFIG MCCLK_FREQ = 2.5;
-
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-
+#  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+#  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+#  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 #################################################################
 # Clock I/O
 #################################################################
-LOCATE COMP  "CLK_PCLK_RIGHT"       SITE "U20";
-LOCATE COMP  "CLK_PCLK_LEFT"        SITE "M4";
-LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "W1";
-LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
-
+#LOCATE COMP  "CLK_PCLK_RIGHT"       SITE "U20";
+#LOCATE COMP  "CLK_PCLK_LEFT"        SITE "M4";
+#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
+#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
+LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
+#LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
 DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
-
-
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
 #################################################################
 # Trigger I/O
 #################################################################
-
 #Trigger from fan-out
-LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
-LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
-
-
-
-
+#LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
+#LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
+#IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
+#IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
 #################################################################
 # To central FPGA
 #################################################################
-
-LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
-LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
-LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
-LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
-LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
-LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
-LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
-LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
-LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
-LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
-LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
-LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
 DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
 IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-LOCATE COMP  "TEST_LINE_0"   SITE "A5";
-LOCATE COMP  "TEST_LINE_1"   SITE "A6";
-LOCATE COMP  "TEST_LINE_2"   SITE "G8";
-LOCATE COMP  "TEST_LINE_3"   SITE "F9";
-LOCATE COMP  "TEST_LINE_4"   SITE "D9";
-LOCATE COMP  "TEST_LINE_5"   SITE "D10";
-LOCATE COMP  "TEST_LINE_6"   SITE "F10";
-LOCATE COMP  "TEST_LINE_7"   SITE "E10";
-LOCATE COMP  "TEST_LINE_8"   SITE "A8";
-LOCATE COMP  "TEST_LINE_9"   SITE "B8";
-LOCATE COMP  "TEST_LINE_10"  SITE "G10";
-LOCATE COMP  "TEST_LINE_11"  SITE "G9";
-LOCATE COMP  "TEST_LINE_12"  SITE "C9";
-LOCATE COMP  "TEST_LINE_13"  SITE "C10";
-LOCATE COMP  "TEST_LINE_14"  SITE "H10";
-LOCATE COMP  "TEST_LINE_15"  SITE "H11";
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
 DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
-
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
 #################################################################
 # Connection to AddOn
 #################################################################
-
-LOCATE COMP  "LED_LINKOK_1"  SITE "P1";     #DQLL0_0   #1
-LOCATE COMP  "LED_RX_1"      SITE "P2";     #DQLL0_1   #3
-LOCATE COMP  "LED_TX_1"      SITE "T2";     #DQLL0_2   #5
-LOCATE COMP  "SFP_MOD0_1"    SITE "U3";     #DQLL0_3   #7
-LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP  "SFP_TXDIS_1"   SITE "P3";     #DQSLL0_C  #15
-LOCATE COMP  "SFP_LOS_1"     SITE "P5";     #DQLL0_6   #17
-LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-
-LOCATE COMP  "LED_LINKOK_2"  SITE "N5";     #DQLL0_8   #21
-LOCATE COMP  "LED_RX_2"      SITE "N6";     #DQLL0_9   #23
-LOCATE COMP  "LED_TX_2"      SITE "AC2";    #DQLL2_0   #25
-LOCATE COMP  "SFP_MOD0_2"    SITE "AC3";    #DQLL2_1   #27
-LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP  "SFP_TXDIS_2"   SITE "AA2";    #DQLL2_5   #35
-LOCATE COMP  "SFP_LOS_2"     SITE "W7";     #DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-
-LOCATE COMP  "LED_LINKOK_3"    SITE "AD1";    #DQLL3_0   #2
-LOCATE COMP  "LED_RX_3"        SITE "AD2";    #DQLL3_1   #4
-LOCATE COMP  "LED_TX_3"        SITE "AB5";    #DQLL3_2   #6
-LOCATE COMP  "SFP_MOD0_3"      SITE "AB6";    #DQLL3_3   #8
-LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP  "SFP_TXDIS_3"     SITE "Y7";     #DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP  "SFP_LOS_3"       SITE "AA3";    #DQLL3_6   #18
-LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-
-LOCATE COMP  "LED_LINKOK_4"    SITE "W8";     #DQLL3_8   #22
-LOCATE COMP  "LED_RX_4"        SITE "W9";     #DQLL3_9   #24
-LOCATE COMP  "LED_TX_4"        SITE "V1";     #DQLL1_0   #26
-LOCATE COMP  "SFP_MOD0_4"      SITE "U2";     #DQLL1_1   #28
-LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP  "SFP_TXDIS_4"     SITE "R3";     #DQLL1_5   #36
-LOCATE COMP  "SFP_LOS_4"       SITE "T3";     #DQSLL1_T  #38
-LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-
-
-
-LOCATE COMP  "LED_LINKOK_5"   SITE "W23";    #DQLR1_0   #169
-LOCATE COMP  "LED_RX_5"       SITE "W22";    #DQLR1_1   #171
-LOCATE COMP  "LED_TX_5"       SITE "AA25";   #DQLR1_2   #173
-LOCATE COMP  "SFP_MOD0_5"     SITE "Y24";    #DQLR1_3   #175
-LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP  "SFP_TXDIS_5"    SITE "W20";    #DQSLR1_C  #183
-LOCATE COMP  "SFP_LOS_5"      SITE "AA24";   #DQLR1_6   #185
-LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-
-LOCATE COMP  "LED_LINKOK_6"   SITE "R25";    #DQLR2_0   #170
-LOCATE COMP  "LED_RX_6"       SITE "R26";    #DQLR2_1   #172
-LOCATE COMP  "LED_TX_6"       SITE "T25";    #DQLR2_2   #174
-LOCATE COMP  "SFP_MOD0_6"     SITE "T24";    #DQLR2_3   #176
-LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP  "SFP_TXDIS_6"    SITE "V22";    #DQSLR2_C  #184
-LOCATE COMP  "SFP_LOS_6"      SITE "U24";    #DQLR2_6   #186
-LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-
-
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
+#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
+#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
+#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
+#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
+#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
+#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
+#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
+#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
+#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
+#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
+#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
+#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
+#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
+#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
+#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
+#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
+#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
+#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
+#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
+#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
+#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
+#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
+#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
+#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
 DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
-
-
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
 #################################################################
 # Additional Lines to AddOn
 #################################################################
-
 #Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
 #all lines are input only
 #line 4/5 go to PLL input
-LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-
+#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
+#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
+#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
+#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
+#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
+#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
 #################################################################
 # Flash ROM and Reboot
 #################################################################
-
-LOCATE COMP  "FLASH_CLK"    SITE "B12";
-LOCATE COMP  "FLASH_CS"   SITE "E11";
-LOCATE COMP  "FLASH_DIN"   SITE "E12";
-LOCATE COMP  "FLASH_DOUT"    SITE "A12";
-
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
 DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
-
-LOCATE COMP  "PROGRAMN"   SITE "B11";
-IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
-
-
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
 #################################################################
 # Misc
 #################################################################
-LOCATE COMP  "TEMPSENS"    SITE "A13";
-IOBUF  PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
-
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
 #coding of FPGA number
-LOCATE COMP "CODE_LINE_1"    SITE "AA20";
-LOCATE COMP "CODE_LINE_0"    SITE "Y21";
-IOBUF  PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
-IOBUF  PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP  ;
-
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
 #terminated differential pair to pads
-LOCATE COMP  "SUPPL"   SITE "C14";
-IOBUF  PORT "SUPPL" IO_TYPE=LVDS25   ;
-
-
+LOCATE COMP "SUPPL" SITE "C14" ;
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
 #################################################################
 # LED
 #################################################################
-LOCATE COMP  "LED_GREEN"    SITE "F12";
-LOCATE COMP  "LED_ORANGE"   SITE "G13";
-LOCATE COMP  "LED_RED"      SITE "A15";
-LOCATE COMP  "LED_YELLOW"   SITE "A16";
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
 DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;\r
-\r
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
-
 #################################################################
 # Basic Settings
 #################################################################
-
-  SYSCONFIG MCCLK_FREQ = 20;
-
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-  
+SYSCONFIG MCCLK_FREQ=20 ;
+#      FREQUENCY PORT CLK_PCLK_RIGHT                                                                   200 MHz;
+#      FREQUENCY PORT CLK_PCLK_LEFT                                                                    200 MHz;
+#      FREQUENCY PORT CLK_GPLL_LEFT                                                                    125 MHz;
+#FREQUENCY NET "rx_clock_half" 100.000000 MHz ;
+#FREQUENCY NET "rx_clock_full" 200.000000 MHz ;
 #################################################################
 # Reset Nets
 #################################################################  
-GSR_NET NET "GSR_N";  
-
-
-
-
+#GSR_NET NET "GSR_N";  
 #################################################################
 # Locate Serdes and media interfaces
 #################################################################
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP   "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-
-REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI"   "R13C150D" 12 16 DEVSIZE;
-REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; 
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SYNC_LINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20 ns;
-
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-BLOCK JTAGPATHS;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
+#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
+#REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
+#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
+#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
+#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
+#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
+#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_SYNC_LINK/wa_pos*" 20.000000 ns ;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+BLOCK JTAGPATHS ;
+USE PRIMARY NET "CLK_GPLL_RIGHT_c" ;
+FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;

diff --git a/soda_source/soda_source_synconstraints.fdc b/soda_source/soda_source_synconstraints.fdc
new file mode 100644 (file)
index 0000000..9d02335
--- /dev/null
+++ b/soda_source/soda_source_synconstraints.fdc
@@ -0,0 +1,47 @@
+
+###==== BEGIN Header
+
+# Synopsys, Inc. constraint file
+# /local/lemmens/lattice/soda/soda_source/soda_source_synconstraints.fdc
+# Written on Tue Dec  3 18:26:37 2013
+# by Synplify Pro, G-2012.09L-1  FDC Constraint Editor
+
+# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
+# These sections are generated from SCOPE spreadsheet tabs.
+
+###==== END Header
+
+###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
+###==== END Collections
+
+###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
+create_clock  -name {clk_raw_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOK} -period {5}
+
+create_clock  -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10}
+create_clock  -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10}
+create_clock  -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5}
+set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} }
+set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} }
+set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} }
+set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} }
+###==== END Clocks
+
+###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
+###==== END "Generated Clocks"
+
+###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
+###==== END Inputs/Outputs
+
+###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
+###==== END "Delay Paths"
+
+###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
+###==== END Attributes
+
+###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
+###==== END "I/O Standards"
+
+###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
+###==== END "Compile Points"
+
+

diff --git a/source/med_ecp3_sfp_sync_down.vhd b/source/med_ecp3_sfp_sync_down.vhd
index b9af9a10b30e969a559cbc1a7aee2767855fd8c8..081b95719b04807c65205aa8537327d70ebafc96 100644 (file)
--- a/source/med_ecp3_sfp_sync_down.vhd
+++ b/source/med_ecp3_sfp_sync_down.vhd
@@ -72,10 +72,11 @@ architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is
   -- Placer Directives
   attribute HGROUP : string;
   -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture  is "media_interface_group";
+  attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture  is "media_downlink_group";
   attribute syn_sharing : string;
   attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";
 
+\r
 
 component DCS
 -- synthesis translate_off

diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx
index 472bcbacecbd51d15bb38730838ac282c26a1669..3a9db775924ce008b98a54b7cecb65e89b29ac59 100644 (file)
--- a/source/serdes_sync_downstream.ipx
+++ b/source/serdes_sync_downstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 10:05:44.402" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 04 11:25:23.076" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
                <File name="serdes_sync_downstream.lpc" type="lpc" modified="2013 10 02 10:05:42.000"/>
                <File name="serdes_sync_downstream.pp" type="pp" modified="2013 10 02 10:05:42.000"/>
                <File name="serdes_sync_downstream.sym" type="sym" modified="2013 10 02 10:05:43.000"/>
                <File name="serdes_sync_downstream.tft" type="tft" modified="2013 10 01 11:57:48.000"/>
-               <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 10 02 10:05:42.000"/>
+               <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2013 10 09 13:11:15.000"/>
                <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2013 10 01 11:57:48.000"/>
   </Package>
 </DiamondModule>

diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd
index 1092549e90fb1e2ee7f10538aa6a6f896e9d5162..639e5c09e7a2c0e9d340c0c2e90c49a424b3c967 100644 (file)
--- a/source/trb3_periph_sodasource.vhd
+++ b/source/trb3_periph_sodasource.vhd
@@ -20,10 +20,10 @@ entity trb3_periph_sodasource is
     );
   port(
     --Clocks 
-    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+               CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
+               CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
+               CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+               CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
 
     --Trigger
     --TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
@@ -33,8 +33,8 @@ entity trb3_periph_sodasource is
     --CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
 
     --serdes I/O - connect as you like, no real use
-    SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-    SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
+               SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
+               SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
 
     --Inter-FPGA Communication
     FPGA5_COMM : inout std_logic_vector(11 downto 0);
@@ -76,27 +76,27 @@ entity trb3_periph_sodasource is
 
   attribute syn_useioff                  : boolean;
   --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of LED_GREEN     : signal is false;
-  attribute syn_useioff of LED_ORANGE    : signal is false;
-  attribute syn_useioff of LED_RED       : signal is false;
-  attribute syn_useioff of LED_YELLOW    : signal is false;
-  attribute syn_useioff of TEMPSENS      : signal is false;
-  attribute syn_useioff of PROGRAMN      : signal is false;
-  attribute syn_useioff of CODE_LINE     : signal is false;
-  attribute syn_useioff of LED_LINKOK    : signal is false;
-  attribute syn_useioff of LED_TX        : signal is false;
-  attribute syn_useioff of LED_RX        : signal is false;
-  attribute syn_useioff of SFP_MOD0      : signal is false;
-  attribute syn_useioff of SFP_TXDIS     : signal is false;
-  attribute syn_useioff of SFP_LOS       : signal is false;
-  attribute syn_useioff of TEST_LINE  : signal is false;
+  attribute syn_useioff of LED_GREEN           : signal is false;
+  attribute syn_useioff of LED_ORANGE          : signal is false;
+  attribute syn_useioff of LED_RED                     : signal is false;
+  attribute syn_useioff of LED_YELLOW          : signal is false;
+  attribute syn_useioff of TEMPSENS                    : signal is false;
+  attribute syn_useioff of PROGRAMN                    : signal is false;
+  attribute syn_useioff of CODE_LINE           : signal is false;
+  attribute syn_useioff of LED_LINKOK          : signal is false;
+  attribute syn_useioff of LED_TX                      : signal is false;
+  attribute syn_useioff of LED_RX                      : signal is false;
+  attribute syn_useioff of SFP_MOD0                    : signal is false;
+  attribute syn_useioff of SFP_TXDIS           : signal is false;
+  attribute syn_useioff of SFP_LOS                     : signal is false;
+  attribute syn_useioff of TEST_LINE           : signal is false;
 
   --important signals _with_ IO-FF
-  attribute syn_useioff of FLASH_CLK  : signal is true;
-  attribute syn_useioff of FLASH_CS   : signal is true;
-  attribute syn_useioff of FLASH_DIN  : signal is true;
-  attribute syn_useioff of FLASH_DOUT : signal is true;
-  attribute syn_useioff of FPGA5_COMM : signal is true;
+  attribute syn_useioff of FLASH_CLK           : signal is true;
+  attribute syn_useioff of FLASH_CS                    : signal is true;
+  attribute syn_useioff of FLASH_DIN           : signal is true;
+  attribute syn_useioff of FLASH_DOUT          : signal is true;
+  attribute syn_useioff of FPGA5_COMM          : signal is true;
 
 
 end entity;