*** empty log message ***

diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd
index 699c8ee184df3ec7495e82b318a1c53783724ec8..f1427c5b1db2f7f86adf51177535968ea5d55464 100644 (file)
--- a/design/mdc_oepb_pack.vhd
+++ b/design/mdc_oepb_pack.vhd
@@ -224,7 +224,7 @@ component mdc_addon_daq_bus_0
       REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
       REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
       REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
-      CLOCK_FREQUENCY          : itneger range 1 to 200 := 100;
+      CLOCK_FREQUENCY          : integer range 1 to 200 := 100
       );
 
     port(

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index ce90923e6db024d88ccdfa375f5c722d447fa512..00dbfddbba49604c6603dfef25fbab93fb681876 100644 (file)
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -66,7 +66,7 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal MED_STAT_OP    : std_logic_vector(16-1 downto 0);
   signal MED_CTRL_OP    : std_logic_vector(16-1 downto 0);
   signal MED_STAT_DEBUG : std_logic_vector(63 downto 0);
-  signal MED_CTRL_DEBUG : std_logic_vector(63 downto 0);
+  signal MED_CTRL_DEBUG : std_logic_vector(15 downto 0);
 
   signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
   signal LVL1_TRG_RECEIVED_OUT : std_logic;
@@ -195,7 +195,6 @@ begin
 ---------------------------------------------------------------------
   API: trb_net16_endpoint_hades_full
     generic map(
-      BROADCAST_BITMASK        => x"FD",
       REGIO_NUM_STAT_REGS      => 3,
       REGIO_NUM_CTRL_REGS      => 3,
       --standard values for output registers
@@ -204,7 +203,8 @@ begin
       REGIO_USED_CTRL_REGS     => (others => '1'),
       REGIO_USED_CTRL_BITMASK  => (others => '1'),
       BROADCAST_BITMASK        => x"FD",
-      REGIO_COMPILE_TIME       => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32))
+      REGIO_COMPILE_TIME       => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+      CLOCK_FREQUENCY          => 100
       )
     port map(
       CLK    => CLK_100,