signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0);
signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0);
signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0);
-
+signal debug_retrans_i : std_logic_vector(4*32-1 downto 0);
+
signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0);
attribute nopad : string;
attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32),
+ DEBUG_RETRANS_OUT => debug_retrans_i(i*32+31 downto i*32),
+
BUS_RX => mii_rx_i(i),
BUS_TX => mii_tx_i(i)
);
MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
- MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'),
+ MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
+ --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i,
+ --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'),
DEBUG_OUT => open
);
signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0);
signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0);
signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0);
-
+signal debug_retrans_i : std_logic_vector(4*32-1 downto 0);
+
signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0);
attribute nopad : string;
attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32),
DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32),
+
+ DEBUG_RETRANS_OUT => debug_retrans_i(i*32+31 downto i*32),
BUS_RX => mii_rx_i(i),
BUS_TX => mii_tx_i(i)
MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
- MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'),
+ MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
+ --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i,
+ --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'),
DEBUG_OUT => open
);
STAT_RESET : out std_logic_vector(31 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0);
+ DEBUG_RETRANS_OUT : out std_logic_vector(31 downto 0);
+ FORCE_CRC_ERROR_IN : in std_logic := '0';
+
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX
);
signal STAT_RESET_i : std_logic_vector(31 downto 0);
signal DEBUG_OUT_i : std_logic_vector(31 downto 0);
+signal last_FORCE_CRC_ERROR_IN : std_logic;
+signal crc_error_delay : std_logic_vector(3 downto 0) := "0000";
+
begin
STAT_RESET <= STAT_RESET_i;
DEBUG_OUT <= DEBUG_OUT_i;
+last_FORCE_CRC_ERROR_IN <= FORCE_CRC_ERROR_IN when rising_edge(CLK_SYS);
+DEBUG_RETRANS_OUT <= start_retr_counter & request_retr_counter when rising_edge(CLK_SYS);
+
rst_n_tx <= not (CLEAR or sd_los_i or make_link_reset_real_i) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1)
else not (CLEAR or make_link_reset_real_i);
BUS_TX.ack <= '1';
case BUS_RX.addr(3 downto 0) is
when x"0" => force_crc_error <= '1';
+ when x"1" => crc_error_delay <= BUS_RX.data(3 downto 0);
when others => BUS_TX.unknown <= '1';
end case;
elsif BUS_RX.read = '1' then
BUS_TX.ack <= '1';
- BUS_TX.data <= x"deadface";
case BUS_RX.addr(3 downto 0) is
when x"0" => BUS_TX.data <= x"000" & "000" & force_crc_error & request_retr_counter;
when x"1" => BUS_TX.data <= x"0000" & start_retr_counter;
when others => BUS_TX.unknown <= '1';
end case;
end if;
-
- if request_retr_i = '1' then
+
+ if last_FORCE_CRC_ERROR_IN = '0' and FORCE_CRC_ERROR_IN = '1' then
+ force_crc_error <= '1';
+ elsif request_retr_i = '1' then
force_crc_error <= '0';
end if;
end process;
--ENABLE_SEND_CHKSUM => '1', --SIM
ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8),
+ --RESET_RETRANSMIT_IN => send_link_reset_i,
+ RESET_RETRANSMIT_IN => '0',
DEBUG_OUT => DEBUG_TX_CONTROL_i,
STAT_REG_OUT => STAT_TX_CONTROL_i
START_POSITION_OUT => start_retr_position_i,
FORCE_CRC_ERROR => force_crc_error,
+ CRC_ERROR_DELAY => crc_error_delay,
+ --RESET_RETRANSMIT_IN => MEDIA_INT2MED.ctrl_op(15),
+ RESET_RETRANSMIT_IN => '0',
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
RX_DLM => rx_dlm_i,
START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0');
FORCE_CRC_ERROR : in std_logic := '0';
+ CRC_ERROR_DELAY : in std_logic_vector(3 downto 0);
+ RESET_RETRANSMIT_IN : in std_logic;
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
RX_DLM : out std_logic := '0';
RX_ALLOW_IN : in std_logic := '0';
ENABLE_SEND_CHKSUM : in std_logic;
+ RESET_RETRANSMIT_IN : in std_logic;
DEBUG_OUT : out std_logic_vector(31 downto 0);
STAT_REG_OUT : out std_logic_vector(31 downto 0)
START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0');
FORCE_CRC_ERROR : in std_logic;
+ CRC_ERROR_DELAY : in std_logic_vector(3 downto 0);
+ RESET_RETRANSMIT_IN : in std_logic;
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
RX_DLM : out std_logic := '0';
signal use_crc : std_logic := '0';
signal last_use_crc : std_logic := '0';
signal load_use_crc : std_logic := '0';
---signal last_load_use_crc : std_logic := '0';
signal disable_crc : std_logic := '0';
signal num_crc : unsigned(3 downto 0) := (others => '0');
-signal num_pak : unsigned(7 downto 0) := (others => '0');
-signal resub_mode : std_logic := '0';
-signal last_good_pos_counter : std_logic_vector(7 downto 0) := (others => '0');
-signal last_send_link_reset_i : std_logic;
+signal num_pak : unsigned(3 downto 0) := (others => '0');
+signal resub_mode : std_logic := '0';
+--signal last_good_pos_counter : std_logic_vector(7 downto 0) := (others => '0');
+--signal last_send_link_reset_i : std_logic;
+signal reset_retrans : std_logic;
+
+--signal num_count : unsigned(7 downto 0) := (others => '0');
+--signal max_count : unsigned(7 downto 0) := (others => '0');
+--signal bad_crc : std_logic_vector(7 downto 0);
+--signal good_crc : std_logic_vector(7 downto 0);
+--signal store_crc : std_logic := '0';
+signal CRC_ERROR_DELAY_cnt : std_logic_vector(3 downto 0) := (others => '0');
+
begin
ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty and (pulse_good_100 or got_pulse_good or pulse_bad_100 or got_pulse_bad or not use_crc); -- when rising_edge(CLK_100);
---ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty;
+
buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty and (((pulse_good_100 or got_pulse_good) and not (pulse_bad_100 or got_pulse_bad)) or not use_crc)
when rising_edge(CLK_100);
---buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100);
RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ;
RX_WRITE_OUT <= buf_rx_write_out;
last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100);
last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100);
last_use_crc <= use_crc when rising_edge(CLK_100);
---use_crc <= next_use_crc when rising_edge(CLK_100);
+reset_retrans <= RESET_RETRANSMIT_IN when rising_edge(CLK_100);
process begin
wait until rising_edge(CLK_100);
if RX_ALLOW_IN = '0' then
rx_packet_num <= "100";
- --good_pos_counter <= (others => '0');
elsif buf_rx_write_out = '1' then
if rx_packet_num = "100" then
rx_packet_num <= "000";
end if;
end if;
- if send_link_reset_i = '1' --and last_send_link_reset_i = '0'
- --and last_good_pos_counter /= x"00"
- then
- if last_good_pos_counter /= x"00" then
- num_pak(7 downto 0) <= last_good_pos_counter;
- end if;
+ if send_link_reset_i = '1' or reset_retrans = '1' then
good_pos_counter <= (others => '0');
end if;
end process;
-last_good_pos_counter <= good_pos_counter when rising_edge(CLK_100) ; -- and waiting_for_retr = '1';
--- and resub_mode = '1';
-last_send_link_reset_i <= send_link_reset_i when rising_edge(CLK_100);
----------------------------------------------------------------------
-- Clock Domain Transfer
when K_IDLE =>
rx_state <= GET_IDLE;
crc_reset <= '1';
+ resub_mode <= '0';
when K_RST =>
rx_state <= MAKE_RESET;
reset_cnt <= x"00";
rx_state_bits <= x"4";
crc_en <= '1';
if reg_rx_k_in = '0' then
- --if resub_mode = '1' then
- --num_pak <= num_pak+1;
- --end if;
- next_sop <= '0';
+ next_sop <= '0';
rx_data(15 downto 8)<= reg_rx_data_in;
rx_data(16) <= next_sop;
rx_data(17) <= '0';
num_pakets <= num_pakets+1;
rx_state <= FIRST;
else
- rx_state <= SLEEP;
+ rx_state <= SLEEP;
end if;
when GET_CRC =>
if (use_crc = '0') then
-- first time
load_use_crc <= '1';
- --pulse_good <= '1';
disable_crc <= '0';
- else
- if ((crc_q = reg_rx_data_in and waiting_for_retr = '0') --- and num_pakets = 5)
- and force_crc_error = '0') or disable_crc = '1' then -- CRC match
- pulse_good <= '1';
- else
- if force_crc_error = '1' then
- disable_crc <= '1';
- end if;
- --pulse_good <= '1';
+ else
+ if (crc_q /= reg_rx_data_in or waiting_for_retr = '1' or --- or num_pakets /= 5)
+ (force_crc_error = '1' and CRC_ERROR_DELAY_cnt = "0000") ) and disable_crc = '0' then
+ -- bad
pulse_bad <= '1';
if waiting_for_retr = '0' then
if crc_q /= reg_rx_data_in then
num_crc <= num_crc+1;
- --else
- --num_pak <= num_pak+1;
+ else
+ num_pak <= num_pak+1;
end if;
- req_retr_i <= '1';
+ req_retr_i <= '1';
waiting_for_retr <= '1';
- end if;
+ end if;
+ else
+ -- good
+ pulse_good <= '1';
+ if force_crc_error = '0' then
+ CRC_ERROR_DELAY_cnt <= CRC_ERROR_DELAY;
+ disable_crc <= '0';
+ end if;
end if;
end if;
crc_reset <= '1';
rx_state <= FIRST;
num_pakets <= (others => '0');
-
+ if force_crc_error = '1' then
+ CRC_ERROR_DELAY_cnt <= std_logic_vector(unsigned(CRC_ERROR_DELAY_cnt) - 1);
+ end if;
+
when GET_RETR =>
+ if force_crc_error = '1' then
+ disable_crc <= '1';
+ end if;
rx_state <= FIRST;
waiting_for_retr <= '0';
crc_reset <= '1';
- num_pakets <= (others => '0');
- --num_pak <= (others => '0');
- resub_mode <= '1';
- num_crc <= num_crc+1; --BUGBUG
- --load_use_crc <= '0';
+ num_pakets <= (others => '0');
+ resub_mode <= '1';
when GET_DLM =>
rx_state_bits <= x"5";
start_retr_i <= '1';
start_retr_pos_i <= reg_rx_data_in;
rx_state <= FIRST;
-
+
when MAKE_RESET =>
rx_state_bits <= x"F";
load_use_crc <= '0';
crc_reset <= '1';
waiting_for_retr <= '0';
- num_pakets <= (others => '0');
- resub_mode <= '0';
+ num_pakets <= (others => '0');
+ resub_mode <= '0';
if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then
send_link_reset_i <= '1';
make_reset_i <= '0';
make_reset_i <= '0';
send_link_reset_i <= '0';
end if;
+
+ if reset_retrans = '1' then
+ load_use_crc <= '0';
+ crc_reset <= '1';
+ waiting_for_retr <= '0';
+ num_pakets <= (others => '0');
+ resub_mode <= '0';
+ end if;
+
end process;
reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_200);
);
---REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data
REQUEST_POSITION_OUT <= good_pos_counter;
SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200);
DEBUG_OUT(7) <= ct_fifo_write;
DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0);
---DEBUG_OUT(16) <= reg_rx_k_in;
---DEBUG_OUT(17) <= make_reset_i;
---DEBUG_OUT(18) <= send_link_reset_i;
---DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0';
+DEBUG_OUT(16) <= reg_rx_k_in;
+DEBUG_OUT(17) <= make_reset_i;
+DEBUG_OUT(18) <= send_link_reset_i;
+DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0';
+
+DEBUG_OUT(20) <= use_crc;
---DEBUG_OUT(20) <= use_crc;
+DEBUG_OUT(23 downto 21) <= (others => '0');
+DEBUG_OUT(31 downto 28) <= num_pak;
+DEBUG_OUT(27 downto 24) <= num_crc;
---DEBUG_OUT(23 downto 21) <= (others => '0');
---DEBUG_OUT(27 downto 24) <= num_crc;
-DEBUG_OUT(23 downto 16) <= last_good_pos_counter;
-DEBUG_OUT(31 downto 24) <= num_pak;
-- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
- MEDIA_STATUS_REG_IN : in std_logic_vector(127 downto 0);
+ MEDIA_STATUS_REG_IN : in std_logic_vector(511 downto 0);
DEBUG_OUT : out std_logic_vector(31 downto 0)
);
end entity;
end process;
-end architecture;
\ No newline at end of file
+end architecture;
RX_ALLOW_IN : in std_logic := '0';
ENABLE_SEND_CHKSUM : in std_logic;
+ RESET_RETRANSMIT_IN : in std_logic;
DEBUG_OUT : out std_logic_vector(31 downto 0);
STAT_REG_OUT : out std_logic_vector(31 downto 0)
signal ram_empty : std_logic;
signal ram_afull : std_logic;
- signal ram_read_addr1 : unsigned(7 downto 0) := (others => '0');
- signal ram_read_addr2 : unsigned(7 downto 0) := (others => '0');
+ --signal ram_read_addr1 : unsigned(7 downto 0) := (others => '0');
+ --signal ram_read_addr2 : unsigned(7 downto 0) := (others => '0');
signal request_position_q : std_logic_vector( 7 downto 0);
signal send_chksum_counter : std_logic_vector(7 downto 0) := x"00";
- signal num_pak : unsigned(15 downto 0) := (others => '0');
- signal resub_mode : std_logic := '0';
+ --signal num_pak : unsigned(15 downto 0) := (others => '0');
+ signal resub_mode : std_logic := '0';
+ signal reset_retrans : std_logic;
begin
save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
+ reset_retrans <= RESET_RETRANSMIT_IN when rising_edge(CLK_100);
----------------------------------------------------------------------
-- RAM
----------------------------------------------------------------------
-- ram_read_addr <= (others => '0');
-- els
if rising_edge(CLK_200) then
- if tx_allow_qtx = '0' or send_link_reset_qtx = '1'
+ if tx_allow_qtx = '0' or send_link_reset_qtx = '1' or reset_retrans = '1'
then
- num_pak(15 downto 8) <= (others => '0');
- if ram_read_addr /= x"00" then
- num_pak(7 downto 0) <= ram_read_addr;
- end if;
ram_read_addr <= (others => '0');
- --ram_read_addr2 <= (others => '0');
elsif load_read_pointer_i = '1' then
- ram_read_addr1 <= ram_read_addr;
ram_read_addr <= unsigned(restart_position_i);
- ram_read_addr2 <= unsigned(restart_position_i);
elsif ram_read = '1' then
ram_read_addr <= ram_read_addr + to_unsigned(1,1);
end if;
-- ram_write_addr <= (others => '0');
-- els
if rising_edge(CLK_200) then
- if tx_allow_qtx = '0' or send_link_reset_qtx = '1'
- then
+ if tx_allow_qtx = '0' or send_link_reset_qtx = '1' or reset_retrans = '1' then
ram_write_addr <= (others => '0');
elsif ram_write = '1' then
ram_write_addr <= ram_write_addr + to_unsigned(1,1);
--RAM empty
--- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;
ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0';
ram_afull <= '1' when ram_fill_level >= 4 else '0';
send_link_reset_qtx, make_request_i, make_restart_i, send_dlm_i)
begin
if rising_edge(CLK_200) then
--- ram_read <= '0';
TX_K_OUT <= '0';
TX_CD_OUT <= '0';
debug_sending_dlm <= '0';
first_idle <= '1';
--- load_read_pointer_i <= '0';
case current_state is
when SEND_IDLE_L =>
TX_DATA_OUT <= K_IDLE;
current_state <= SEND_IDLE_H;
first_idle <= first_idle;
load_eop <= '0';
+ resub_mode <= '0';
when SEND_IDLE_H =>
if rx_allow_qtx = '1' or toggle_idle = '1' then
when SEND_DATA_H =>
TX_DATA_OUT <= ram_dout(15 downto 8);
- --if resub_mode = '1' then
- --num_pak <= num_pak+1;
- --end if;
when SEND_CHKSUM_L =>
send_chksum_counter <= std_logic_vector(unsigned(send_chksum_counter) + 1);
--TX_DATA_OUT <= std_logic_vector(ram_read_addr);
TX_DATA_OUT <= x"FF"; --
current_state <= SEND_DATA_L; ---
- --num_pak <= (others => '0');
- resub_mode <= '1';
+ resub_mode <= '1';
when SEND_REQUEST_L =>
TX_DATA_OUT <= K_REQ;
current_state <= SEND_REQUEST_L;
elsif make_restart_i = '1' then
current_state <= SEND_START_L;
--- load_read_pointer_i <= '1';
elsif send_dlm_i = '1' then
current_state <= SEND_DLM_L;
elsif load_eop = '1' then
current_state <= SEND_CHKSUM_L;
elsif ram_empty = '0' then
--- ram_read <= '1';
current_state <= SEND_DATA_L;
else
current_state <= SEND_IDLE_L;
if RESET_IN = '1' then
ram_read <= '0';
end if;
+ if reset_retrans = '1' then
+ resub_mode <= '0';
+ end if;
+
+
end process;
----------------------------------------------------------------------
PULSE_B_OUT => start_retransmit_i
);
--- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync
--- port map(
--- CLK_A_IN => CLK_100,
--- RESET_A_IN => RESET_IN,
--- PULSE_A_IN => SEND_DLM,
--- CLK_B_IN => CLK_200,
--- RESET_B_IN => RESET_IN,
--- PULSE_B_OUT => send_dlm_in_i
--- );
send_dlm_in_i <= SEND_DLM;
THE_POSITION_REG : process(CLK_100)
--Store Request Retransmit position
THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN)
begin
- if RESET_IN = '1' then
+ if RESET_IN = '1' or reset_retrans = '1' then
make_request_i <= '0';
request_position_i <= (others => '0');
elsif rising_edge(CLK_200) then
--Store Restart position
THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN)
begin
- if RESET_IN = '1' then
+ if RESET_IN = '1' or reset_retrans = '1' then
make_restart_i <= '0';
restart_position_i <= (others => '0');
load_read_pointer_i <= '0';
-- DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0);
-- DEBUG_OUT(31 downto 24) <= send_chksum_counter;
--- DEBUG_OUT(23 downto 16) <= ram_read_addr1 when rising_edge(CLK_100);
--- DEBUG_OUT(31 downto 24) <= ram_read_addr2 when rising_edge(CLK_100);
-DEBUG_OUT(31 downto 16) <= num_pak when rising_edge(CLK_100);
process(CLK_100)
begin
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