--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
- constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant USE_EXTERNAL_CLOCK : integer := c_NO;
constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
--Use sync mode, RX clock for all parts of the FPGA
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60";
--set to 0 for backplane serdes, set to 3 for front SFP serdes
- constant SERDES_NUM : integer := 0;
+ constant SERDES_NUM : integer := 3;
constant INCLUDE_UART : integer := c_YES;
constant INCLUDE_SPI : integer := c_YES;
TOPNAME => "trb3sc_adc",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.5_x64',
+lattice_path => '/d/jspc29/lattice/diamond/3.7_x64',
+synplify_path => '/d/jspc29/lattice/synplify/L-2016.03/',
# synplify_path => '/d/jspc29/lattice/synplify/J-2015.03-SP1/',
-synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
-synplify_binary => "/d/jspc29/lattice/synplify/I-2013.09-SP1/bin/synplify_pro",
+# synplify_path => '/d/jspc29/lattice/synplify/I-2013.09-SP1/',
+# synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+# synplify_binary => "/d/jspc29/lattice/synplify/I-2013.09-SP1/bin/synplify_pro",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/adcaddon; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/I-2013.09-SP1/bin/synplify_premier_dp -batch trb3sc_adc.prj\" #",
-nodelist_file => 'nodelist_frankfurt.txt',
+nodelist_file => 'nodes_frankfurt_adcaddon.txt',
#Include only necessary lpf files
-l 5
-y
-s 12
--t 32
+-t 1
-c 1
-e 2
-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+
+LOCATE COMP "THE_MEDIA_INTERFACE_OLD/gen_serdes_0_200_ctc.THE_SERDES/PCSD_INST" SITE "PCSD" ;
+LOCATE UGROUP "THE_MEDIA_INTERFACE_OLD/media_interface_group" REGION "MEDIA_MIXED" ;
+
+
+
#################################################################
# ADC Processor
#################################################################
#USE PRIMARY NET "CLK_GPLL_RIGHT_c";
#USE PRIMARY NET "CLK_PCLK_LEFT_c";
-USE PRIMARY NET "CLK_CORE_PCLK_c";
-USE PRIMARY NET "CLK_EXT_PCLK";
+PROHIBIT PRIMARY NET "P_CLOCK_c";
+PROHIBIT SECONDARY NET "P_CLOCK_c";
+
+# USE PRIMARY NET "CLK_CORE_PCLK_c";
+# USE PRIMARY NET "CLK_EXT_PCLK";
-# USE PRIMARY2EDGE NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
-# USE PRIMARY2EDGE NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i;
\ No newline at end of file
+PROHIBIT PRIMARY NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i ;
+PROHIBIT SECONDARY NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
+USE EDGE NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
+USE EDGE NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i;
\ No newline at end of file
add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
-add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out40.vhd"
+#add_file -vhdl -lib work "../../trb3/base/cores/pll_in200_out40.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_in240_out40.vhd"
add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd"
+
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_slowcontrol_data_buffer.vhd"
add_file -vhdl -lib "work" "trb3sc_adc.vhd"
-#add_file -constraint "trb3sc_adc.sdc"
+add_file -constraint "trb3sc_adc.sdc"
signal adcspi_ctrl : std_logic_vector(7 downto 0);
-
+ signal s : std_logic_vector(3 downto 0);
+attribute nopad : string;
+attribute nopad of s : signal is "true";
begin
---------------------------------------------------------------------------
CTRL_DEBUG => open
);
+
+-- THE_MEDIA_INTERFACE_OLD : trb_net16_med_ecp3_sfp
+-- generic map(
+-- SERDES_NUM => 0, --number of serdes in quad
+-- EXT_CLOCK => c_NO, --use internal clock
+-- USE_200_MHZ => c_YES, --run on 200 MHz clock
+-- USE_125_MHZ => c_NO,
+-- USE_CTC => c_YES
+-- )
+-- port map(
+-- CLK => clk_full_osc,
+-- SYSCLK => clk_sys,
+-- RESET => reset_i,
+-- CLEAR => clear_i,
+-- CLK_EN => '1',
+-- --Internal Connection
+-- MED_DATA_IN => int2med(0).data,
+-- MED_PACKET_NUM_IN => int2med(0).packet_num,
+-- MED_DATAREADY_IN => int2med(0).dataready,
+-- MED_READ_OUT => med2int(0).tx_read,
+-- MED_DATA_OUT => med2int(0).data,
+-- MED_PACKET_NUM_OUT => med2int(0).packet_num,
+-- MED_DATAREADY_OUT => med2int(0).dataready,
+-- MED_READ_IN => '1',
+-- REFCLK2CORE_OUT => open,
+-- --SFP Connection
+-- SD_RXD_P_IN => s(0),
+-- SD_RXD_N_IN => s(1),
+-- SD_TXD_P_OUT => s(2),
+-- SD_TXD_N_OUT => s(3),
+-- SD_REFCLK_P_IN => open,
+-- SD_REFCLK_N_IN => open,
+-- SD_PRSNT_N_IN => SFP_MOD0(0),
+-- SD_LOS_IN => SFP_LOS(0),
+-- SD_TXDIS_OUT => SFP_TX_DIS(0),
+-- -- Status and control port
+-- STAT_OP => med2int(0).stat_op,
+-- CTRL_OP => int2med(0).ctrl_op,
+-- STAT_DEBUG => med_stat_debug(63 downto 0),
+-- CTRL_DEBUG => (others => '0')
+-- );
+
SFP_TX_DIS(0) <= '1';
gen_sfp_con : if SERDES_NUM = 3 generate
sfp_los_i <= SFP_LOS(1);
sfp_prsnt_i <= BACK_GPIO(1);
BACK_GPIO(0) <= sfp_txdis_i;
end generate;
-
+--
---------------------------------------------------------------------------
-- Endpoint
---------------------------------------------------------------------------
THE_ADC : entity work.adc_handler
port map(
CLK => clk_sys,
- CLK_ADCRAW => clk_full_osc,
+ CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc,
+ CLK_RAW_LEFT => CLK_CORE_PLL_LEFT,
+ CLK_RAW_RIGHT=> CLK_CORE_PLL_RIGHT,
- ADCCLK_OUT => P_CLOCK,
+ ADCCLK_OUT => open, --P_CLOCK,
ADC_DATA( 4 downto 0) => ADC1_CH,
ADC_DATA( 9 downto 5) => ADC2_CH,
ADC_DATA(14 downto 10) => ADC3_CH,
CLK => clk_sys,
CLK_ADCRAW => clk_full_osc,
- ADCCLK_OUT => P_CLOCK,
+ ADCCLK_OUT => open, --P_CLOCK,
ADC_DATA( 4 downto 0) => ADC1_CH,
ADC_DATA( 9 downto 5) => ADC2_CH,
ADC_DATA(14 downto 10) => ADC3_CH,
);
end generate;
+
+ THE_ADC_REF : entity work.pll_in240_out40
+ port map(
+ CLK => CLK_CORE_PCLK,
+ CLKOP => P_CLOCK,
+ LOCK => open
+ );
---------------------------------------------------------------------------
-- Bus Handler
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_in240_out200" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 06 22 13:33:31.162" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="pll_in240_out200" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 06 13 13:11:08.021" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="pll_in240_out200.lpc" type="lpc" modified="2015 06 22 13:33:26.000"/>
- <File name="pll_in240_out200.vhd" type="top_level_vhdl" modified="2015 06 22 13:33:26.000"/>
- <File name="pll_in240_out200_tmpl.vhd" type="template_vhdl" modified="2015 06 22 13:33:26.000"/>
+ <File name="pll_in240_out200.lpc" type="lpc" modified="2016 06 13 13:11:04.000"/>
+ <File name="pll_in240_out200.vhd" type="top_level_vhdl" modified="2016 06 13 13:11:04.000"/>
+ <File name="pll_in240_out200_tmpl.vhd" type="template_vhdl" modified="2016 06 13 13:11:04.000"/>
</Package>
</DiamondModule>
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.7
+CoreRevision=5.8
ModuleName=pll_in240_out200
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=06/22/2015
-Time=13:33:26
+Date=06/13/2016
+Time=13:11:04
[Parameters]
Verilog=0
OFrq=200.000000
DutyTrimP=Rising
DelayMultP=0
-fb_mode=CLKOP
+fb_mode=CLKOS
Mult=5
Phase=0.0
Duty=8
enClkOK2=0
[Command]
-cmd_line= -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
+cmd_line= -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLKOS -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
--- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
-- Module Version: 5.7
---/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
+--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_in240_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 240 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -fb_mode CLKOS -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw
--- Mon Jun 22 13:33:26 2015
+-- Mon Jun 13 13:11:04 2016
library IEEE;
use IEEE.std_logic_1164.all;
CLKOS: out std_logic;
CLKOK: out std_logic;
LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_in240_out200 : entity is true;
end pll_in240_out200;
architecture Structure of pll_in240_out200 is
-- internal signal declarations
- signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
+ signal CLKOS_t: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "240.000000";
attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "100.000000";
attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ generic map (FEEDBK_PATH=> "CLKOS", CLKOK_BYPASS=> "DISABLED",
CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 6,
FIN=> "240.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ port map (CLKI=>CLK, CLKFB=>CLKOS_t, RST=>scuba_vlo,
RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
jspc29 / trb3sc.git / commitdiff