--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 7.5
+--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n statmem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 11 -rp 1010 -data_width 18 -rdata_width 18 -num_rows 1024 -outdataA REGISTERED -outdataB REGISTERED -writemodeA NORMAL -writemodeB NORMAL -cascade -1
+
+-- Sun Apr 17 23:59:41 2022
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity statmem is
+ port (
+ DataInA: in std_logic_vector(17 downto 0);
+ DataInB: in std_logic_vector(17 downto 0);
+ AddressA: in std_logic_vector(9 downto 0);
+ AddressB: in std_logic_vector(9 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(17 downto 0);
+ QB: out std_logic_vector(17 downto 0));
+end statmem;
+
+architecture Structure of statmem is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute MEM_LPC_FILE of statmem_0_0_0 : label is "statmem.lpc";
+ attribute MEM_INIT_FILE of statmem_0_0_0 : label is "";
+ attribute RESETMODE of statmem_0_0_0 : label is "SYNC";
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ statmem_0_0_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
+ DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
+ DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
+ DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
+ DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
+ DIA15=>DataInA(15), DIA16=>DataInA(16), DIA17=>DataInA(17),
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
+ ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
+ ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
+ ADA12=>AddressA(8), ADA13=>AddressA(9), CEA=>ClockEnA,
+ CLKA=>ClockA, OCEA=>ClockEnA, WEA=>WrA, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>ResetA,
+ DIB0=>DataInB(0), DIB1=>DataInB(1), DIB2=>DataInB(2),
+ DIB3=>DataInB(3), DIB4=>DataInB(4), DIB5=>DataInB(5),
+ DIB6=>DataInB(6), DIB7=>DataInB(7), DIB8=>DataInB(8),
+ DIB9=>DataInB(9), DIB10=>DataInB(10), DIB11=>DataInB(11),
+ DIB12=>DataInB(12), DIB13=>DataInB(13), DIB14=>DataInB(14),
+ DIB15=>DataInB(15), DIB16=>DataInB(16), DIB17=>DataInB(17),
+ ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>AddressB(0), ADB5=>AddressB(1),
+ ADB6=>AddressB(2), ADB7=>AddressB(3), ADB8=>AddressB(4),
+ ADB9=>AddressB(5), ADB10=>AddressB(6), ADB11=>AddressB(7),
+ ADB12=>AddressB(8), ADB13=>AddressB(9), CEB=>ClockEnB,
+ CLKB=>ClockB, OCEB=>ClockEnB, WEB=>WrB, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>ResetB, DOA0=>QA(0),
+ DOA1=>QA(1), DOA2=>QA(2), DOA3=>QA(3), DOA4=>QA(4),
+ DOA5=>QA(5), DOA6=>QA(6), DOA7=>QA(7), DOA8=>QA(8),
+ DOA9=>QA(9), DOA10=>QA(10), DOA11=>QA(11), DOA12=>QA(12),
+ DOA13=>QA(13), DOA14=>QA(14), DOA15=>QA(15), DOA16=>QA(16),
+ DOA17=>QA(17), DOB0=>QB(0), DOB1=>QB(1), DOB2=>QB(2),
+ DOB3=>QB(3), DOB4=>QB(4), DOB5=>QB(5), DOB6=>QB(6),
+ DOB7=>QB(7), DOB8=>QB(8), DOB9=>QB(9), DOB10=>QB(10),
+ DOB11=>QB(11), DOB12=>QB(12), DOB13=>QB(13), DOB14=>QB(14),
+ DOB15=>QB(15), DOB16=>QB(16), DOB17=>QB(17));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of statmem is
+ for Structure
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trb3sc.git / commitdiff