*** empty log message ***

diff --git a/tdc_releases/tdc_v0.3/Channel.vhd b/tdc_releases/tdc_v0.3/Channel.vhd
index 4de1a17af2b190e373d9a6b9b4dad7ffb931e99e..d1fc5659bf562152790562a1da34cf60e007b7eb 100644 (file)
--- a/tdc_releases/tdc_v0.3/Channel.vhd
+++ b/tdc_releases/tdc_v0.3/Channel.vhd
@@ -197,7 +197,7 @@ begin
       DataB  => data_b_i,
       ClkEn  => '1', --ff_array_en_i,
       Result => result_i);
-  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000F" & x"7FFFFFF";
+  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
   data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
 
   --FF_Array_Enable : process (hit_detect_i, release_delay_line_i)

diff --git a/tdc_releases/tdc_v0.3/Reference_channel.vhd b/tdc_releases/tdc_v0.3/Reference_channel.vhd
index 13cddbabfc54cfb356671f7814887fd558027886..346ca4e65535484c8e068c7153adeed6fab0e1f2 100644 (file)
--- a/tdc_releases/tdc_v0.3/Reference_channel.vhd
+++ b/tdc_releases/tdc_v0.3/Reference_channel.vhd
@@ -185,7 +185,7 @@ begin
       DataB  => data_b_i,
       ClkEn  => '1',                    --ff_array_en_i,
       Result => result_i);
-  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000FF" & x"7FFFFFF";
+  data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
   data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
 
   --FF_Array_Enable : process (hit_detect_i, release_delay_line_i)

diff --git a/tdc_releases/tdc_v0.3/TDC.vhd b/tdc_releases/tdc_v0.3/TDC.vhd
index c4c267c8e2f831750e17217b0e17ba759480f622..d4fb88311e9439979a1ba18fcefe487fdbf5c865 100644 (file)
--- a/tdc_releases/tdc_v0.3/TDC.vhd
+++ b/tdc_releases/tdc_v0.3/TDC.vhd
@@ -221,7 +221,7 @@ architecture TDC of TDC is
   type   channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0);
   signal channel_data_i        : channel_data_array;
   signal channel_data_reg      : channel_data_array;
-  signal hit_in_i              : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+  signal hit_in_i              : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
 
 -- Slow Control Signals
   signal ch_en_i                  : std_logic_vector(63 downto 0);
@@ -1112,12 +1112,10 @@ begin
         logic_analyser_reg <= ref_debug_i(15 downto 0);
 
       elsif logic_anal_control = x"3" then  -- Data out
-        logic_analyser_reg(7 downto 0)  <= fsm_debug_reg;
-        logic_analyser_reg(8)           <= REFERENCE_TIME;
-        logic_analyser_reg(13)          <= data_wr_reg;
-        logic_analyser_reg(12 downto 9) <= data_out_reg(25 downto 22);
-        logic_analyser_reg(14)          <= data_out_reg(26);
-        logic_analyser_reg(15)          <= RESET;
+        logic_analyser_reg(7 downto 0)   <= fsm_debug_reg;
+        logic_analyser_reg(8)            <= REFERENCE_TIME;
+        logic_analyser_reg(9)            <= data_wr_reg;
+        logic_analyser_reg(15 downto 10) <= data_out_reg(27 downto 22);
       end if;
     end if;
   end process REG_LOGIC_ANALYSER_OUTPUT;
@@ -1138,7 +1136,7 @@ begin
 --  TDC_DEBUG(31 downto 28)          <= 
 
   -- Register 0x81 & 0x82
-  TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 0);
+  TDC_DEBUG(1*32+CHANNEL_NUMBER-2 downto 1*32+0) <= channel_empty_i(CHANNEL_NUMBER-1 downto 1);
   
 -- Register 0x83
   TDC_DEBUG(3*32+31 downto 3*32+0) <= "00000" & TRG_WIN_POST & "00000" & TRG_WIN_PRE;