Fix little TDC ctrl reg bug

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index 1c558231f72f78339981987b1acbf6fc9be3f59b..f8cf7aeb880fd0e62aa7726d0151b2dae0bd324d 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -737,7 +737,7 @@ LED_YELLOW <= not med_stat_op(11);
       wait until rising_edge(clk_100_i);
       pos                := to_integer(unsigned(bustdc_ctrl_rx.addr(2 downto 0)));
       bustdc_ctrl_tx.data <= tdc_ctrl_reg_arr(pos);
-      bustdc_ctrl_tx.ack  <= bustdc_ctrl_rx.read;
+      bustdc_ctrl_tx.ack  <= bustdc_ctrl_rx.read or bustdc_ctrl_rx.write; -- always acknowledge, one could check the addr indeed
       if bustdc_ctrl_rx.write = '1' then
         tdc_ctrl_reg_arr(pos) <= bustdc_ctrl_rx.data;
       end if;