library work;
use work.all;
use work.version.all;
+use work.config_type.all;
use work.trb_net_std.all;
+
entity trb_v2b_fpga is
generic (
RW_SYSTEM : integer range 1 to 2 := 1; --1 -trb, 2 -addon with portE 10 9 as rw
- TRBV2_TYPE : integer range 0 to 8 := 3;
+ TRBV2_TYPE : integer range 0 to 8 := 0;
-- 0 - trbv2 + RPC or TOF or FWALL or Start or
-- Veto (one board !),
-- 1 - MDC,
-- 2 - SHOWER,
- -- 3 - CTS+Trigger box
+ -- 3 - CTS+Trigger logic
-- 4 - CTS+VULOM (trbent)
-- 5 - CTS only, lvl2 is automatic (trbent)
-- 6 - CTS plus TDC readout and waits for
-- external busy without trbnet
-- 7 - '6' is the source of the triggers
-- 8 - for tdc EUGEN readout
- TRBNET_ENABLE : integer range 0 to 3 := 2; -- 0 - disable,
+ TRBNET_ENABLE : integer range 0 to 3 := 1; -- 0 - disable,
-- 1 - end point
-- 2 - cts
-- 3 - slow ctrl
HADES_OLD_BUS_ENABLE : integer range 0 to 1 := 0;
DSP_INT_ENABLE : integer range 0 to 1 := 0; -- dsp interface enable
SDRAM_INT_ENABLE : integer range 0 to 1 := 0; -- sdram interface enable
- SCALERS_ENABLE : integer range 0 to 1 := 0;
+ SCALERS_ENABLE : integer range 0 to 1 := 1;
RW_REGISTERS_NUMBER : integer range 0 to 40 := 29; --32 bit registers
--accesed by trbnet or
--etrax (read/write) -
--control
- R_REGISTERS_NUMBER : integer range 0 to 60 := 58; --only read - status
+ R_REGISTERS_NUMBER : integer range 0 to 80 := 72; --only read - status
ENABLE_DMA : integer range 1 to 2 := 2; --1- DMA , 2 - no DMA
--2- also for trbnet
--end point !
- NUMBER_OFF_ADD_DATA : integer range 0 to 255 := 8;
+ NUMBER_OFF_ADD_DATA : integer range 0 to 255 := 19;
REGIO_NUM_STAT_REGS : integer range 0 to 255 := 2;
REGIO_NUM_CTRL_REGS : integer range 0 to 255 := 3;
- DEBUG_OPTION : integer range 0 to 8 := 6; --0 no debug
+ DEBUG_OPTION : integer range 0 to 8 := 7; --0 no debug
--1 trbnet enpoit
- --2 trbent cts
+ --2 trbent cts
--3 sfp
--4 stand alone
--5 sdram
--6 trbnet regio
--7 trbnet data handler
+
TRIGGER_RW_REGISTERS_NUMBER : integer range 0 to 40 := 4;
TRIGGER_R_REGISTERS_NUMBER : integer range 0 to 40 := 4;
--there(rpc) and calc diff
--2-check if its there but tof
--is different!
- CONFIG_TYPE: integer range 0 to 9 :=0; -- 0 - CTS
- -- 1 - TOF
- -- 2 - RPC
- -- 3 - FWALL
- -- 4 - START/VETO --see compile script!
CTS_NUMBER_IPU_DATA: integer range 0 to 9 :=2
);
port (
-------------------------------------------------------------------------
ADDON_TO_TRB_CLKINN : in std_logic;
ADDON_TO_TRB_CLKINP : in std_logic;
- ADO_LVDS_IN : in std_logic_vector(51 downto 0); --lvds signal
- ADO_LVDS_OUT : out std_logic_vector(9 downto 0); --lvds signal
+ ADO_LVDS_IN : in std_logic_vector(61 downto 0); --lvds signal
+-- ADO_LVDS_OUT : out std_logic_vector(7 downto 0); --lvds signal
ADO_TTL : inout std_logic_vector(46 downto 0);
-- ADO_TTL : inout std_logic_vector(15 downto 0);
-- ADO_TTL : in std_logic;
-
+
+ --sim--SIM_MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ --sim--SIM_MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ --sim--SIM_MED_DATAREADY_IN : in std_logic;
+ --sim--SIM_MED_READ_OUT : out std_logic;
+ --sim--SIM_MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ --sim--SIM_MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ --sim--SIM_MED_DATAREADY_OUT : out std_logic;
+ --sim--SIM_MED_READ_IN : in std_logic;
+
-------------------------------------------------------------------------------
--TDC JTAG
-------------------------------------------------------------------------------
architecture trb_v2b_fpga of trb_v2b_fpga is
+ component clk_300
+ port (
+ CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+ end component;
+
component clock200
port (
CLKIN_IN : in std_logic;
CLK40_IN : in std_logic;
LVL1_LVDS_TRIGGER_IN : in std_logic_vector(4 downto 0);
LVL1_TTL_TRIGGER_IN : in std_logic_vector(4 downto 0);
+ LVL1_RCTS_TYPE_IN : in std_logic_vector(3 downto 0);
LVL1_FAST_TRIGG_IN : in std_logic;
LVL1_TIMING_TRIGGER_OUT : out std_logic;
+ LVL1_TIMING_TEST_SIGNAL_OUT : out std_logic;
LVL1_APV_TRIGGER_OUT : out std_logic;
LVL1_TRIGBOX_TRIGGER_IN : in std_logic;
LVL1_TRIGBOX_TRIGGER_CODE_IN : in std_logic_vector(3 downto 0);
RESET : in std_logic;
TDC_DATA_IN : in std_logic_vector (31 downto 0);
START_TDC_READOUT : in std_logic;
+ SAVE_TRBNET_HEADERS : in std_logic;
A_TDC_READY : in std_logic;
B_TDC_READY : in std_logic;
C_TDC_READY : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
SDRAM_BUSY : in std_logic;
+ TDC_DATA_DOWNSCALE_IN : in std_logic;
TRBNET_DATA_FINISHED_OUT : out std_logic;
TRBNET_DATA_WRITE_OUT : out std_logic;
TRBNET_DATA_OUT : out std_logic_vector(31 downto 0)
);
end component;
- component simpleupcounter_32bit
- port (
- QOUT : out std_logic_vector(31 downto 0);
- UP : in std_logic;
- CLK : in std_logic;
- CLR : in std_logic);
- end component;
-
component up_down_counter
generic (
NUMBER_OF_BITS : positive);
REGIO_COMPILE_TIME : std_logic_vector(31 downto 0);
REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0);
REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0);
+ REGIO_USE_VAR_ENDPOINT_ID : integer;
REGIO_USE_1WIRE_INTERFACE : integer;
CLOCK_FREQUENCY : integer range 1 to 200);
port (
REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
REGIO_READ_ENABLE_OUT : out std_logic;
REGIO_WRITE_ENABLE_OUT : out std_logic;
-- -----------------------------------------------------------------------------
+-- component trb_net16_endpoint_hades_full_handler
+-- generic (
+-- IBUF_DEPTH : channel_config_t;
+-- FIFO_TO_INT_DEPTH : channel_config_t;
+-- FIFO_TO_APL_DEPTH : channel_config_t;
+-- APL_WRITE_ALL_WORDS : channel_config_t;
+-- ADDRESS_MASK : std_logic_vector(15 downto 0);
+-- BROADCAST_BITMASK : std_logic_vector(7 downto 0);
+-- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0);
+-- REGIO_NUM_STAT_REGS : integer range 0 to 6;
+-- REGIO_NUM_CTRL_REGS : integer range 0 to 6;
+-- REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0);
+-- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0);
+-- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0);
+-- REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0);
+-- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0);
+-- REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0);
+-- REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0);
+-- REGIO_USE_1WIRE_INTERFACE : integer;
+-- REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES;
+-- CLOCK_FREQUENCY : integer range 1 to 200;
+-- DATA_INTERFACE_NUMBER : integer range 1 to 16;
+-- DATA_BUFFER_DEPTH : integer range 9 to 15;
+-- DATA_BUFFER_WIDTH : integer range 1 to 32;
+-- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2;
+-- TRG_RELEASE_AFTER_DATA : integer range 0 to 1;
+-- HEADER_BUFFER_DEPTH : integer range 9 to 15;
+-- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2);
+-- port (
+-- CLK : in std_logic;
+-- RESET : in std_logic;
+-- CLK_EN : in std_logic := '1';
+-- MED_DATAREADY_OUT : out std_logic;
+-- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+-- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+-- MED_READ_IN : in std_logic;
+-- MED_DATAREADY_IN : in std_logic;
+-- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+-- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+-- MED_READ_OUT : out std_logic;
+-- MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+-- MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+-- TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
+-- LVL1_TRG_DATA_VALID_OUT : out std_logic;
+-- LVL1_VALID_TIMING_TRG_OUT : out std_logic;
+-- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic;
+-- LVL1_INVALID_TRG_OUT : out std_logic;
+-- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+-- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+-- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+-- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
+-- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+-- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+-- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+-- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
+-- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+-- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+-- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+-- REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+-- REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+-- REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
+-- REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+-- REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
+-- REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+-- REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+-- REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+-- BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+-- BUS_DATA_OUT : out std_logic_vector(32-1 downto 0);
+-- BUS_READ_ENABLE_OUT : out std_logic;
+-- BUS_WRITE_ENABLE_OUT : out std_logic;
+-- BUS_TIMEOUT_OUT : out std_logic;
+-- BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+-- BUS_DATAREADY_IN : in std_logic := '0';
+-- BUS_WRITE_ACK_IN : in std_logic := '0';
+-- BUS_NO_MORE_DATA_IN : in std_logic := '0';
+-- BUS_UNKNOWN_ADDR_IN : in std_logic := '0';
+-- ONEWIRE_INOUT : inout std_logic;
+-- ONEWIRE_MONITOR_IN : in std_logic := '0';
+-- ONEWIRE_MONITOR_OUT : out std_logic;
+-- REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');
+-- TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0);
+-- TIME_LOCAL_OUT : out std_logic_vector (7 downto 0);
+-- TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0);
+-- TIME_TICKS_OUT : out std_logic_vector (1 downto 0);
+-- STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
+-- STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
+-- STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
+-- STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0);
+-- STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0);
+-- CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
+-- IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
+-- STAT_ONEWIRE : out std_logic_vector (31 downto 0);
+-- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0));
+-- end component;
+
component trb_net16_endpoint_hades_full_handler
generic (
IBUF_DEPTH : channel_config_t;
APL_WRITE_ALL_WORDS : channel_config_t;
ADDRESS_MASK : std_logic_vector(15 downto 0);
BROADCAST_BITMASK : std_logic_vector(7 downto 0);
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0);
REGIO_NUM_STAT_REGS : integer range 0 to 6;
REGIO_NUM_CTRL_REGS : integer range 0 to 6;
REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0);
REGIO_USE_1WIRE_INTERFACE : integer;
REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES;
CLOCK_FREQUENCY : integer range 1 to 200;
+ TIMING_TRIGGER_RAW : integer range 0 to 1;
DATA_INTERFACE_NUMBER : integer range 1 to 16;
DATA_BUFFER_DEPTH : integer range 9 to 15;
DATA_BUFFER_WIDTH : integer range 1 to 32;
- DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2;
+ DATA_BUFFER_FULL_THRESH : integer range 0 to 2**15-2;
TRG_RELEASE_AFTER_DATA : integer range 0 to 1;
HEADER_BUFFER_DEPTH : integer range 9 to 15;
- HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2);
+ HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**15-2);
port (
CLK : in std_logic;
RESET : in std_logic;
LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ TRG_MULTIPLE_TRG_OUT : out std_logic;
+ TRG_TIMEOUT_DETECTED_OUT : out std_logic;
+ TRG_SPURIOUS_TRG_OUT : out std_logic;
+ TRG_MISSING_TMG_TRG_OUT : out std_logic;
+ TRG_SPIKE_DETECTED_OUT : out std_logic;
FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0');
IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
STAT_ONEWIRE : out std_logic_vector (31 downto 0);
- STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0));
+ STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0);
+ DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0));
end component;
component trb_net16_med_tlk
TRIGGER_OUT_EN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
MULTIPLEXER_SELECT : in std_logic_vector(8*3-1 downto 0);
TRIGGER_LOGIC_CTRL_IN : in std_logic_vector(31 downto 0);
- SCALER_OUT : out std_logic_vector(32*32-1 downto 0);
+ SCALER_OUT : out std_logic_vector(62*32-1 downto 0);
BEAM_INHIBIT_IN : in std_logic;
NO_TIMING_OUT : out std_logic;
LVL1_BUSY_IN : in std_logic;
+ LVL1_TRIGGER_ACCEPTED_IN : in std_logic;
LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
LVL1_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
LVL1_TRIGGER_OUT : out std_logic;
TRIGGER_LOGIC_DEBUG_OUT : out std_logic_vector(31 downto 0);
IPU_DATA_IN : in std_logic_vector(31 downto 0);
IPU_DATA_VALID_IN : in std_logic;
+ TRBNET_LVL1_STATUS_IN : in std_logic_vector(31 downto 0);
+ TRBNET_BUSY_IN : in std_logic;
TOKEN_IN : in std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_VALID_OUT : out std_logic;
- TOKEN_OUT : out std_logic
+ TOKEN_OUT : out std_logic;
+ TRANSMIT_NO_DATA_IN : in std_logic
);
end component;
signal tdc_clk : std_logic;
signal tdc_clk_i : std_logic;
signal tdc_data_in_i : std_logic_vector(31 downto 0);
+ signal save_trbnet_headers_i : std_logic;
signal a_data_ready_i : std_logic;
signal b_data_ready_i : std_logic;
signal c_data_ready_i : std_logic;
signal readout_sdram_int_clk : std_logic;
signal sdram_data_ready_i : std_logic;
--scalers
- type scaler_counter_arr is array(0 to 7) of std_logic_vector(31 downto 0);
+ type scaler_counter_arr is array(0 to NUMBER_OFF_ADD_DATA-1) of std_logic_vector(31 downto 0);
signal scaler_counter : scaler_counter_arr;
- signal scaler_pulse : std_logic_vector(7 downto 0);
-
+ signal scaler_pulse : std_logic_vector(NUMBER_OFF_ADD_DATA-1 downto 0);
+ signal number_of_rpc_add_data : std_logic_vector(7 downto 0);
+ signal scaler_reset : std_logic;
+
--ctu
signal lvl1_ctu_status_i : std_logic_vector(31 downto 0);
signal lvl2_ctu_status_i : std_logic_vector(31 downto 0);
signal check_pulse : std_logic;
signal check_counter : std_logic_vector(16 downto 0);
signal lvds_add_on_data : std_logic_vector(31 downto 0);
- signal ado_lv_out_i : std_logic_vector(4 downto 0);
+ signal ado_lv_out_i : std_logic_vector(3 downto 0);
signal self_trigg_counter : std_logic_vector(7 downto 0);
signal r_register_vector : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
signal med_stat_op_in_i : std_logic_vector (15 downto 0);
signal med_ctrl_op_out_i : std_logic_vector (15 downto 0);
signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
- --trbnet values
-
--- SET_TRBNET_CONSTANTS_CTS: if CONFIG_TYPE = 0 generate
--- regio_hardware_version_i <= x"53000000";
--- regio_compile_version_i <= x"0001";
--- broadcast_bitmask_i <= x"fc";
--- end generate SET_TRBNET_CONSTANTS_CTS;
-
--- SET_TRBNET_CONSTANTS_TOF: if CONFIG_TYPE = 1 generate
--- regio_hardware_version_i <= x"81000000";
--- regio_compile_version_i <= x"0001";
--- broadcast_bitmask_i <= x"ef";
--- end generate SET_TRBNET_CONSTANTS_TOF;
-
--- SET_TRBNET_CONSTANTS_RPC: if CONFIG_TYPE = 3 generate
--- regio_hardware_version_i <= x"83000000";
--- regio_compile_version_i <= x"0001";
--- broadcast_bitmask_i <= x"df";
--- end generate SET_TRBNET_CONSTANTS_RPC;
-
--- SET_TRBNET_CONSTANTS_FWALL: if CONFIG_TYPE = 4 generate
--- regio_hardware_version_i <= x"84000000";
--- regio_compile_version_i <= x"0001";
--- broadcast_bitmask_i <= x"bf";
--- end generate SET_TRBNET_CONSTANTS_FWALL;
-
--- SET_TRBNET_CONSTANTS_START_VETO: if CONFIG_TYPE = 2 generate
--- regio_hardware_version_i <= x"82000000";
--- regio_compile_version_i <= x"0001";
--- broadcast_bitmask_i <= x"f9";
--- end generate SET_TRBNET_CONSTANTS_START_VETO;
-
- constant regio_hardware_version_i : std_logic_vector(31 downto 0) := x"53000000";
- constant regio_compile_version_i : std_logic_vector(15 downto 0) := x"0001";
- constant broadcast_bitmask_i : std_logic_vector(7 downto 0) := x"fc";
-
--trbnet -cts
signal not_ipu_dataready_out_i : std_logic;
signal ipu_dataready_out_end_pulse : std_logic;
signal lvl2_trigger_i_pulse : std_logic;
signal cntr_for_dummy_header : std_logic_vector(1 downto 0) := "00";
signal ipu_data_in_i : std_logic_vector(31 downto 0);
+ signal fee_trg_statusbits_in_buf : std_logic_vector(31 downto 0);
+
--vulom
signal vulom_event : std_logic_vector(31 downto 0);
signal vulom_event_valid : std_logic;
signal triggbox_data_valid_out : std_logic;
signal triggbox_token_out : std_logic;
signal trigbox_busy_out : std_logic;
- signal scaler_out_i : std_logic_vector(32*32 -1 downto 0);
+ signal scaler_out_i : std_logic_vector(62*32 -1 downto 0);
signal fee_trg_release_in_i : std_logic_vector(0 downto 0);
+ signal how_many_add_data_i : std_logic_vector(7 downto 0);
+ signal rcts_code_in, rcts_code_in_sync : std_logic_vector(3 downto 0);
+ signal test_timing_signal : std_logic;
+
+ type MDC_DELAY_TIMING is (IDLE, MDC_DELAY_TIMING_A, MDC_DELAY_TIMING_B, MDC_DELAY_TIMING_C);
+ signal MDC_DELAY_TIMING_CURRENT, MDC_DELAY_TIMING_NEXT : MDC_DELAY_TIMING;
+
+ --mdc delay
+ signal mdc_delay_cntr_rst, mdc_delay_cntr_rst_fsm, mdc_delay_cntr_up, mdc_delay_cntr_up_fsm, mdc_width_cntr_rst, mdc_width_cntr_rst_fsm, mdc_width_cntr_up, mdc_width_cntr_up_fsm, mdc_timing_out, mdc_timing_out_fsm : std_logic;
+ signal mdc_delay_cntr : std_logic_vector(7 downto 0);
+ signal mdc_width_cntr : std_logic_vector(3 downto 0);
+
+ signal lvl1_trg_information_buf, lvl1_trg_information_saved : std_logic_vector(23 downto 0);
+
begin
-- ADD_LVDS IN------------------------------------------------------------------
- ADO_LVDS_IN_PROC : for line in 0 to 25 generate --62 lines in total
+ ADO_LVDS_IN_PROC : for line in 0 to 30 generate --62 lines in total
IBUFDS_LVDS : IBUFDS
generic map (
DIFF_TERM => true
-- ADD_LVDS OUT------------------------------------------------------------------
- ADO_LVDS_OUT_PROC : for line in 0 to 4 generate
- OBUFDS_LVDS_LINE : OBUFDS
- generic map (
- IOSTANDARD => "LVDS_25"
- )
- port map (
- O => ADO_LVDS_OUT(line*2),
- OB => ADO_LVDS_OUT(line*2+1),
- I => ado_lv_out_i(line)
- );
- end generate ADO_LVDS_OUT_PROC;
+-- ADO_LVDS_OUT_PROC : for line in 0 to 3 generate
+-- OBUFDS_LVDS_LINE : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- O => ADO_LVDS_OUT(line*2),
+-- OB => ADO_LVDS_OUT(line*2+1),
+-- I => ado_lv_out_i(line)
+-- );
+-- end generate ADO_LVDS_OUT_PROC;
-------------------------------------------------------------------------------
REGIO_COMPILE_VERSION => regio_compile_version_i,
REGIO_HARDWARE_VERSION => regio_hardware_version_i,
REGIO_USE_1WIRE_INTERFACE => c_YES, --c_YES,c_NO,c_MONITOR
+ REGIO_USE_VAR_ENDPOINT_ID => c_NO,
CLOCK_FREQUENCY => 100
)
port map (
IPU_SEND_IN => lvl2_trigger_i,
IPU_TYPE_IN => lvl2_trigger_code_i,
IPU_NUMBER_IN => lvl2_trigger_tag_i,
- IPU_INFORMATION_IN => x"00",
+ IPU_INFORMATION_IN => ipu_information_in_i,
IPU_RND_CODE_IN => lvl2_rnd_number_out_i,
IPU_DATA_OUT => ipu_data_out_i,
IPU_DATAREADY_OUT => ipu_dataready_out_i,
REGIO_COMMON_CTRL_REG_OUT => open, --regio_common_ctrl_reg_out_i,
REGIO_REGISTERS_IN => regio_registers_in_i,
REGIO_REGISTERS_OUT => open,--regio_registers_out_i,
+ COMMON_STAT_REG_STROBE => open,
+ COMMON_CTRL_REG_STROBE => open,
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
REGIO_ADDR_OUT => regio_addr_out_i,
REGIO_READ_ENABLE_OUT => regio_read_enable_out_i,
REGIO_WRITE_ENABLE_OUT => regio_write_enable_out_i,
TIMER_TICKS_OUT => open,
STAT_DEBUG_1 => stat_debug_1_i,
STAT_DEBUG_2 => stat_debug_2_i);
- lvl2_local_busy_i <= lvl1_busy_i or lvl2_busy_i;
+
+ lvl2_local_busy_i <= lvl1_busy_i or lvl2_busy_i;
UPDATE_EB_CNTR : process (CLK, reset_i)
begin
if rising_edge(CLK) then
- if reset_i = '1' or (counter_for_event_builder_id = rw_register_i(9) and lvl1_finished_i = '1') then
+ if reset_i = '1' or (counter_for_event_builder_id = (rw_register_i(9)-1) and lvl1_finished_i = '1') then
counter_for_event_builder_id <= (others => '0');
elsif lvl1_finished_i = '1' then
counter_for_event_builder_id <= counter_for_event_builder_id + 1;
trg_information_in_i(6 downto 0) <= rw_register_i(8)(6 downto 0);
ipu_information_in_i(3 downto 0) <= event_builder_id(3 downto 0);
-
+ r_register_i(22)(3 downto 0) <= ipu_information_in_i(3 downto 0);
end generate TRBnet_CTS;
CLK40_IN => TDC_CLK,
LVL1_LVDS_TRIGGER_IN => lvds_add_on_data(4 downto 0),
LVL1_TTL_TRIGGER_IN => ADO_TTL(20 downto 16),
+ LVL1_RCTS_TYPE_IN => rcts_code_in_sync,
LVL1_FAST_TRIGG_IN => fast_ref_trigger,
LVL1_TIMING_TRIGGER_OUT => timing_signal,--ado_lv_out_i(0),
+ LVL1_TIMING_TEST_SIGNAL_OUT => test_timing_signal,
LVL1_APV_TRIGGER_OUT => apv_signal,--ado_lv_out_i(1),
LVL1_TRIGBOX_TRIGGER_IN => lvl1_trigger_out_i,
LVL1_TRIGBOX_TRIGGER_CODE_IN => lvl1_trigger_code_out_i,
);
--ado_lv_out_i <= (others => '0');
- ENABLE_TIMING_TRIGGER_OUT: if TRBV2_TYPE = 5 generate
+ ENABLE_TIMING_TRIGGER_OUT: if TRBV2_TYPE = 5 or TRBV2_TYPE = 3 generate
ado_lv_out_i(0) <= timing_signal;
ado_lv_out_i(1) <= apv_signal;
end generate ENABLE_TIMING_TRIGGER_OUT;
-
+
+ ADO_TTL(13 downto 10) <= (others => 'Z');
+ SYNC_SIGNALS : process (CLK, reset_i)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ rcts_code_in_sync <= x"1";
+ else
+ rcts_code_in_sync <= ADO_TTL(13 downto 10);
+ end if;
+ end if;
+ end process SYNC_SIGNALS;
+
end generate CTS_GENERATE;
ado_lv_out_i(2) <= lvl1_cts_busy_out_i;
ado_lv_out_i(3) <= lvl2_cts_busy_out_i;
- ado_lv_out_i(4) <= tdc_clk;--counter_for_clk(0);-- xor clk40_a;
+-- ado_lv_out_i(4) <= tdc_clk;--counter_for_clk(0);-- xor clk40_a;
end generate ENABLE_CTS_SIGNALS;
-
ENABLE_DEBUG_CTS : if DEBUG_OPTION = 2 generate
-
- ADO_TTL(0) <= lvl1_trigger_i;--TDC_CLK;
- ADO_TTL(1) <= lvl1_cts_busy_out_i;
- ADO_TTL(2) <= lvl2_local_busy_i;
+-- ADO_TTL(0) <= lvl1_trigger_i;--TDC_CLK;
+-- ADO_TTL(1) <= lvl1_cts_busy_out_i;
+-- ADO_TTL(2) <= lvl2_local_busy_i;
ADO_TTL(3) <= lvl1_finished_i;
- ADO_TTL(4) <= lvl2_trigger_i;
- ADO_TTL(5) <= lvl2_finished_i;
+-- ADO_TTL(4) <= lvl2_trigger_i;
+ ADO_TTL(4) <= lvl1_trigger_i;
+-- ADO_TTL(5) <= lvl2_finished_i;
+ ADO_TTL(5) <= lvl1_cts_busy_out_i;
ADO_TTL(6) <= trg_busy_out_i;--ipu_read_in_i;
ADO_TTL(7) <= ipu_dataready_out_i;
-- ADO_TTL(8) <= tdc_register_01_i(0);
CLK40_IN => TDC_CLK,
LVL1_LVDS_TRIGGER_IN => "00000",
LVL1_TTL_TRIGGER_IN => "00000",
+ LVL1_RCTS_TYPE_IN => x"1",
LVL1_FAST_TRIGG_IN => lvl1_trigger_i,
- LVL1_TIMING_TRIGGER_OUT => dummy_lvl1_trigger,
+ LVL1_TIMING_TRIGGER_OUT => open,
+ LVL1_TIMING_TEST_SIGNAL_OUT => open,
LVL1_APV_TRIGGER_OUT => open,
LVL1_TRIGBOX_TRIGGER_IN => '0',
LVL1_TRIGBOX_TRIGGER_CODE_IN => (others => '0'),
LVL1_LOCAL_BUSY => dummy_lvl1_trigger,
LVL1_TRBNET_BUSY => '0',
LVL1_CTS_BUSY_OUT => open,
- LVL1_TRIGGER_OUT => open,
+ LVL1_TRIGGER_OUT => dummy_lvl1_trigger,
LVL1_TRIGGER_CODE_OUT => open,
LVL1_TRIGGER_TAG_OUT => open,
LVL1_RND_NUMBER_OUT => open,
en_clk => '1',
signal_in => fast_ref_trigger,
pulse => trg_timing_trg_received_in_i);
-
+ --sim-- med_stat_op_in_i <= (others => '0');
THE_TRB_NET16_ENDPOINT_HADES_FULL_HANDLER : trb_net16_endpoint_hades_full_handler
generic map (
IBUF_DEPTH => (6,6,6,6),
APL_WRITE_ALL_WORDS => (c_NO,c_NO,c_NO,c_NO),
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => broadcast_bitmask_i,
+ BROADCAST_SPECIAL_ADDR => x"FF",
REGIO_NUM_STAT_REGS => 3,
REGIO_NUM_CTRL_REGS => 3,
REGIO_INIT_CTRL_REGS => (others => '0'),
REGIO_USE_1WIRE_INTERFACE => c_YES,
REGIO_USE_VAR_ENDPOINT_ID => c_NO,
CLOCK_FREQUENCY => 100,
+ TIMING_TRIGGER_RAW => c_YES,
DATA_INTERFACE_NUMBER => 1,
DATA_BUFFER_DEPTH => 14,
DATA_BUFFER_WIDTH => 32,
MED_DATA_IN => med_data_out_i,
MED_PACKET_NUM_IN => med_packet_num_out_i,
MED_READ_OUT => med_read_in_i(0),
- MED_STAT_OP_IN => med_stat_op_in_i,
+ MED_STAT_OP_IN => med_stat_op_in_i, --no_sim--
+--sim-- MED_STAT_OP_IN => (others => '0') ,
MED_CTRL_OP_OUT => med_ctrl_op_out_i,
TRG_TIMING_TRG_RECEIVED_IN => trg_timing_trg_received_in_i,--TRG_TIMING_TRG_RECEIVED_IN,
LVL1_TRG_DATA_VALID_OUT => lvl1_trigger_i,
LVL1_TRG_TYPE_OUT => lvl1_trigger_code_i,
LVL1_TRG_NUMBER_OUT => lvl1_trigger_tag_i,
LVL1_TRG_CODE_OUT => open,--lvl1_trigger_code_i,
- LVL1_TRG_INFORMATION_OUT => open,--LVL1_TRG_INFORMATION_OUT,
+ LVL1_TRG_INFORMATION_OUT => lvl1_trg_information_buf,--open,--LVL1_TRG_INFORMATION_OUT,
LVL1_INT_TRG_NUMBER_OUT => open,--
+ TRG_MULTIPLE_TRG_OUT => open,--
+ TRG_TIMEOUT_DETECTED_OUT => open,--
+ TRG_SPURIOUS_TRG_OUT => open,--
+ TRG_MISSING_TMG_TRG_OUT => open,--
+ TRG_SPIKE_DETECTED_OUT => open,--
FEE_TRG_RELEASE_IN => fee_trg_release_in_i,--
- FEE_TRG_STATUSBITS_IN => (others => '0'),
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in_buf,--(others => '0'),
FEE_DATA_IN => ipu_data_in_i,
FEE_DATA_WRITE_IN => trbnet_data_write_out_i,
FEE_DATA_FINISHED_IN => trbnet_data_finished_out_i,
CTRL_MPLEX => (others => '0'),
IOBUF_CTRL_GEN => (others => '0'),
STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open);
+ STAT_ADDR_DEBUG => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
trbnet_data_write_out_i(0) <= ipu_dataready_in_i;
trbnet_data_finished_out_i(0) <= lvl2_finished_i;
ipu_read_out_i <= '1';
DEBUG_TRBNET_HANDLER : if DEBUG_OPTION = 7 generate
- ADO_TTL(0) <= lvl1_trigger_i;
- ADO_TTL(1) <= fee_trg_release_in_i(0);
- ADO_TTL(2) <= trbnet_data_write_out_i(0);
- ADO_TTL(3) <= trbnet_data_finished_out_i(0);
- ADO_TTL(7 downto 4) <= ipu_data_in_i(31 downto 28);
- ADO_TTL(11 downto 8) <= tdc_register_01_i(27 downto 24);
- ADO_TTL(12) <= tdc_register_02_i(12);
- ADO_TTL(13) <= tdc_register_02_i(13);
- ADO_TTL(14) <= tdc_register_02_i(14);
- ADO_TTL(15) <= tdc_register_02_i(29);
-
+-- ADO_TTL(0) <= lvl1_trigger_i;
+-- ADO_TTL(1) <= fee_trg_release_in_i(0);
+-- ADO_TTL(2) <= trbnet_data_write_out_i(0);
+-- ADO_TTL(3) <= trbnet_data_finished_out_i(0);
+-- ADO_TTL(7 downto 4) <= ipu_data_in_i(31 downto 28);
+-- ADO_TTL(11 downto 8) <= tdc_register_01_i(27 downto 24);
+-- ADO_TTL(12) <= tdc_register_02_i(12);
+-- ADO_TTL(13) <= tdc_register_02_i(13);
+-- ADO_TTL(14) <= tdc_register_02_i(14);
+-- ADO_TTL(15) <= tdc_register_02_i(29);
+
+ ADO_TTL(15 downto 0) <= med_data_out_i;
+ -- ADO_TTL(18 downto 16) <= med_packet_num_out_i;
+ ADO_TTL(16) <= med_dataready_out_i(0);
+ ADO_TTL(35 downto 20) <= med_data_in_i;
+ -- ADO_TTL(38 downto 36) <= med_packet_num_in_i;
+ ADO_TTL(36) <= med_dataready_in_i(0);
-- ADO_TTL(4) <=
-- ADO_TTL(0) <=
-- ADO_TTL(0) <=
-- STAT_ADDR_DEBUG => open);
ENABLE_DEBUG_ENDPOINT : if DEBUG_OPTION = 1 generate
- ADO_TTL(0) <= lvl1_trigger_i;
- ADO_TTL(1) <= lvl1_cts_busy_out_i;
- ADO_TTL(2) <= trg_busy_out_i;
+
ADO_TTL(3) <= lvl1_finished_i;
- ADO_TTL(4) <= lvl2_trigger_i;
- ADO_TTL(5) <= CLK;
- ADO_TTL(6) <= ipu_read_out_i;
+ ADO_TTL(4) <= lvl1_trigger_i;
+ ADO_TTL(5) <= fee_trg_release_in_i(0);
+ ADO_TTL(6) <= trbnet_data_finished_out_i(0);
ADO_TTL(7) <= ipu_dataready_in_i;
ADO_TTL(15 downto 8) <= ipu_data_in_i(31 downto 24);
end generate ENABLE_DEBUG_ENDPOINT;
O => tlk_clk_r(0)
);
+ --sim-- med_data_out_i <=SIM_MED_DATA_IN ;
+ --sim-- med_packet_num_out_i <=SIM_MED_PACKET_NUM_IN ;
+ --sim-- med_dataready_out_i(0) <=SIM_MED_DATAREADY_IN ;
+ --sim--SIM_MED_READ_OUT <= med_read_in_i(0);
+ --sim--SIM_MED_DATA_OUT <= med_data_in_i;
+ --sim--SIM_MED_PACKET_NUM_OUT <= med_packet_num_in_i;
+ --sim--SIM_MED_DATAREADY_OUT <= med_dataready_in_i(0);
+ --sim-- med_read_out_i(0) <= SIM_MED_READ_IN;
+ --
TLK_API_INT : trb_net16_med_tlk
port map (
RESET => reset_i,
TLK_TX_ER => TLK_TX_ER,
SFP_LOS => SFP_LOS,
SFP_TX_DIS => SFP_TX_DIS,
- MED_DATAREADY_IN => med_dataready_in_i(0),
- MED_READ_IN => med_read_in_i(0),
- MED_DATA_IN => med_data_in_i,
- MED_PACKET_NUM_IN => med_packet_num_in_i,
- MED_DATAREADY_OUT => med_dataready_out_i(0),
- MED_READ_OUT => med_read_out_i(0),
- MED_DATA_OUT => med_data_out_i,
- MED_PACKET_NUM_OUT => med_packet_num_out_i,
+ MED_DATAREADY_IN => med_dataready_in_i(0), --no_sim--
+ MED_READ_IN => med_read_in_i(0), --no_sim--
+ MED_DATA_IN => med_data_in_i, --no_sim--
+ MED_PACKET_NUM_IN => med_packet_num_in_i, --no_sim--
+ MED_DATAREADY_OUT => med_dataready_out_i(0), --no_sim--
+ MED_READ_OUT => med_read_out_i(0), --no_sim--
+ MED_DATA_OUT => med_data_out_i, --no_sim--
+ MED_PACKET_NUM_OUT => med_packet_num_out_i, --no_sim--
+
+--sim-- MED_DATAREADY_IN => '0',
+--sim-- MED_READ_IN => '0',
+--sim-- MED_DATA_IN => (others =>'0'),
+--sim-- MED_PACKET_NUM_IN => (others =>'0'),
+--sim-- MED_DATAREADY_OUT => open,
+--sim-- MED_READ_OUT => open,
+--sim-- MED_DATA_OUT => open,
+--sim-- MED_PACKET_NUM_OUT => open,
+
STAT => open,
STAT_MONITOR => open,
- STAT_OP => med_stat_op_in_i,
+ STAT_OP => med_stat_op_in_i, --no_sim--
+--sim-- STAT_OP => open,
CTRL_OP => x"0000");
DGOOD <= not med_stat_op_in_i(9);
end generate TRBnet_MEDIA;
lvds_add_on_data(23) and
lvds_add_on_data(24) and
lvds_add_on_data(25) and
+ lvds_add_on_data(26) and
+ lvds_add_on_data(27) and
+ lvds_add_on_data(28) and
+ lvds_add_on_data(29) and
+ lvds_add_on_data(30) and
addon_clk ;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
ENBLE_TRIGGER_LOGIC: if TRBV2_TYPE = 3 generate
+-- THE_CLK_300: clk_300
+-- port map (
+-- CLKIN_IN => CLK,
+-- RST_IN => reset_i,
+-- CLKFX_OUT => clk200,
+-- CLK0_OUT => open,
+-- LOCKED_OUT => LOCKED_OUT);
+
+
THE_CLOCK200: clock200
port map (
CLKIN_IN => CLK,
CLK2X_OUT => clk200,
LOCKED_OUT => LOCKED_OUT);
- trigger_in_i <= lvds_add_on_data(19 downto 16) & ADO_TTL(29 downto 24) & ADO_TTL(21 downto 16) & lvds_add_on_data(15 downto 0);
+ trigger_in_i <= ADO_TTL(31 downto 30) & ADO_TTL(23 downto 22) & ADO_TTL(29 downto 24) & ADO_TTL(21 downto 16) & lvds_add_on_data(15 downto 0);
ADO_TTL(29 downto 24) <= (others => 'Z');
ADO_TTL(21 downto 16) <= (others => 'Z');
signal_in_i <= (others => '0') ;
-- ADO_TTL(35 downto 32) <= signal_out_i(3 downto 0);
- ADO_TTL(2 downto 1) <= signal_out_i(1 downto 0);
+
+ ADO_TTL(1) <= signal_out_i(0);
+ ADO_TTL(2) <= '0';
+ ADO_TTL(3) <= signal_out_i(1);
+ ADO_TTL(4) <= '0';
+
+ ADO_TTL(6) <= trg_busy_out_i;
+ ADO_TTL(7) <= lvl2_cts_busy_out_i;
+
+
+ --ADO_TTL(35 downto 34) <= signal_out_i(1 downto 0);
+
+ ADO_TTL(36) <= timing_signal or (rw_register_i(28)(31) and test_timing_signal);
+ ADO_TTL(37) <= mdc_timing_out or (rw_register_i(28)(31) and test_timing_signal);
+ MDC_DELAY_TIMING_CLK : process (CLK, reset_i)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ MDC_DELAY_TIMING_CURRENT <= IDLE;
+ mdc_delay_cntr_rst <= '1';
+ mdc_delay_cntr_up <= '0';
+ mdc_width_cntr_rst <= '1';
+ mdc_width_cntr_up <= '0';
+ mdc_timing_out <= '0';
+ else
+ MDC_DELAY_TIMING_CURRENT <= MDC_DELAY_TIMING_NEXT;
+ mdc_delay_cntr_rst <= mdc_delay_cntr_rst_fsm;
+ mdc_delay_cntr_up <= mdc_delay_cntr_up_fsm;
+ mdc_width_cntr_rst <= mdc_width_cntr_rst_fsm;
+ mdc_width_cntr_up <= mdc_width_cntr_up_fsm;
+ mdc_timing_out <= mdc_timing_out_fsm;
+ end if;
+ end if;
+ end process MDC_DELAY_TIMING_CLK;
+
+ MDC_DELAY_TIMING_PROC : process (CLK)
+ begin
+
+ mdc_delay_cntr_rst_fsm <= '1';
+ mdc_delay_cntr_up_fsm <= '0';
+ mdc_width_cntr_rst_fsm <= '1';
+ mdc_width_cntr_up_fsm <= '0';
+ mdc_timing_out_fsm <= '0';
+
+ case (MDC_DELAY_TIMING_CURRENT) is
+
+ when IDLE =>
+ if timing_signal = '1' then
+ MDC_DELAY_TIMING_NEXT <= MDC_DELAY_TIMING_A ;
+ else
+ MDC_DELAY_TIMING_NEXT <= IDLE;
+ end if;
+
+ when MDC_DELAY_TIMING_A =>
+ mdc_delay_cntr_rst_fsm <= '0';
+ mdc_delay_cntr_up_fsm <= '1';
+ if mdc_delay_cntr(6 downto 2) = rw_register_i(28)(28 downto 24) then
+ MDC_DELAY_TIMING_NEXT <= MDC_DELAY_TIMING_B;
+ else
+ MDC_DELAY_TIMING_NEXT <= MDC_DELAY_TIMING_A;
+ end if;
+
+ when MDC_DELAY_TIMING_B =>
+ mdc_width_cntr_rst_fsm <= '0';
+ mdc_width_cntr_up_fsm <= '1';
+ mdc_timing_out_fsm <= '1';
+ if mdc_width_cntr = x"a" then
+ MDC_DELAY_TIMING_NEXT <= IDLE;
+ else
+ MDC_DELAY_TIMING_NEXT <= MDC_DELAY_TIMING_B;
+ end if;
+
+ when others =>
+ MDC_DELAY_TIMING_NEXT <= IDLE;
+
+ end case;
+ end process MDC_DELAY_TIMING_PROC;
+
+ MDC_DELAY: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => mdc_delay_cntr_rst,
+ COUNT_OUT => mdc_delay_cntr,
+ UP_IN => mdc_delay_cntr_up,
+ DOWN_IN => '0');
+ MDC_TIMING_WIDTH: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 4)
+ port map (
+ CLK => CLK,
+ RESET => mdc_width_cntr_rst,
+ COUNT_OUT => mdc_width_cntr,
+ UP_IN => mdc_width_cntr_up,
+ DOWN_IN => '0');
+
+
- ADO_TTL(36) <= timing_signal;
- SCALER_REGISTER: for i in 0 to 31 generate
+-- SCALER_REGISTER: for i in 0 to 31 generate
+ SCALER_REGISTER: for i in 0 to 45 generate
r_register_i(i+27) <= scaler_out_i ((i+1)*32 -1 downto i*32);
end generate SCALER_REGISTER;
+
+
+
ADO_TTL(0) <= 'Z';
beam_inhibit_in_i <= ADO_TTL(0);
downscale_register_i <= rw_register_i(16) & rw_register_i(15) & rw_register_i(14) & rw_register_i(13);--
BEAM_INHIBIT_IN => beam_inhibit_in_i,
NO_TIMING_OUT => no_timing,
LVL1_BUSY_IN => lvl1_cts_busy_out_i,
+ LVL1_TRIGGER_ACCEPTED_IN => lvl1_trigger_i,
LVL1_TRIGGER_TAG_OUT => lvl1_trigger_tag_out_i,
LVL1_TRIGGER_CODE_OUT => lvl1_trigger_code_out_i,
LVL1_TRIGGER_OUT => lvl1_trigger_out_i,
TRIGGER_LOGIC_DEBUG_OUT => r_register_i(25),
IPU_DATA_IN => ipu_data_out_i,
IPU_DATA_VALID_IN => ipu_dataready_out_i,
+ TRBNET_LVL1_STATUS_IN => trg_status_bits_out_i,
+ TRBNET_BUSY_IN => trg_busy_out_i,
TOKEN_IN => triggbox_token_in,
DATA_OUT => triggbox_data_out,
DATA_VALID_OUT => triggbox_data_valid_out,
- TOKEN_OUT => triggbox_token_out
+ TOKEN_OUT => triggbox_token_out,
+ TRANSMIT_NO_DATA_IN => rw_register_i(5)(30)
-- IPU_DATA_IN => ...
);
-end generate ENBLE_TRIGGER_LOGIC;
-DUMMY_TRIGGER_LOGIC: if TRBV2_TYPE /= 3 generate
- trigbox_busy_out <= '0';
- lvl1_trigger_out_i <= '0';
-end generate DUMMY_TRIGGER_LOGIC;
+ end generate ENBLE_TRIGGER_LOGIC;
+ DUMMY_TRIGGER_LOGIC: if TRBV2_TYPE /= 3 generate
+ trigbox_busy_out <= '0';
+ lvl1_trigger_out_i <= '0';
+ end generate DUMMY_TRIGGER_LOGIC;
---------------------------------------------------------------------------
-- tdc interface
---------------------------------------------------------------------------
- --debug
-
--- ADO_TTL(0) <= not_hades_trigger;
--- ADO_TTL(1) <= trigger_to_tdc_i;
---
--- ADO_TTL(3) <= A_DATA_READY;
--- ADO_TTL(4) <= B_DATA_READY;
--- ADO_TTL(5) <= C_DATA_READY;
--- ADO_TTL(6) <= D_DATA_READY;
-
--- ADO_TTL(8) <= TOKEN_IN;
--- ADO_TTL(9) <= lvl2_busy_i;
--- ADO_TTL(10) <= bunch_reset_i;
--- ADO_TTL(11) <= event_reset_i;
--- ADO_TTL(12) <= TDC_CLK;
- --end debug
+
+
VIRT_TRST <= not fpga_register_06_i(5); --'1';
TDC_RESET <= '0'; --fpga_register_06_i(5);--'0';
- --TDC TRB
- TDC_INT_FOR_DIFF_PLATFORMSa : if TRBV2_TYPE = 0 or TRBV2_TYPE = 6 or TRBV2_TYPE = 7 generate
--- ADO_TTL(7) <= lvl1_busy_i;--token_out_i;
--- ADO_TTL(2) <= lvl1_busy_i;
+ TDC_INT_FOR_DIFF_PLATFORMSa : if (TRBV2_TYPE = 0 or TRBV2_TYPE = 6 or TRBV2_TYPE = 7) and TRBNET_ENABLE = 0 generate
start_tdc_readout_i <= lvl1_trigger_i;
+ save_trbnet_headers_i <= '1';
tdc_clk_i <= TDC_CLK;
readout_sdram_int_clk <= TDC_CLK;
tdc_data_in_i <= TDC_OUT;
d_data_ready_i <= D_DATA_READY;
token_in_i <= TOKEN_IN;
TOKEN_OUT <= token_out_i;
+ ADO_TTL(46) <= 'Z'; --for the hub on the veto
end generate TDC_INT_FOR_DIFF_PLATFORMSa;
+ TDC_INT_FOR_DIFF_PLATFORMSatrbnet : if TRBV2_TYPE = 0 and TRBNET_ENABLE = 1 generate
+ start_tdc_readout_i <= lvl1_valid_timing_trg_out_i or lvl1_valid_notiming_trg_out_i; --if
+ save_trbnet_headers_i <= lvl1_trigger_i;
+ tdc_clk_i <= TDC_CLK;
+ readout_sdram_int_clk <= TDC_CLK;
+ tdc_data_in_i <= TDC_OUT;
+ a_data_ready_i <= A_DATA_READY;
+ b_data_ready_i <= B_DATA_READY;
+ c_data_ready_i <= C_DATA_READY;
+ d_data_ready_i <= D_DATA_READY;
+ token_in_i <= TOKEN_IN;
+ TOKEN_OUT <= token_out_i;
+ ADO_TTL(46) <= 'Z'; --for the hub on the veto
+ end generate TDC_INT_FOR_DIFF_PLATFORMSatrbnet;
+
+
--Shower or MDC
TDC_INT_FOR_DIFF_PLATFORMSb : if TRBV2_TYPE = 1 or TRBV2_TYPE = 2 generate
start_tdc_readout_i <= lvl1_trigger_i;
+ save_trbnet_headers_i <= '1';
tdc_clk_i <= addon_clk;
readout_sdram_int_clk <= addon_clk;
tdc_data_in_i <= ADO_TTL(38 downto 7);
--CTS plus Vulom
TDC_INT_FOR_DIFF_PLATFORMSc : if TRBV2_TYPE = 4 generate
start_tdc_readout_i <= lvl1_trigger_i;
+ save_trbnet_headers_i <= '1';
tdc_clk_i <= CLK;
readout_sdram_int_clk <= CLK;
tdc_data_in_i <= vulom_event;
TDC_INT_FOR_DIFF_PLATFORMSd : if TRBV2_TYPE = 5 generate
start_tdc_readout_i <= lvl2_trigger_i;
not_ipu_dataready_out_i <= not ipu_busy_out_i;
+ save_trbnet_headers_i <= '1';
EXT_TRIGGER_1 : edge_to_pulse
port map (
end generate TDC_INT_FOR_DIFF_PLATFORMSd;
TDC_INT_FOR_DIFF_PLATFORMSe : if TRBV2_TYPE = 3 generate
+ save_trbnet_headers_i <= '1';
start_tdc_readout_i <= lvl1_trigger_i;
tdc_clk_i <= CLK;
readout_sdram_int_clk <= CLK;
ADO_TTL(12) <= TDC_CLK;
end generate DEBUG_STAND_ALONE;
+ CHOOSE_NUMBER_OF_ADD_DATA_A: if TRBV2_CONFIG_TYPE = 2 generate
+ how_many_add_data_i <= number_of_rpc_add_data;
+ end generate CHOOSE_NUMBER_OF_ADD_DATA_A;
+ CHOOSE_NUMBER_OF_ADD_DATA_B: if TRBV2_CONFIG_TYPE /= 2 generate
+ how_many_add_data_i <= fpga_register_06_i(23 downto 16);
+ end generate CHOOSE_NUMBER_OF_ADD_DATA_B;
+
+
TDC_INT : tdc_interfacev2
generic map (
ENABLE_DMA => ENABLE_DMA,
RESET => reset_i,
TDC_DATA_IN => tdc_data_in_i,
START_TDC_READOUT => start_tdc_readout_i, --lvl1_trigger_i,
+ SAVE_TRBNET_HEADERS => save_trbnet_headers_i,
A_TDC_ERROR => A_TDC_ERROR,
B_TDC_ERROR => B_TDC_ERROR,
C_TDC_ERROR => C_TDC_ERROR,
LVL1_RND_CODE => lvl1_rnd_number_out_i, --apl_seqnr_out_i, --tdc_tag_i,
LVL1_CODE => lvl1_trigger_code_i, --apl_data_out_i(3 downto 0), --tdc_code_i,
LVL2_TAG => lvl2_trigger_tag_i(7 downto 0), --apl_seqnr_out_i, --tdc_tag_i,
- HOW_MANY_ADD_DATA => fpga_register_06_i(23 downto 16),
+ HOW_MANY_ADD_DATA => how_many_add_data_i,--
ADDITIONAL_DATA => additional_data_i,
LVL2_TRIGGER => lvl2_trigger_i,
TDC_DATA_OUT => tdc_data_out_i,
DATA_IN => data_out_i,
DATA_OUT => data_in_i,
SDRAM_BUSY => sdram_busy_i,
+ TDC_DATA_DOWNSCALE_IN => lvl1_trg_information_saved(17),
TRBNET_DATA_FINISHED_OUT => open,-- trbnet_data_finished_out_i(0),
TRBNET_DATA_WRITE_OUT => open,
TRBNET_DATA_OUT => open--trbnet_data_out_i
);
+
+ fee_trg_statusbits_in_buf(3 downto 0) <= tdc_register_00_i(3 downto 0);
+ fee_trg_statusbits_in_buf(4) <= tdc_register_00_i(12);
+
+ SAVE_LVL1_INFO : process (CLK, reset_i)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ lvl1_trg_information_saved <= (others => '0');
+ elsif lvl1_trigger_i = '1' then
+ lvl1_trg_information_saved <= lvl1_trg_information_buf;
+ else
+ lvl1_trg_information_saved <= lvl1_trg_information_saved;
+ end if;
+ end if;
+ end process SAVE_LVL1_INFO;
+
-----------------------------------------------------------------------------
-- sdram to tdc interface
-----------------------------------------------------------------------------
MED_READ_IN => med_read_in_i,
MED_PACKET_NUM_IN => med_packet_num_in_i,
MED_PACKET_NUM_OUT => med_packet_num_out_i,
- MED_STAT_OP => med_stat_op_in_i,
+ MED_STAT_OP => med_stat_op_in_i,
MED_CTRL_OP => med_ctrl_op_out_i,
LINK_DEBUG => link_debug_i,
TX_DIS => open,
-- scalers - there has to be an GP-AddOn with correct configuration see GP_AddOn
-- directory (not available now).
-------------------------------------------------------------------------
- SCALERS_ON_TTL_ENABLE : if SCALERS_ENABLE = 1 generate
- SCALER : for ttl_line in 0 to 7 generate
- PULSE_TO_EDGE : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => ADO_TTL(ttl_line),
- pulse => scaler_pulse(ttl_line));
- SCALER : simpleupcounter_32bit
- port map (
- QOUT => scaler_counter(ttl_line),
- UP => scaler_pulse(ttl_line),
- CLK => CLK,
- CLR => reset_i);
+ SCALERS_ON_LVDS_ENABLE : if SCALERS_ENABLE = 1 or TRBV2_CONFIG_TYPE = 2 generate
+ SET_SCALER_RESET : process (CLK, reset_i)
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ scaler_reset <= '1';
+ elsif lvl1_trigger_code_i = x"E" and lvl1_finished_i = '1' then
+ scaler_reset <= '1';
+ else
+ scaler_reset <= '0';
+ end if;
+ end if;
+ end process SET_SCALER_RESET;
+
+ SCALER : for lvds_line in 0 to NUMBER_OFF_ADD_DATA - 1 generate
+ FIRST_6: if lvds_line < 14 generate
+ PULSE_TO_EDGE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvds_add_on_data(lvds_line),
+ pulse => scaler_pulse(lvds_line));
+
+ RPC_SCALER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => scaler_reset,
+ COUNT_OUT => scaler_counter(lvds_line),
+ UP_IN => scaler_pulse(lvds_line),
+ DOWN_IN => '0');
+ additional_data_i((lvds_line+1)*32-1 downto lvds_line*32) <= scaler_counter(lvds_line);
+ end generate FIRST_6;
+
+ SEVENTH: if lvds_line > 14 generate
+ PULSE_TO_EDGE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvds_add_on_data(27+14-lvds_line),
+ pulse => scaler_pulse(lvds_line));
+
+ RPC_SCALER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => scaler_reset,
+ COUNT_OUT => scaler_counter(lvds_line),
+ UP_IN => scaler_pulse(lvds_line),
+ DOWN_IN => '0');
+ additional_data_i((lvds_line+1)*32-1 downto lvds_line*32) <= scaler_counter(lvds_line);
+ end generate SEVENTH;
+
end generate SCALER;
- ADO_TTL(7 downto 0) <= (others => 'Z');
- end generate SCALERS_ON_TTL_ENABLE;
-
-
+ end generate SCALERS_ON_LVDS_ENABLE;
+
+ RPC_SCALERS_ENABLE: if TRBV2_CONFIG_TYPE=2 generate
+
+ ENABLE_RPC_SCALERS_ON_MDC_CAL : process (CLK,reset_i,lvl1_trigger_code_i, fpga_register_06_i(0))
+ begin
+ if rising_edge(CLK) then
+ if reset_i = '1' then
+ number_of_rpc_add_data <= x"00";
+ elsif lvl1_trigger_code_i = x"E" and fpga_register_06_i(0) = '1' and lvl1_trigger_i = '1' then --
+ --valid only when there is data valid to
+ number_of_rpc_add_data <= x"13"; --16 individual and 3 global multiplicities
+ else
+ number_of_rpc_add_data <= fpga_register_06_i(23 downto 16); --x"08";
+ end if;
+ end if;
+ end process ENABLE_RPC_SCALERS_ON_MDC_CAL;
+
+ end generate RPC_SCALERS_ENABLE;
--------------------------------------------------------------------------
jspc29 / trbv2.git / commitdiff