schematics update

diff --git a/schematics.htm b/schematics.htm
index ba8ce6bf3ca8c14b4d8f789b00dc896b20274e2d..a4d89d47ddf082fb3a81d002be798ec66a50e7f8 100644 (file)
--- a/schematics.htm
+++ b/schematics.htm
@@ -7,7 +7,11 @@
     <th> Description </th>
   </tr>
 <tr> <td><a href="schematics/trb3.pdf">TRB3</a> <td>The main TRB3 board. 
-<tr> <td><a href="schematics/clockdistribution.png">TRB3 clock distribution</a> <td>The distribution of clock and trigger signals on the TRB3
+  
+  <tr>
+    <th> AddOn </th>
+    <th> Description </th>
+  </tr>
 <tr> <td><a href="schematics/4conn.pdf">4conn AddOn</a> <td>AddOn with four 40-pin connectors, compatible to connector on Padiwa front-end module
 <tr> <td><a href="schematics/ada1.pdf">ADA1 AddOn</a> <td>AddOn with two 80-pin connectors, compatible to input on TRB2
 <tr> <td><a href="schematics/addon_ada_alles.pdf">ADA2 AddOn</a> <td>AddOn with two 80-pin connectors, compatible to input on TRB2
@@ -15,6 +19,16 @@
 <tr> <td><a href="schematics/multitest.pdf">MultiTest AddOn</a> <td>AddOn with several test ciruits
 <tr> <td><a href="schematics/sfp.pdf">SFP AddOn</a> <td>AddOn with 6 SFP cages. For use as TrbNet hub
 <tr> <td><a href="schematics/cts.pdf">CTS AddOn</a> <td>AddOn for the central FPGA with additional I/O for CTS
+
+  <tr>
+    <th> FEE </th>
+    <th> Description </th>
+  </tr>
 <tr> <td><a href="schematics/PADIWA3-all.pdf">PADIWA3</a> <td>for signal discrimination
 <tr> <td><a href="schematics/padiwa-amps1.pdf">PADIW-AMPS1</a> <td>for signal discrimination and charge determination
+<tr>
+    <th> Other </th>
+    <th> Description </th>
+  </tr>
+<tr> <td><a href="schematics/clockdistribution.png">TRB3 clock distribution</a> <td>The distribution of clock and trigger signals on the TRB3
 </table>

diff --git a/schematics/clockdistribution.png b/schematics/clockdistribution.png
new file mode 100644 (file)
index 0000000..c8ccf52
Binary files /dev/null and b/schematics/clockdistribution.png differ