constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
--input monitor and trigger generation logic
- constant INCLUDE_TDC : integer := c_YES;
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_TDC : integer := c_NO;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
constant INCLUDE_STATISTICS : integer := c_YES;
- constant TRIG_GEN_INPUT_NUM : integer := 0;
- constant TRIG_GEN_OUTPUT_NUM : integer := 0;
- constant MONITOR_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_INPUT_NUM : integer := 40;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 2;
+ constant MONITOR_INPUT_NUM : integer := 40;
constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
constant TRIGGER_COIN_COUNT : integer := 1;
constant TRIGGER_PULSER_COUNT : integer := 3;
constant TRIGGER_RAND_PULSER : integer := 1;
- constant TRIGGER_ADDON_COUNT : integer := 2;
+ constant TRIGGER_ADDON_COUNT : integer := 4;
constant PERIPH_TRIGGER_COUNT : integer := 0;
- constant ADDON_LINE_COUNT : integer := 18;
+ constant ADDON_LINE_COUNT : integer := 44;
constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
--TODO:
-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
TOPNAME => "trb3sc_cts",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.9_x64',
-synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
+synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1',
#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
BACK_LVDS : inout std_logic_vector( 1 downto 0);
BACK_GPIO : inout std_logic_vector( 3 downto 0);
- SPARE_IN : in std_logic_vector( 1 downto 0);
- INP : in std_logic_vector(95 downto 64);
+ SPARE_IN : in std_logic_vector( 1 downto 0);
+ KEL : in std_logic_vector(40 downto 1);
RJ_IO : out std_logic_vector( 3 downto 0); --0, inner RJ trigger output
--LED
attribute syn_useioff of FLASH_OUT : signal is true;
attribute syn_useioff of SPARE_IN : signal is false;
- attribute syn_useioff of INP : signal is false;
+ attribute syn_useioff of KEL : signal is false;
end entity;
signal med_ctrl_op : std_logic_vector (5*16-1 downto 0);
signal rdack, wrack : std_logic;
- signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal trigger_gen_outputs_i: std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0);
signal trigger_busy_i : std_logic;
signal cts_trigger_out : std_logic;
THE_CTS : CTS
generic map (
EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic
+ PLATTFORM => 1, --TRB3sc+KEL+RJ45
OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,
- ADDON_GROUPS => 2,
- ADDON_GROUP_UPPER => (1,17, others => 0)
+ ADDON_GROUPS => 3,
+ ADDON_GROUP_UPPER => (2,40,2, others => 0)
)
port map (
CLK => clk_sys,
);
cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
- cts_addon_triggers_in(17 downto 2) <= INP(79 downto 64);
+ cts_addon_triggers_in(41 downto 2) <= KEL(40 downto 1);
+ cts_addon_triggers_in(43 downto 42) <= trigger_gen_outputs_i;
buscts_tx.nack <= '0';
buscts_tx.ack <= '0';
CLK => clk_sys,
RESET_IN => reset_i,
- TIMER_CLOCK_IN => INP(80),
- TIMER_RESET_IN => INP(81),
+ TIMER_CLOCK_IN => KEL(20),
+ TIMER_RESET_IN => KEL(21),
TRIGGER_IN => cts_trigger_out,
BUSRDO_RX => cts_rdo_rx,
CLK => clk_sys,
RESET_IN => reset_i,
- MBS_IN => INP(80),
+ MBS_IN => KEL(20),
CLK_200 => clk_full,
TRG_ASYNC_OUT => mbs_async_out, --TODO MBS async connect to TDC
ADC_CLK => ADC_CLK,
--Trigger & Monitor
MONITOR_INPUTS => monitor_inputs_i,
- TRIG_GEN_INPUTS => open,
- TRIG_GEN_OUTPUTS => open,
+ TRIG_GEN_INPUTS => monitor_inputs_i,
+ TRIG_GEN_OUTPUTS => trigger_gen_outputs_i,
--SED
SED_ERROR_OUT => sed_error_i,
--Slowcontrol
DEBUG_OUT => open
);
-monitor_inputs_i <= INP;
+monitor_inputs_i <= KEL;
gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate
do_reboot_i <= common_ctrl_reg(15);
---------------------------------------------------------------------------
-- I/O
---------------------------------------------------------------------------
- spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
- DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
- DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
- DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
- spi_miso(3 downto 0) <= (others => '0');
- spi_miso(15 downto 7) <= (others => '0');
+-- spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
+-- DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
+-- DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
+-- DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
+-- spi_miso(3 downto 0) <= (others => '0');
+-- spi_miso(15 downto 7) <= (others => '0');
RJ_IO(0) <= cts_trigger_out;
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
- THE_TDC : entity work.TDC_record
- generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
- STATUS_REG_NR => 21, -- Number of status regs
- DEBUG => c_YES,
- SIMULATION => c_NO)
- port map (
- RESET => reset_i,
- CLK_TDC => clk_full_osc,
- CLK_READOUT => clk_sys, -- Clock for the readout
- REFERENCE_TIME => cts_trigger_out, -- Reference time input
- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
- -- Trigger signals from handler
- BUSRDO_RX => cts_rdo_rx,
- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
- -- Slow control bus
- BUS_RX => bustdc_rx,
- BUS_TX => bustdc_tx,
- -- Dubug signals
- INFO_IN => timer,
- LOGIC_ANALYSER_OUT => open
- );
-
- -- For single edge measurements
- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2+64 downto 64);
- end generate;
-
- -- For ToT Measurements
- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
- Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate
- hit_in_i(i*2+1) <= INP(i+64);
- hit_in_i(i*2+2) <= not INP(i+64);
- end generate Gen_Hit_In_Signals;
- end generate;
-
+-- THE_TDC : entity work.TDC_record
+-- generic map (
+-- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+-- STATUS_REG_NR => 21, -- Number of status regs
+-- DEBUG => c_YES,
+-- SIMULATION => c_NO)
+-- port map (
+-- RESET => reset_i,
+-- CLK_TDC => clk_full_osc,
+-- CLK_READOUT => clk_sys, -- Clock for the readout
+-- REFERENCE_TIME => cts_trigger_out, -- Reference time input
+-- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+-- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+-- -- Trigger signals from handler
+-- BUSRDO_RX => cts_rdo_rx,
+-- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM),
+-- -- Slow control bus
+-- BUS_RX => bustdc_rx,
+-- BUS_TX => bustdc_tx,
+-- -- Dubug signals
+-- INFO_IN => timer,
+-- LOGIC_ANALYSER_OUT => open
+-- );
+--
+-- -- For single edge measurements
+-- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+-- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2+64 downto 64);
+-- end generate;
+--
+-- -- For ToT Measurements
+-- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+-- Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate
+-- hit_in_i(i*2+1) <= INP(i+64);
+-- hit_in_i(i*2+2) <= not INP(i+64);
+-- end generate Gen_Hit_In_Signals;
+-- end generate;
end architecture;
#################################################################\r
# Pin-header IO\r
#################################################################\r
-#on KEL1\r
-LOCATE COMP "INP_64" SITE "AP5";\r
-LOCATE COMP "INP_65" SITE "AP2";\r
-LOCATE COMP "INP_66" SITE "AN1";\r
-LOCATE COMP "INP_67" SITE "AN3";\r
-LOCATE COMP "INP_68" SITE "AL5";\r
-LOCATE COMP "INP_69" SITE "AM6";\r
-LOCATE COMP "INP_70" SITE "AL4";\r
-LOCATE COMP "INP_71" SITE "AJ5";\r
-LOCATE COMP "INP_72" SITE "AJ2";\r
-LOCATE COMP "INP_73" SITE "AL3";\r
-LOCATE COMP "INP_74" SITE "AD9";\r
-LOCATE COMP "INP_75" SITE "AJ4";\r
-LOCATE COMP "INP_76" SITE "V4";\r
-LOCATE COMP "INP_77" SITE "V5"; \r
-LOCATE COMP "INP_78" SITE "T9";\r
-LOCATE COMP "INP_79" SITE "T2";\r
- #on KEL2\r
-LOCATE COMP "INP_80" SITE "AP29";\r
-LOCATE COMP "INP_81" SITE "AP33";\r
-LOCATE COMP "INP_82" SITE "AN34";\r
-LOCATE COMP "INP_83" SITE "AP31";\r
-LOCATE COMP "INP_84" SITE "AN32";\r
-LOCATE COMP "INP_85" SITE "AM29";\r
-LOCATE COMP "INP_86" SITE "AL31";\r
-LOCATE COMP "INP_87" SITE "AL30"; \r
-LOCATE COMP "INP_88" SITE "AL34";\r
-LOCATE COMP "INP_89" SITE "AJ31";\r
-LOCATE COMP "INP_90" SITE "AH33";\r
-LOCATE COMP "INP_91" SITE "AL32";\r
-LOCATE COMP "INP_92" SITE "AF32";\r
-LOCATE COMP "INP_93" SITE "AE32";\r
-LOCATE COMP "INP_94" SITE "AE30";\r
-LOCATE COMP "INP_95" SITE "AD26";\r
-DEFINE PORT GROUP "INP_group" "INP*" ;\r
-IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
-\r
-LOCATE COMP "DAC_IN_SDI_5" SITE "P7";\r
-LOCATE COMP "DAC_IN_SDI_6" SITE "M29";\r
-DEFINE PORT GROUP "IN_group" "DAC_IN*" ;\r
-IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
-\r
-\r
-LOCATE COMP "DAC_OUT_SDO_5" SITE "R8";\r
-LOCATE COMP "DAC_OUT_SCK_5" SITE "R2";\r
-LOCATE COMP "DAC_OUT_CS_5" SITE "P9";\r
-LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28";\r
-LOCATE COMP "DAC_OUT_SCK_6" SITE "M34";\r
-LOCATE COMP "DAC_OUT_CS_6" SITE "L28";\r
-DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ;\r
-IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;\r
-\r
+# #on KEL1\r
+# LOCATE COMP "INP_64" SITE "AP5";\r
+# LOCATE COMP "INP_65" SITE "AP2";\r
+# LOCATE COMP "INP_66" SITE "AN1";\r
+# LOCATE COMP "INP_67" SITE "AN3";\r
+# LOCATE COMP "INP_68" SITE "AL5";\r
+# LOCATE COMP "INP_69" SITE "AM6";\r
+# LOCATE COMP "INP_70" SITE "AL4";\r
+# LOCATE COMP "INP_71" SITE "AJ5";\r
+# LOCATE COMP "INP_72" SITE "AJ2";\r
+# LOCATE COMP "INP_73" SITE "AL3";\r
+# LOCATE COMP "INP_74" SITE "AD9";\r
+# LOCATE COMP "INP_75" SITE "AJ4";\r
+# LOCATE COMP "INP_76" SITE "V4";\r
+# LOCATE COMP "INP_77" SITE "V5"; \r
+# LOCATE COMP "INP_78" SITE "T9";\r
+# LOCATE COMP "INP_79" SITE "T2";\r
+# #on KEL2\r
+# LOCATE COMP "INP_80" SITE "AP29";\r
+# LOCATE COMP "INP_81" SITE "AP33";\r
+# LOCATE COMP "INP_82" SITE "AN34";\r
+# LOCATE COMP "INP_83" SITE "AP31";\r
+# LOCATE COMP "INP_84" SITE "AN32";\r
+# LOCATE COMP "INP_85" SITE "AM29";\r
+# LOCATE COMP "INP_86" SITE "AL31";\r
+# LOCATE COMP "INP_87" SITE "AL30"; \r
+# LOCATE COMP "INP_88" SITE "AL34";\r
+# LOCATE COMP "INP_89" SITE "AJ31";\r
+# LOCATE COMP "INP_90" SITE "AH33";\r
+# LOCATE COMP "INP_91" SITE "AL32";\r
+# LOCATE COMP "INP_92" SITE "AF32";\r
+# LOCATE COMP "INP_93" SITE "AE32";\r
+# LOCATE COMP "INP_94" SITE "AE30";\r
+# LOCATE COMP "INP_95" SITE "AD26";\r
+# DEFINE PORT GROUP "INP_group" "INP*" ;\r
+# IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+# \r
+# LOCATE COMP "DAC_IN_SDI_5" SITE "P7";\r
+# LOCATE COMP "DAC_IN_SDI_6" SITE "M29";\r
+# DEFINE PORT GROUP "IN_group" "DAC_IN*" ;\r
+# IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
+# \r
+# \r
+# LOCATE COMP "DAC_OUT_SDO_5" SITE "R8";\r
+# LOCATE COMP "DAC_OUT_SCK_5" SITE "R2";\r
+# LOCATE COMP "DAC_OUT_CS_5" SITE "P9";\r
+# LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28";\r
+# LOCATE COMP "DAC_OUT_SCK_6" SITE "M34";\r
+# LOCATE COMP "DAC_OUT_CS_6" SITE "L28";\r
+# DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ;\r
+# IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;\r
+LOCATE COMP "KEL_1" SITE "AP5";\r
+LOCATE COMP "KEL_2" SITE "AP2";\r
+LOCATE COMP "KEL_3" SITE "AN1";\r
+LOCATE COMP "KEL_4" SITE "AN3";\r
+LOCATE COMP "KEL_5" SITE "AL5";\r
+LOCATE COMP "KEL_6" SITE "AM6";\r
+LOCATE COMP "KEL_7" SITE "AL4";\r
+LOCATE COMP "KEL_8" SITE "AJ5";\r
+LOCATE COMP "KEL_9" SITE "AJ2";\r
+LOCATE COMP "KEL_10" SITE "AL3";\r
+LOCATE COMP "KEL_11" SITE "AD9";\r
+LOCATE COMP "KEL_12" SITE "AJ4";\r
+LOCATE COMP "KEL_13" SITE "V4";\r
+LOCATE COMP "KEL_14" SITE "V5";\r
+LOCATE COMP "KEL_15" SITE "T9";\r
+LOCATE COMP "KEL_16" SITE "T2";\r
+LOCATE COMP "KEL_17" SITE "P7";\r
+LOCATE COMP "KEL_18" SITE "R8";\r
+LOCATE COMP "KEL_19" SITE "R2";\r
+LOCATE COMP "KEL_20" SITE "P9";\r
+LOCATE COMP "KEL_21" SITE "AP29";\r
+LOCATE COMP "KEL_22" SITE "AP33";\r
+LOCATE COMP "KEL_23" SITE "AN34";\r
+LOCATE COMP "KEL_24" SITE "AP31";\r
+LOCATE COMP "KEL_25" SITE "AN32";\r
+LOCATE COMP "KEL_26" SITE "AM29";\r
+LOCATE COMP "KEL_27" SITE "AL31";\r
+LOCATE COMP "KEL_28" SITE "AL30";\r
+LOCATE COMP "KEL_29" SITE "AL34";\r
+LOCATE COMP "KEL_30" SITE "AJ31";\r
+LOCATE COMP "KEL_31" SITE "AH33";\r
+LOCATE COMP "KEL_32" SITE "AL32";\r
+LOCATE COMP "KEL_33" SITE "AF32";\r
+LOCATE COMP "KEL_34" SITE "AE32";\r
+LOCATE COMP "KEL_35" SITE "AE30";\r
+LOCATE COMP "KEL_36" SITE "AD26";\r
+LOCATE COMP "KEL_37" SITE "M29";\r
+LOCATE COMP "KEL_38" SITE "AC28";\r
+LOCATE COMP "KEL_39" SITE "M34";\r
+LOCATE COMP "KEL_40" SITE "L28";\r
+DEFINE PORT GROUP "KEL_group" "KEL*" ;\r
+IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;\r
\r
\r
#################################################################\r
jspc29 / trb3sc.git / commitdiff