--- /dev/null
+
+vhdl work "../trb_net_std.vhd"
+vhdl work "../trb_net16_term_buf.vhd"
+vhdl work "../xilinx/shift_lut_x16.vhd"
+vhdl work "../xilinx/xilinx_fifo_lut.vhd"
+
+vhdl work "../xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd"
+-- vhdl work "../xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd"
+vhdl work "../xilinx/virtex2/trb_net16_fifo_arch.vhd"
+-- vhdl work "../trb_net16_fifo.vhd"
+
+vhdl work "../trb_net_CRC.vhd"
+vhdl work "../trb_net_onewire.vhd"
+vhdl work "../basics/rom_16x8.vhd"
+vhdl work "../basics/ram.vhd"
+vhdl work "../basics/ram_16x8_dp.vhd"
+vhdl work "../basics/ram_16x16_dp.vhd"
+vhdl work "../trb_net16_addresses.vhd"
+vhdl work "../basics/ram_dp.vhd"
+vhdl work "../trb_net16_term.vhd"
+vhdl work "../trb_net16_term_buf.vhd"
+vhdl work "../trb_net_sbuf.vhd"
+vhdl work "../trb_net16_sbuf.vhd"
+vhdl work "../trb_net16_regIO.vhd"
+vhdl work "../trb_net_priority_encoder.vhd"
+vhdl work "../trb_net_dummy_fifo.vhd"
+vhdl work "../trb_net16_dummy_fifo.vhd"
+vhdl work "../trb_net16_term_ibuf.vhd"
+vhdl work "../trb_net_priority_arbiter.vhd"
+vhdl work "../trb_net_pattern_gen.vhd"
+vhdl work "../trb_net16_obuf_nodata.vhd"
+vhdl work "../trb_net16_obuf.vhd"
+vhdl work "../trb_net16_ibuf.vhd"
+vhdl work "../trb_net16_api_base.vhd"
+vhdl work "../trb_net16_iobuf.vhd"
+vhdl work "../trb_net16_io_multiplexer.vhd"
+vhdl work "../testbench/trb_net16_dummy_apl.vhd"
+-- vhdl work "../testbench/trb_net16_dummy_passive_apl.vhd"
+vhdl work "../trb_net16_ipudata.vhd"
+vhdl work "../trb_net16_trigger.vhd"
+vhdl work "../trb_net16_endpoint_hades_full.vhd"
+vhdl work "../trb_net16_endpoint_active_4_channel.vhd"
+
+-- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
+
+-- vhdl work "../trb_net16_endpoint_1_trg_0_api.vhd"
+-- vhdl work "../trb_net_med_8bit_slow.vhd"
+
+vhdl work "../trb_net16_hub_func.vhd"
+vhdl work "../trb_net16_hub_base.vhd"
+vhdl work "../trb_net16_hub_logic.vhd"
+vhdl work "single_testbench.vhd"
\ No newline at end of file
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+
+entity testbench is
+end entity testbench;
+
+architecture testbench_arch of testbench is
+
+ component trb_net16_endpoint_active_4_channel is
+ generic (
+ IBUF_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE;
+ API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE;
+ API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_SECURE_MODE;
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_STAT_OP_IN : in std_logic_vector (15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector (15 downto 0);
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_READ_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_SHORT_TRANSFER_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_DTYPE_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*4-1 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*32-1 downto 0);
+ APL_SEND_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_TARGET_ADDRESS_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*16-1 downto 0);
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*c_NUM_WIDTH-1 downto 0);
+ APL_TYP_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*3-1 downto 0);
+ APL_DATAREADY_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_READ_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*8-1 downto 0);
+ APL_LENGTH_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*16-1 downto 0);
+
+ -- Status and control port
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ MPLEX_CTRL : in std_logic_vector (31 downto 0);
+ CTRL_GEN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*32-1 downto 0)
+ );
+ end component;
+
+ component trb_net16_endpoint_hades_full is
+ generic (
+ USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
+ IBUF_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
+ FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6);
+ IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+ INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
+ APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
+ REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ --standard values for output registers
+ REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
+ --set to 0 for unused ctrl registers to save resources
+ REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
+ --set to 0 for each unused bit in a register
+ REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
+ REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
+ REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F00E";
+ REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ REGIO_USE_1WIRE_INTERFACE: integer := c_YES
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+
+ MED_STAT_OP_IN : in std_logic_vector(15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0);
+
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_OUT : out std_logic;
+ LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
+ LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_IN : in std_logic := '0';
+
+
+ --Data Port
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_OUT: out std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_IN : in std_logic_vector (31 downto 0);
+ IPU_DATAREADY_IN : in std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_IN : in std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_OUT : out std_logic;
+ IPU_LENGTH_IN : in std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
+ REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
+ REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
+ REGIO_IDRAM_WR_IN : in std_logic := '0';
+ REGIO_ONEWIRE_INOUT : inout std_logic;
+ --Additional r/w access to ctrl registers
+ REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ REGIO_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_EXT_REG_WRITE_IN : in std_logic := '0';
+ REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0');
+
+ STAT_DEBUG_IPU : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_1 : out std_logic_vector (31 downto 0);
+ STAT_DEBUG_2 : out std_logic_vector (31 downto 0);
+ MED_STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_MPLEX : in std_logic_vector (31 downto 0);
+ IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0);
+ STAT_ONEWIRE : out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+
+ component trb_net16_dummy_apl is
+ generic (
+ TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"ffff";
+ PREFILL_LENGTH : integer := 1;
+ TRANSFER_LENGTH : integer := 5 -- length of dummy data
+ -- might not work with transfer_length > api_fifo
+ -- because of incorrect handling of fifo_full_in!
+ -- shorttransfer is not working too
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_OUT: out std_logic_vector (2 downto 0);
+ APL_DATAREADY_OUT: out std_logic; -- Data word is valid and should be transmitted
+ APL_READ_IN: in std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_OUT: out std_logic; --
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_OUT: out std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+ -- Receiver port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_IN:in std_logic_vector (2 downto 0);
+ APL_TYP_IN: in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_IN: in std_logic; -- Data word is valid and might be read out
+ APL_READ_OUT: out std_logic; -- Read data word
+ -- APL Control port
+ APL_RUN_IN: in std_logic; -- Data transfer is running
+ -- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_IN: in std_logic_vector (7 downto 0)
+ );
+ end component;
+
+ signal CLK : std_logic := '1';
+ signal RESET : std_logic := '1';
+ signal CLK_EN : std_logic := '1';
+
+ signal MED_DATAREADY_IN : std_logic;
+ signal MED_READ_IN : std_logic;
+ signal MED_DATAREADY_OUT : std_logic;
+ signal MED_READ_OUT : std_logic;
+ signal MED_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
+ signal MED_PACKET_NUM_IN : std_logic_vector(2 downto 0);
+ signal MED_DATA_IN : std_logic_vector(15 downto 0);
+ signal MED_DATA_OUT : std_logic_vector(15 downto 0);
+ signal MED_STAT_OP : std_logic_vector(31 downto 0);
+ signal MED_CTRL_OP : std_logic_vector(31 downto 0);
+
+ signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
+ signal LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal LVL1_TRG_RELEASE_IN : std_logic;
+
+ signal IPU_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal IPU_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal IPU_START_READOUT_OUT : std_logic;
+ signal IPU_DATA_IN : std_logic_vector(31 downto 0);
+ signal IPU_DATAREADY_IN : std_logic;
+ signal IPU_READOUT_FINISHED_IN : std_logic;
+ signal IPU_READ_OUT : std_logic;
+ signal IPU_LENGTH_IN : std_logic_vector(15 downto 0);
+ signal IPU_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal ipu_answer_delay : std_logic_vector(11 downto 0);
+
+ signal REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal REGIO_REGISTERS_IN : std_logic_vector(32*2**(3)-1 downto 0);
+ signal REGIO_REGISTERS_OUT : std_logic_vector(32*2**(3)-1 downto 0);
+ signal REGIO_ADDR_OUT : std_logic_vector(15 downto 0);
+ signal REGIO_READ_ENABLE_OUT : std_logic;
+ signal REGIO_WRITE_ENABLE_OUT : std_logic;
+ signal REGIO_DATA_OUT : std_logic_vector(31 downto 0);
+ signal REGIO_DATA_IN : std_logic_vector(31 downto 0);
+ signal REGIO_DATAREADY_IN : std_logic;
+ signal REGIO_NO_MORE_DATA_IN : std_logic;
+ signal REGIO_WRITE_ACK_IN : std_logic;
+ signal REGIO_UNKNOWN_ADDR_IN : std_logic;
+ signal REGIO_TIMEOUT_OUT : std_logic;
+ signal REGIO_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
+ signal REGIO_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
+ signal REGIO_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
+ signal REGIO_IDRAM_WR_IN : std_logic;
+ signal REGIO_ONEWIRE_INOUT : std_logic;
+ signal REGIO_EXT_REG_DATA_IN : std_logic_vector(31 downto 0);
+ signal REGIO_EXT_REG_DATA_OUT : std_logic_vector(31 downto 0);
+ signal REGIO_EXT_REG_WRITE_IN : std_logic;
+ signal REGIO_EXT_REG_ADDR_IN : std_logic_vector(7 downto 0);
+
+ signal APL_DATA_IN : std_logic_vector(63 downto 0);
+ signal APL_PACKET_NUM_IN : std_logic_vector(11 downto 0);
+ signal APL_DATAREADY_IN : std_logic_vector(3 downto 0);
+ signal APL_READ_OUT : std_logic_vector(3 downto 0);
+ signal APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
+ signal APL_DTYPE_IN : std_logic_vector(15 downto 0);
+ signal APL_ERROR_PATTERN_IN : std_logic_vector(127 downto 0);
+ signal APL_SEND_IN : std_logic_vector(3 downto 0);
+ signal APL_TARGET_ADDRESS_IN : std_logic_vector(63 downto 0);
+ signal APL_DATA_OUT : std_logic_vector(63 downto 0);
+ signal APL_PACKET_NUM_OUT : std_logic_vector(11 downto 0);
+ signal APL_TYP_OUT : std_logic_vector(11 downto 0);
+ signal APL_DATAREADY_OUT : std_logic_vector(3 downto 0);
+ signal APL_READ_IN : std_logic_vector(3 downto 0);
+ signal APL_RUN_OUT : std_logic_vector(3 downto 0);
+ signal APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
+ signal APL_LENGTH_IN : std_logic_vector(4*16-1 downto 0);
+ signal APL_MY_ADDRESS_IN : std_logic_vector(15 downto 0);
+
+ signal MPLEX_CTRL : std_logic_vector(31 downto 0);
+
+begin
+ CLK <= not CLK after 5 ns;
+ RESET <= '0' after 50 ns;
+ CLK_EN <= '1';
+
+
+
+
+
+--Active Applications
+---------------------------
+
+ APL0 : trb_net16_dummy_apl
+ generic map(
+ TARGET_ADDRESS => x"FFFF",
+ PREFILL_LENGTH => 3,
+ TRANSFER_LENGTH => 3
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_IN(15 downto 0),
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN(2 downto 0),
+ APL_DATAREADY_OUT => APL_DATAREADY_IN(0),
+ APL_READ_IN => APL_READ_OUT(0),
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(0),
+ APL_DTYPE_OUT => APL_DTYPE_IN(3 downto 0),
+ APL_SEND_OUT => APL_SEND_IN(0),
+ APL_DATA_IN => APL_DATA_OUT(15 downto 0),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(2 downto 0),
+ APL_TYP_IN => APL_TYP_OUT(2 downto 0),
+ APL_DATAREADY_IN => APL_DATAREADY_OUT(0),
+ APL_READ_OUT => APL_READ_IN(0),
+ APL_RUN_IN => APL_RUN_OUT(0),
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN(31 downto 0),
+ APL_SEQNR_IN => APL_SEQNR_OUT(7 downto 0),
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN(15 downto 0)
+ );
+
+ APL1 : trb_net16_dummy_apl
+ generic map(
+ TARGET_ADDRESS => x"FFFF",
+ PREFILL_LENGTH => 3,
+ TRANSFER_LENGTH => 3
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_IN(31 downto 16),
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN(5 downto 3),
+ APL_DATAREADY_OUT => APL_DATAREADY_IN(1),
+ APL_READ_IN => APL_READ_OUT(1),
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(1),
+ APL_DTYPE_OUT => APL_DTYPE_IN(7 downto 4),
+ APL_SEND_OUT => APL_SEND_IN(1),
+ APL_DATA_IN => APL_DATA_OUT(31 downto 16),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(5 downto 3),
+ APL_TYP_IN => APL_TYP_OUT(5 downto 3),
+ APL_DATAREADY_IN => APL_DATAREADY_OUT(1),
+ APL_READ_OUT => APL_READ_IN(1),
+ APL_RUN_IN => APL_RUN_OUT(1),
+ APL_ERROR_PATTERN_OUT => open , --APL_ERROR_PATTERN_IN(63 downto 32),
+ APL_SEQNR_IN => APL_SEQNR_OUT(15 downto 8),
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN(31 downto 16)
+ );
+
+
+ APL_DATA_IN(47 downto 32) <= (others => '0');
+ APL_PACKET_NUM_IN(8 downto 6) <= (others => '0');
+ APL_DATAREADY_IN(2) <= '0';
+ APL_READ_IN(2) <= '0';
+ APL_DTYPE_IN(11 downto 8) <= (others => '0');
+
+ APL3 : trb_net16_dummy_apl
+ generic map(
+ TARGET_ADDRESS => x"FFFF",
+ PREFILL_LENGTH => 3,
+ TRANSFER_LENGTH => 3
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ APL_DATA_OUT => APL_DATA_IN(63 downto 48),
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_IN(11 downto 9),
+ APL_DATAREADY_OUT => APL_DATAREADY_IN(3),
+ APL_READ_IN => APL_READ_OUT(3),
+ APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_IN(3),
+ APL_DTYPE_OUT => APL_DTYPE_IN(15 downto 12),
+ APL_SEND_OUT => APL_SEND_IN(3),
+ APL_DATA_IN => APL_DATA_OUT(63 downto 48),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_OUT(11 downto 9),
+ APL_TYP_IN => APL_TYP_OUT(11 downto 9),
+ APL_DATAREADY_IN => APL_DATAREADY_OUT(3),
+ APL_READ_OUT => APL_READ_IN(3),
+ APL_RUN_IN => APL_RUN_OUT(3),
+ APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_IN(127 downto 96),
+ APL_SEQNR_IN => APL_SEQNR_OUT(31 downto 24),
+ APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_IN(63 downto 48)
+ );
+
+
+MED_CTRL_OP(14 downto 0) <= (others => '0');
+MED_CTRL_OP(15) <= MED_STAT_OP(15);
+MED_CTRL_OP(30 downto 16) <= (others => '0');
+MED_CTRL_OP(31) <= MED_STAT_OP(31);
+APL_MY_ADDRESS_IN <= x"F001"; --Sender address
+APL_LENGTH_IN <= (others => '0');
+
+--Sender
+-----------------------
+ THE_SENDER : trb_net16_endpoint_active_4_channel
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ -- Media direction port
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_STAT_OP_IN => MED_STAT_OP(15 downto 0),
+ MED_CTRL_OP_OUT => MED_CTRL_OP(15 downto 0),
+
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_DATAREADY_IN => APL_DATAREADY_IN,
+ APL_READ_OUT => APL_READ_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+ APL_LENGTH_IN => APL_LENGTH_IN,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+
+ -- Status and control port
+ STAT_DEBUG => open,
+ MPLEX_CTRL => MPLEX_CTRL,
+ CTRL_GEN => (others => '0')
+ );
+
+
+
+
+--Receiver
+-----------------------
+
+ THE_RECEIVER : trb_net16_endpoint_hades_full
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_IN,
+ MED_DATA_OUT => MED_DATA_IN,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN,
+ MED_READ_IN => MED_READ_OUT,
+
+ MED_DATAREADY_IN => MED_DATAREADY_OUT,
+ MED_DATA_IN => MED_DATA_OUT,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT,
+ MED_READ_OUT => MED_READ_IN,
+
+ MED_STAT_OP_IN => MED_STAT_OP(31 downto 16),
+ MED_CTRL_OP_OUT => MED_CTRL_OP(31 downto 16),
+
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT,
+ LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+
+ --Data Port
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+
+ -- Slow Control Data Port
+ REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN,
+ REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT,
+ REGIO_REGISTERS_IN => REGIO_REGISTERS_IN,
+ REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT,
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => REGIO_IDRAM_DATA_IN,
+ REGIO_IDRAM_DATA_OUT => REGIO_IDRAM_DATA_OUT,
+ REGIO_IDRAM_ADDR_IN => REGIO_IDRAM_ADDR_IN,
+ REGIO_IDRAM_WR_IN => REGIO_IDRAM_WR_IN,
+ REGIO_ONEWIRE_INOUT => REGIO_ONEWIRE_INOUT,
+ --Additional r/w access to ctrl registers
+ REGIO_EXT_REG_DATA_IN => REGIO_EXT_REG_DATA_IN,
+ REGIO_EXT_REG_DATA_OUT => REGIO_EXT_REG_DATA_OUT,
+ REGIO_EXT_REG_WRITE_IN => REGIO_EXT_REG_WRITE_IN,
+ REGIO_EXT_REG_ADDR_IN => REGIO_EXT_REG_ADDR_IN,
+
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => open,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => MPLEX_CTRL,
+ IOBUF_CTRL_GEN => (others => '0'),
+ STAT_ONEWIRE => open
+ );
+
+MPLEX_CTRL <= x"00000000";
+
+LVL1_TRG_RELEASE_IN <= '1';
+LVL1_ERROR_PATTERN_IN <= (others => '0');
+IPU_ERROR_PATTERN_IN <= (others => '0');
+APL_ERROR_PATTERN_IN(95 downto 64) <= (others => '0');
+
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ipu_answer_delay <= (others => '0');
+ elsif (ipu_answer_delay(10) = '0' or IPU_START_READOUT_OUT = '0') and not (ipu_answer_delay(3) = '1' and IPU_READ_OUT = '0') then
+ ipu_answer_delay <= ipu_answer_delay(10 downto 0) & (IPU_START_READOUT_OUT and not or_all(ipu_answer_delay));
+ end if;
+ end if;
+ end process;
+ IPU_DATAREADY_IN <= ipu_answer_delay(3);
+ IPU_READOUT_FINISHED_IN <= ipu_answer_delay(9);
+ IPU_LENGTH_IN <= x"0001";
+ IPU_ERROR_PATTERN_IN <= (others => '0');
+ APL_ERROR_PATTERN_IN(63 downto 32) <= x"10EF1234";
+ IPU_DATA_IN <= x"DA1A5E10";
+
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- this is a dummy apl, just sending data into an active api
+
+--THIS IS NOT WORKING correctly!!!!
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity trb_net16_dummy_apl is
+ generic (
+ TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"F001";
+ PREFILL_LENGTH : integer := 1;
+ TRANSFER_LENGTH : integer := 1 -- length of dummy data
+ -- might not work with transfer_length > api_fifo
+ -- because of incorrect handling of fifo_full_in!
+
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
+ APL_SHORT_TRANSFER_OUT: out std_logic;
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
+ APL_SEND_OUT: out std_logic;
+ APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0);
+ -- Receiver port
+ APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN:in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_TYP_IN: in std_logic_vector (2 downto 0);
+ APL_DATAREADY_IN: in std_logic;
+ APL_READ_OUT: out std_logic;
+ -- APL Control port
+ APL_RUN_IN: in std_logic;
+ APL_SEQNR_IN: in std_logic_vector (7 downto 0)
+ );
+end entity;
+
+architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is
+
+ type SENDER_STATE is (IDLE, WRITING, WAITING);
+ signal current_state, next_state : SENDER_STATE;
+ signal next_counter, reg_counter : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic;
+ signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic;
+ signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal address, reghigh, reglow : std_logic_vector(15 downto 0);
+ signal state_bits : std_logic_vector(2 downto 0);
+ signal reg_F0, reg_F1, reg_F2, reg_F3 : std_logic_vector(15 downto 0);
+begin
+
+-- address <= x"0008";
+-- reghigh <= x"DEAD";
+-- reglow <= x"AFFE";
+ reg_F0 <= x"8023"; --x"0001";
+
+ reg_F1 <= x"8000";
+ reg_F2 <= x"0000";--xor_all(APL_DATA_IN) & "000000000000011";
+ reg_F3 <= x"0000";
+ APL_DTYPE_OUT <= x"9";
+ APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
+
+ process(current_state)
+ begin
+ case current_state is
+ when IDLE => state_bits <= "000";
+ when WRITING => state_bits <= "001";
+ when WAITING => state_bits <= "011";
+ when others => state_bits <= "111";
+ end case;
+ end process;
+
+ APL_READ_OUT <= '1'; --just read, do not check
+ APL_ERROR_PATTERN_OUT <= x"12345678";
+ --APL_DATA_OUT <= reg_counter;
+
+ CHECK_1:if TRANSFER_LENGTH >0 generate
+ APL_SHORT_TRANSFER_OUT <= '0';
+ APL_SEND_OUT <= buf_APL_SEND_OUT;
+ end generate;
+ CHECK_2:if TRANSFER_LENGTH =0 generate
+ APL_SHORT_TRANSFER_OUT <= '1';
+ APL_SEND_OUT <= '1' when APL_RUN_IN = '0' else '0';
+ end generate;
+
+
+ SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT)
+ begin -- process
+ next_APL_SEND_OUT <= buf_APL_SEND_OUT;
+ next_state <= IDLE;
+ next_counter <= reg_counter;
+ next_APL_WRITE_OUT <= '0';
+ next_APL_DATA_OUT <= (others => '0');
+ next_packet_counter <= packet_counter;
+-------------------------------------------------------------------------
+-- IDLE
+-------------------------------------------------------------------------
+ if current_state = IDLE then
+ if reg_counter = TRANSFER_LENGTH then
+ next_state <= WAITING;
+ elsif APL_READ_IN = '0' then
+ next_state <= IDLE;
+ else
+ next_state <= WRITING;
+ next_APL_DATA_OUT <= reg_F0;
+ next_APL_WRITE_OUT <= '1';
+ next_packet_counter <= c_F0;
+ next_APL_SEND_OUT <= '1';
+ end if;
+-------------------------------------------------------------------------
+-- WRITING
+-------------------------------------------------------------------------
+ elsif current_state = WRITING then
+ next_APL_SEND_OUT <= '1';
+ next_state <= WRITING;
+ if packet_counter = c_F0 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= reg_F1;
+ next_packet_counter <= c_F1;
+ elsif packet_counter = c_F1 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= reg_F2;
+ next_packet_counter <= c_F2;
+ elsif packet_counter = c_F2 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= reg_F3;
+ next_packet_counter <= c_F3;
+ elsif packet_counter = c_F3 then
+ next_state <= IDLE;
+ next_counter <= reg_counter +1;
+ end if;
+-----------------------------------------------------------------------
+-- WAITING
+-----------------------------------------------------------------------
+ elsif current_state = WAITING then
+ next_APL_SEND_OUT <= '0';
+ if APL_RUN_IN = '1' or buf_APL_SEND_OUT = '1' then
+ next_state <= WAITING;
+ else
+ next_state <= IDLE;
+ next_counter <= (others => '0');
+ end if;
+ end if; -- end state switch
+
+ end process;
+
+APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
+APL_PACKET_NUM_OUT <= packet_counter;
+APL_DATAREADY_OUT <= buf_APL_WRITE_OUT;
+
+
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= IDLE;
+ reg_counter <= (others => '0');
+ buf_APL_DATA_OUT <= (others => '0');
+ buf_APL_WRITE_OUT <= '0';
+ buf_APL_SEND_OUT <= '0';
+ elsif CLK_EN = '1' then
+ reg_counter <= next_counter;
+ current_state <= next_state;
+ packet_counter <= next_packet_counter;
+ buf_APL_DATA_OUT <= next_APL_DATA_OUT;
+ buf_APL_WRITE_OUT <= next_APL_WRITE_OUT;
+ buf_APL_SEND_OUT <= next_APL_SEND_OUT;
+ end if;
+ end if;
+ end process;
+
+end architecture;
--- /dev/null
+-- this is a dummy apl, just sending data into an active api
+
+-- THIS IS NOT WORKING correctly !!!!
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_dummy_passive_apl is
+ generic (
+ TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"ffff";
+ PREFILL_LENGTH : integer := 3;
+ TRANSFER_LENGTH : integer := 3 -- length of dummy data
+ -- might not work with transfer_length > api_fifo
+ -- because of incorrect handling of fifo_full_in!
+ -- shorttransfer is not working too
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
+ APL_SHORT_TRANSFER_OUT: out std_logic;
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0);
+ APL_SEND_OUT: out std_logic;
+ APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0);
+ -- Receiver port
+ APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN:in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_TYP_IN: in std_logic_vector (2 downto 0);
+ APL_DATAREADY_IN: in std_logic;
+ APL_READ_OUT: out std_logic;
+ -- APL Control port
+ APL_RUN_IN: in std_logic;
+ APL_SEQNR_IN: in std_logic_vector (7 downto 0);
+ STAT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_dummy_passive_apl_arch of trb_net16_dummy_passive_apl is
+
+ type SENDER_STATE is (IDLE, WRITING, RUNNING, WAITING, MY_ERROR);
+ signal current_state, next_state : SENDER_STATE;
+ signal next_counter, reg_counter : std_logic_vector(15 downto 0);
+ signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic;
+ signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic;
+ signal next_packet_counter, packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal state_bits : std_logic_vector(2 downto 0);
+ signal current_TYPE_IN, saved_PACKET_TYPE_IN : std_logic_vector(2 downto 0);
+
+begin
+ APL_READ_OUT <= '1'; --just read, do not check
+ APL_DTYPE_OUT <= x"0";
+ APL_ERROR_PATTERN_OUT <= x"12345678";
+ APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
+ --APL_DATA_OUT <= reg_counter;
+
+ CHECK_1:if TRANSFER_LENGTH >0 generate
+ APL_SHORT_TRANSFER_OUT <= '0';
+ end generate;
+ CHECK_2:if TRANSFER_LENGTH =0 generate
+ APL_SHORT_TRANSFER_OUT <= '1';
+ end generate;
+
+ process(current_state)
+ begin
+ case current_state is
+ when IDLE => state_bits <= "000";
+ when WRITING => state_bits <= "001";
+ when RUNNING => state_bits <= "010";
+ when WAITING => state_bits <= "011";
+ when MY_ERROR => state_bits <= "100";
+ when others => state_bits <= "111";
+ end case;
+ end process;
+
+ STAT(2 downto 0) <= state_bits;
+ STAT(8) <= '1' when current_TYPE_IN = TYPE_TRM else '0';
+
+ --this holds the current packet type from fifo_to_apl
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_PACKET_TYPE_IN <= TYPE_ILLEGAL;
+ elsif APL_PACKET_NUM_IN = c_H0 then
+ saved_PACKET_TYPE_IN <= APL_TYP_IN;
+ end if;
+ end if;
+ end process;
+ --create comb. real packet type
+ current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = c_H0 and RESET = '0')
+ else saved_PACKET_TYPE_IN;
+
+ SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN,
+ packet_counter, buf_APL_SEND_OUT, current_TYPE_IN, APL_DATAREADY_IN, APL_PACKET_NUM_IN)
+ begin -- process
+ next_APL_SEND_OUT <= buf_APL_SEND_OUT;
+ next_state <= MY_ERROR;
+ next_counter <= reg_counter;
+ next_APL_PACKET_NUM_OUT <= packet_counter;
+ next_APL_WRITE_OUT <= '0';
+ next_APL_DATA_OUT <= (others => '0');
+ next_packet_counter <= packet_counter;
+-------------------------------------------------------------------------
+-- IDLE
+-------------------------------------------------------------------------
+ if current_state = IDLE then
+ if APL_READ_IN = '0' or reg_counter = PREFILL_LENGTH then
+ next_state <= RUNNING;
+ next_APL_SEND_OUT <= '0';
+ else
+ next_APL_SEND_OUT <= '1';
+ next_state <= WRITING;
+ next_APL_DATA_OUT <= (1 => '1', others => '0');
+ next_APL_WRITE_OUT <= '1';
+ next_packet_counter <= c_F0;
+ end if;
+-------------------------------------------------------------------------
+-- WRITING
+-------------------------------------------------------------------------
+ elsif current_state = WRITING then
+ next_state <= WRITING;
+ if packet_counter = c_F0 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= (0 => '1', others => '0');
+ next_packet_counter <= c_F1;
+ elsif packet_counter = c_F1 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= xor_all(APL_DATA_IN) & reg_counter(14 downto 0);
+ next_packet_counter <= c_F2;
+ elsif packet_counter = c_F2 then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_DATA_OUT <= xor_all(APL_DATA_IN) & reg_counter(14 downto 0);
+ next_packet_counter <= c_F3;
+ elsif packet_counter <=c_F3 then
+ next_state <= IDLE;
+ next_packet_counter <= c_F0;
+ next_counter <= reg_counter +1;
+ end if;
+-----------------------------------------------------------------------
+-- RUNNING
+-----------------------------------------------------------------------
+ elsif current_state = RUNNING then
+ next_APL_SEND_OUT <= '0';
+ if reg_counter = TRANSFER_LENGTH then
+ next_state <= WAITING;
+ else
+ next_state <= RUNNING;
+ if APL_READ_IN = '1' then
+ next_counter <= reg_counter +1;
+ end if;
+ end if;
+-----------------------------------------------------------------------
+-- WAITING
+-----------------------------------------------------------------------
+ elsif current_state = WAITING then
+ if (APL_TYP_IN = TYPE_TRM and APL_PACKET_NUM_IN = c_F3 and APL_DATAREADY_IN = '1') then
+ next_state <= IDLE;
+ next_counter <= (others => '0');
+ else
+ next_state <= WAITING;
+ end if;
+ end if; -- end state switch
+ if RESET = '1' then
+ next_APL_WRITE_OUT <= '0';
+ end if;
+ end process;
+
+APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
+APL_PACKET_NUM_OUT <= packet_counter;
+APL_DATAREADY_OUT <= buf_APL_WRITE_OUT;
+APL_SEND_OUT <= buf_APL_SEND_OUT;
+
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= WAITING;
+ reg_counter <= (others => '0');
+ buf_APL_DATA_OUT <= (others => '0');
+ buf_APL_WRITE_OUT <= '0';
+ buf_APL_SEND_OUT <= '0';
+ elsif CLK_EN = '1' then
+ reg_counter <= next_counter;
+ current_state <= next_state;
+ packet_counter <= next_packet_counter;
+ buf_APL_DATA_OUT <= next_APL_DATA_OUT;
+ buf_APL_WRITE_OUT <= next_APL_WRITE_OUT;
+ buf_APL_SEND_OUT <= next_APL_SEND_OUT;
+ end if;
+ end if;
+ end process;
+
+end architecture;
+++ /dev/null
--- 3 active apis plus one slow control interface
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
---Entity decalaration for clock generator
-entity trb_net16_endpoint_0_trg_3_api_1_regio is
- generic (
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE);
- IBUF_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6);
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
- SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
- --no data / address out?
- SCTR_USE_DATA_PORT : std_logic := '0';
- SCTR_USE_1WIRE_INTERFACE : integer := c_YES;
- SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F007";
- SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-
-
-
- -- IPU-Data Channel APL
- LVL1_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL1_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL1_APL_DATAREADY_IN: in std_logic;
- LVL1_APL_READ_OUT: out std_logic;
- LVL1_APL_SHORT_TRANSFER_IN: in std_logic;
- LVL1_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
- LVL1_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0);
- LVL1_APL_SEND_IN: in std_logic;
- LVL1_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0);
- LVL1_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL1_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL1_APL_TYP_OUT: out std_logic_vector (2 downto 0);
- LVL1_APL_DATAREADY_OUT: out std_logic;
- LVL1_APL_READ_IN: in std_logic;
- LVL1_APL_RUN_OUT: out std_logic;
- LVL1_APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- IPU-Data Channel APL
- LVL2_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_DATAREADY_IN: in std_logic;
- LVL2_APL_READ_OUT: out std_logic;
- LVL2_APL_SHORT_TRANSFER_IN: in std_logic;
- LVL2_APL_DTYPE_IN: in std_logic_vector (3 downto 0);
- LVL2_APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0);
- LVL2_APL_SEND_IN: in std_logic;
- LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0);
- LVL2_APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_TYP_OUT: out std_logic_vector (2 downto 0);
- LVL2_APL_DATAREADY_OUT: out std_logic;
- LVL2_APL_READ_IN: in std_logic;
- LVL2_APL_RUN_OUT: out std_logic;
- LVL2_APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Slow Control Data Port
- SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
- SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0);
- SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- SCTR_READ_ENABLE_OUT : out std_logic;
- SCTR_WRITE_ENABLE_OUT : out std_logic;
- SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0);
- SCTR_DATA_IN : in std_logic_vector(32-1 downto 0);
- SCTR_DATAREADY_IN : in std_logic;
- SCTR_NO_MORE_DATA_IN : in std_logic;
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- SCTR_IDRAM_WR_IN : in std_logic;
- SCTR_ONEWIRE_INOUT : inout std_logic;
-
- -- Status
- STAT_GEN_1: out std_logic_vector (31 downto 0); -- General Status
- STAT_GEN_2: out std_logic_vector (31 downto 0) -- General Status
- );
-end entity;
-
-architecture trb_net16_endpoint_0_trg_2_api_1_regio_arch of trb_net16_endpoint_0_trg_2_api_1_regio is
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_regIO is
- generic (
- REGISTER_WIDTH : integer range 32 to 32 := 32;
- ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
- --no data / address out?
- NO_DAT_PORT : std_logic := '0';
-
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
- --Port to write Unique ID
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when no internal register is accessed
- DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
- DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
-
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
-
-
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
- FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_MASTER_DATAREADY_OUT: out std_logic;
- INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN: in std_logic;
-
- INT_MASTER_DATAREADY_IN: in std_logic;
- INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT: out std_logic;
-
-
- INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the SLAVE path)
- INT_SLAVE_DATAREADY_OUT: out std_logic;
- INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN: in std_logic;
-
- INT_SLAVE_DATAREADY_IN: in std_logic;
- INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 0;
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
-
-signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
-
--- for the connection to the multiplexer
-signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);
-signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);
-
-signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);
-signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_IN : std_logic_vector(7 downto 0);
-
-signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0);
-signal buf_APL_READ_OUT : std_logic_vector(3 downto 0);
-signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
-signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
-signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
-signal buf_APL_SEND_IN : std_logic_vector(3 downto 0);
-signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(4*16-1 downto 0);
-signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0);
-signal buf_APL_READ_IN : std_logic_vector(3 downto 0);
-signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
-signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0);
-signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
-
-signal MY_ADDRESS : std_logic_vector(15 downto 0);
-
-signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
-signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal MPLEX_CTRL : std_logic_vector(31 downto 0);
-signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0);
-
-signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-
-signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
-signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
-signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
-signal buf_IDRAM_WR_IN : std_logic;
-
-begin
-
- MED_CTRL_OP(15) <= MED_STAT_OP(15);
- MED_CTRL_OP(14 downto 0) <= (others => '0');
-
- --Connections for data channel
- genbuffers : for i in 0 to 3 generate
- geniobuf: if USE_CHANNEL(i) = c_YES generate
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => IBUF_DEPTH(i),
- IBUF_SECURE_MODE => IBUF_SECURE_MODE(i),
- SBUF_VERSION => 0,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),
- USE_VENDOR_CORES => c_YES,
- USE_CHECKSUM => cfg_USE_CHECKSUM(i),
- INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i),
- REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i)
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
-
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN,
-
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
-
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
-
- -- Status and control port
- STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),
- STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
- CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
- STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32)
- );
- genactapi : if API_TYPE(i) = c_API_ACTIVE generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i),
- APL_READ_OUT => buf_APL_READ_OUT(i),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
- APL_SEND_IN => buf_APL_SEND_IN(i),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i),
- APL_READ_IN => buf_APL_READ_IN(i),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(i),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- genpasapi : if API_TYPE(i) = c_API_PASSIVE generate
- constant j : integer := i;
- begin
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j),
- APL_READ_OUT => buf_APL_READ_OUT(j),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
- APL_SEND_IN => buf_APL_SEND_IN(j),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
- APL_READ_IN => buf_APL_READ_IN(j),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(j),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- end generate;
- gentermbuf: if USE_CHANNEL(i) = c_NO generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
-
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)
- );
- end generate;
- end generate;
-
-
- buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= LVL1_APL_DATA_IN;
- buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH) <= LVL2_APL_DATA_IN;
- buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= LVL1_APL_PACKET_NUM_IN;
- buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN;
- buf_APL_DATAREADY_IN(0) <= LVL1_APL_DATAREADY_IN;
- buf_APL_DATAREADY_IN(2) <= LVL2_APL_DATAREADY_IN;
- LVL1_APL_READ_OUT <= buf_APL_READ_OUT(0);
- LVL2_APL_READ_OUT <= buf_APL_READ_OUT(2);
- buf_APL_SHORT_TRANSFER_IN(0) <= LVL1_APL_SHORT_TRANSFER_IN;
- buf_APL_SHORT_TRANSFER_IN(2) <= LVL2_APL_SHORT_TRANSFER_IN;
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= LVL1_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(3*4-1 downto 2*4) <= LVL2_APL_DTYPE_IN;
- buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= LVL1_APL_ERROR_PATTERN_IN;
- buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32) <= LVL2_APL_ERROR_PATTERN_IN;
- buf_APL_SEND_IN(0) <= LVL1_APL_SEND_IN;
- buf_APL_SEND_IN(2) <= LVL2_APL_SEND_IN;
- buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= LVL1_APL_TARGET_ADDRESS_IN;
- buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16) <= LVL2_APL_TARGET_ADDRESS_IN;
-
- LVL1_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH);
- LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH);
- LVL1_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH);
- LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH);
- LVL1_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0);
- LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(2);
- buf_APL_READ_IN(0) <= LVL1_APL_READ_IN;
- buf_APL_READ_IN(2) <= LVL2_APL_READ_IN;
-
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= LVL1_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(3*4-1 downto 2*4) <= LVL2_APL_DTYPE_IN;
- LVL1_APL_RUN_OUT <= buf_APL_RUN_OUT(0);
- LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(2);
- LVL1_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8);
- LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(3*8-1 downto 2*8);
-
- regIO : trb_net16_regIO
- generic map(
- REGISTER_WIDTH => 32,
- ADDRESS_WIDTH => 16,
- NUM_STAT_REGS => SCTR_NUM_STAT_REGS,
- NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS,
- --standard values for output registers
- INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS,
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS => SCTR_USED_CTRL_REGS,
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK,
- --no data / address out?
- NO_DAT_PORT => SCTR_USE_DATA_PORT,
- INIT_ADDRESS => SCTR_INIT_ADDRESS,
- INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID,
- COMPILE_TIME => SCTR_COMPILE_TIME,
- COMPILE_VERSION => SCTR_COMPILE_VERSION,
- HARDWARE_VERSION => SCTR_HARDWARE_VERSION
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Port to API
- API_DATA_OUT => buf_APL_DATA_IN(4*c_DATA_WIDTH-1 downto 3*c_DATA_WIDTH),
- API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(4*c_NUM_WIDTH-1 downto 3*c_NUM_WIDTH),
- API_DATAREADY_OUT => buf_APL_DATAREADY_IN(3),
- API_READ_IN => buf_APL_READ_OUT(3),
- API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(3),
- API_DTYPE_OUT => buf_APL_DTYPE_IN(4*4-1 downto 3*4),
- API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(4*32-1 downto 3*32),
- API_SEND_OUT => buf_APL_SEND_IN(3),
- API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(4*16-1 downto 3*16),
- API_DATA_IN => buf_APL_DATA_OUT(4*c_DATA_WIDTH-1 downto 3*c_DATA_WIDTH),
- API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(4*c_NUM_WIDTH-1 downto 3*c_NUM_WIDTH),
- API_TYP_IN => buf_APL_TYP_OUT(4*3-1 downto 3*3),
- API_DATAREADY_IN => buf_APL_DATAREADY_OUT(3),
- API_READ_OUT => buf_APL_READ_IN(3),
- API_RUN_IN => buf_APL_RUN_OUT(3),
- API_SEQNR_IN => buf_APL_SEQNR_OUT(4*8-1 downto 3*8),
- --Port to write Unique ID
- IDRAM_DATA_IN => buf_IDRAM_DATA_IN,
- IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT,
- IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
- IDRAM_WR_IN => buf_IDRAM_WR_IN,
- MY_ADDRESS_OUT => MY_ADDRESS,
- --Common Register in / out
- COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
- COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT,
- --Custom Register in / out
- REGISTERS_IN => SCTR_REGISTERS_IN,
- REGISTERS_OUT => SCTR_REGISTERS_OUT,
- --following ports only used when no internal register is accessed
- DAT_ADDR_OUT => SCTR_ADDR_OUT,
- DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT,
- DAT_DATA_OUT => SCTR_DATA_OUT,
- DAT_DATA_IN => SCTR_DATA_IN,
- DAT_DATAREADY_IN => SCTR_DATAREADY_IN,
- DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN,
- STAT => SCTR_REGIO_STAT
- );
-
- gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate
- buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN;
- buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN;
- buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN;
- SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
- SCTR_ONEWIRE_INOUT <= '0';
- buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN;
- end generate;
- gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate
- buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0);
- buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32);
-
- onewire_interface : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => 1,
- CLK_PERIOD => 10
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- --connection to 1-wire interface
- ONEWIRE => SCTR_ONEWIRE_INOUT,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => buf_IDRAM_DATA_IN,
- ADDR_OUT => buf_IDRAM_ADDR_IN,
- WRITE_OUT=> buf_IDRAM_WR_IN,
- TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
- STAT => open
- );
- end generate;
-
-
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,
- INT_DATA_OUT => MED_IO_DATA_IN,
- INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
- INT_READ_IN => MED_IO_READ_OUT,
- INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,
- INT_DATA_IN => MED_IO_DATA_OUT,
- INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,
- INT_READ_OUT => MED_IO_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
-end architecture;
-
+++ /dev/null
--- a trigger receiver - as simple as possible
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net16_endpoint_1_trg_0_api is
-
- generic (
- TRG_CHANNEL : integer := 0;
- TRG_SECURE_MODE : integer := 0 -- if 0, error pattern and dtype must be valid until next
- -- trigger comes in. if 1 these can be valid on falling edge of hold_trm only
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
-
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-
- --Trigger Output
- TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
- TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
- TRG_CODE_OUT : out std_logic_vector (7 downto 0);
- TRG_INFORMATION_OUT : out std_logic_vector (15 downto 0);
- TRG_RECEIVED_OUT : out std_logic;
- TRG_RELEASE_IN : in std_logic;
- TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
-
- -- Status and control port => just coming from the iobuf for debugging
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_LOCKED: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- STAT_api_control_signals: out std_logic_vector(31 downto 0);
- STAT_MPLEX: out std_logic_vector(31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0);
- MPLEX_CTRL: in std_logic_vector (31 downto 0);
- API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_endpoint_1_trg_0_api_arch of trb_net16_endpoint_1_trg_0_api is
-
-component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := 0;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
-
-
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
- );
-end component;
- component trb_net16_io_multiplexer is
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
-end component;
-component trb_net16_trigger is
- generic (
- USE_TRG_PORT : integer range 0 to 1 := c_YES;
- --even when NO, ERROR_PACKET_IN is used for automatic replys
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high only
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- Trigger information output
- TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
- TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
- TRG_CODE_OUT : out std_logic_vector (7 downto 0);
- TRG_INFORMATION_OUT : out std_logic_vector (15 downto 0);
- TRG_RECEIVED_OUT : out std_logic;
- TRG_RELEASE_IN : in std_logic;
- TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
- );
- end component;
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
- );
- end component;
-
- signal apl_to_buf_INIT_DATAREADY: std_logic;
- signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
- signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
- signal apl_to_buf_INIT_READ : std_logic;
-
- signal buf_to_apl_INIT_DATAREADY: std_logic;
- signal buf_to_apl_INIT_DATA : std_logic_vector (15 downto 0);
- signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (1 downto 0);
- signal buf_to_apl_INIT_READ : std_logic;
-
- signal apl_to_buf_REPLY_DATAREADY: std_logic;
- signal apl_to_buf_REPLY_DATA : std_logic_vector (15 downto 0);
- signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
- signal apl_to_buf_REPLY_READ : std_logic;
-
- signal buf_to_apl_REPLY_DATAREADY: std_logic;
- signal buf_to_apl_REPLY_DATA : std_logic_vector (15 downto 0);
- signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (1 downto 0);
- signal buf_to_apl_REPLY_READ : std_logic;
-
- -- for the connection to the multiplexer
- signal MED_INIT_DATAREADY_OUT : std_logic;
- signal MED_INIT_DATA_OUT : std_logic_vector (15 downto 0);
- signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
- signal MED_INIT_READ_IN : std_logic;
-
- signal MED_IBUF_DATAREADY_IN : std_logic;
- signal MED_IBUF_DATA_IN : std_logic_vector (15 downto 0);
- signal MED_IBUF_PACKET_NUM_IN : std_logic_vector (1 downto 0);
- signal MED_IBUF_READ_OUT : std_logic;
-
- signal MED_REPLY_DATAREADY_OUT : std_logic;
- signal MED_REPLY_DATA_OUT : std_logic_vector (15 downto 0);
- signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
- signal MED_REPLY_READ_IN : std_logic;
-
- signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
- signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
-
- signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
- signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
- signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
-
-begin
--------------------------------------------------
---Connection between multiplexer and iobuf
--------------------------------------------------
- --Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- gentrg: if i = TRG_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2) <= MED_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH) <= MED_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2) <= MED_REPLY_PACKET_NUM_OUT;
- MED_INIT_READ_IN <= m_READ_IN(i*2);
- MED_REPLY_READ_IN <= m_READ_IN(i+1);
- MED_IBUF_DATAREADY_IN <= m_DATAREADY_IN(i);
- MED_IBUF_DATA_IN <= m_DATA_IN(c_DATA_WIDTH-1 downto 0);
- MED_IBUF_PACKET_NUM_IN <= m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0);
- m_READ_OUT(i) <= MED_IBUF_READ_OUT;
- end generate;
- genelse: if i /= TRG_CHANNEL generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN(c_DATA_WIDTH-1 downto 0),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
- MED_READ_OUT => m_READ_OUT(i),
-
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+1 downto i*c_NUM_WIDTH*2),
- MED_INIT_READ_IN => m_READ_IN(i*2),
-
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*c_NUM_WIDTH*2+3 downto i*c_NUM_WIDTH*2+2),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1)
- );
- end generate;
- end generate;
-
-IOBUF: trb_net16_iobuf
- generic map(
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(TRG_CHANNEL),
- USE_CHECKSUM => cfg_USE_CHECKSUM(TRG_CHANNEL)
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_INIT_READ_IN,
- MED_DATAREADY_IN => MED_IBUF_DATAREADY_IN,
- MED_DATA_IN => MED_IBUF_DATA_IN,
- MED_PACKET_NUM_IN => MED_IBUF_PACKET_NUM_IN,
- MED_READ_OUT => MED_IBUF_READ_OUT,
- MED_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_REPLY_READ_IN,
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ,
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_GEN,
- STAT_IBUF_BUFFER => STAT_IBUF_BUFFER,
- CTRL_GEN => CTRL_GEN,
- STAT_CTRL_IBUF_BUFFER => STAT_CTRL_IBUF_BUFFER
- );
-
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => RESET ,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
- trglvl1 : trb_net16_trigger
- generic map(
- USE_APL_PORT => c_YES,
- SECURE_MODE => std_TERM_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_REPLY_DATA,
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_REPLY_READ,
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_INIT_DATA,
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_INIT_READ,
-
- -- "mini" APL, just to see the triggers coming in
- TRG_TYPE_OUT => TRG_TYPE_OUT,
- TRG_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
- TRG_NUMBER_OUT => TRG_NUMBER_OUT,
- TRG_CODE_OUT => TRG_CODE_OUT,
- TRG_INFORMATION_OUT => TRG_INFORMATION_OUT,
- TRG_RECEIVED_OUT => TRG_RECEIVED_OUT,
- TRG_RELEASE_IN => TRG_RELEASE_IN,
- TRG_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
- );
-
-apl_to_buf_INIT_DATAREADY <= '0';
-apl_to_buf_INIT_DATA <= (others => '0');
-apl_to_buf_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_REPLY_READ <= '1';
-
-
-end architecture;
\ No newline at end of file
+++ /dev/null
-
--- NOT UP TO DATE
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--- this is an trigger receiver combined with a passive api
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
---Entity decalaration for clock generator
-entity trb_net16_endpoint_1_trg_1_api is
-
- generic (
- --api type for data channel
- API_TYPE : integer range 0 to 1 := 0;
- --Fifo for data channel
- DAT_INIT_DEPTH : integer range 0 to 7 := 2;
- DAT_REPLY_DEPTH : integer range 0 to 7 := 0; --passive api doesn't need a fifo here
- DAT_FIFO_TO_INT_DEPTH : integer range 0 to 7 := 1;
- DAT_FIFO_TO_APL_DEPTH : integer range 0 to 7 := 1;
- --SBUF_DATA_VERSION : integer range 0 to 1 := 0;
- --Fifo for TRG channel
- TRG_INIT_DEPTH : integer range 0 to 7 := 0;
- TRG_REPLY_DEPTH : integer range 0 to 7 := 0;
- TRG_SECURE_MODE : integer range 0 to 1 := 0;
- --SBUF_TRG_VERSION : integer range 0 to 1 := 0;
- --Multiplexer
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0;
- TRG_CHANNEL : integer range 0 to 3 := 0; --range 0 to 2**(MUX_WIDTH-1)
- DAT_CHANNEL : integer range 0 to 3 := 2; --range 0 to 2**(MUX_WIDTH-1)
- --General
- DATA_WIDTH : integer range 16 to 16 := 16;
- NUM_WIDTH : integer range 2 to 2 := 2
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_READ_IN: in std_logic; -- Media is reading
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- APL Transceiver port
- APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- APL_WRITE_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_TARGET_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- -- TRG Receiver port
- TRG_GOT_TRIGGER_OUT : out std_logic;
- TRG_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- TRG_DTYPE_OUT : out std_logic_vector(3 downto 0);
- TRG_SEQNR_OUT : out std_logic_vector(7 downto 0);
- TRG_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- TRG_RELEASE_IN : in std_logic;
-
- -- Status and control port => for debugging
- STAT_DAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_DAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_DAT_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_DAT_GEN: in std_logic_vector (31 downto 0);
- CTRL_DAT_LOCKED: in std_logic_vector (31 downto 0);
- STAT_DAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_DAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_TRG_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- STAT_TRG_api_control_signals: out std_logic_vector(31 downto 0);
- CTRL_TRG_GEN: in std_logic_vector (31 downto 0);
- CTRL_TRG_LOCKED: in std_logic_vector (31 downto 0);
- STAT_TRG_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_TRG_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0);
- STAT_MPLEX: out std_logic_vector(31 downto 0);
- MPLEX_CTRL: in std_logic_vector (31 downto 0);
- DAT_API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- DAT_API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
-end entity;
-
-architecture trb_net16_endpoint_1_trg_1_api_arch of trb_net16_endpoint_1_trg_1_api_endpoint is
-
- component trb_net16_iobuf is
-
- generic (
- INIT_DEPTH : integer := 1;
- REPLY_DEPTH : integer := 1
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic; -- Media is reading
-
- MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
- --by the media (via the TrbNetIOMultiplexer)
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic; -- Media is reading
-
- MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
- -- (the IOBUF MUST read)
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
- MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the reply path)
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
- STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
- STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN: in std_logic_vector (31 downto 0);
- CTRL_LOCKED: in std_logic_vector (31 downto 0);
- STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
- STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (API_TYPE : integer := API_TYPE; -- type of api: 0 passive, 1 active
- --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
- FIFO_TO_INT_DEPTH : integer := 1; -- direction to medium
- FIFO_TO_APL_DEPTH : integer := 1); -- direction to application
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- APL Transmitter port
- APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
- APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN : in std_logic; --
- APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN : in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
- -- Receiver port
- APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
- APL_READ_IN : in std_logic; -- Read data word
- -- APL Control port
- APL_RUN_OUT : out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
- -- Internal direction port
- -- the ports with master or slave in their name are to be mapped by the active api
- -- to the init respectivly the reply path and vice versa in the passive api.
- -- lets define: the "master" path is the path that I send data on.
- INT_MASTER_DATAREADY_OUT : out std_logic;
- INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_MASTER_READ_IN : in std_logic;
- INT_MASTER_DATAREADY_IN : in std_logic;
- INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_MASTER_READ_OUT : out std_logic;
- INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last HDR
- INT_SLAVE_DATAREADY_OUT : out std_logic;
- INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
- INT_SLAVE_READ_IN : in std_logic;
- INT_SLAVE_DATAREADY_IN : in std_logic;
- INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
- INT_SLAVE_READ_OUT : out std_logic;
- -- Status and control port
- STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 1;
- SECURE_MODE : integer range 0 to 1 := 0
- --if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these must be available when hold_trm goes low
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- INT_READ_IN: in std_logic;
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- INT_READ_OUT: out std_logic;
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-
- component trb_net16_io_multiplexer is
- generic (
- DATA_WIDTH : integer := 16;
- NUM_WIDTH : integer := 2;
- MUX_WIDTH : integer range 1 to 5 := 3;
- MUX_SECURE_MODE : integer range 0 to 1 := 0 --use sbufs or not?
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_DATAREADY_OUT: out std_logic;
- MED_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT:out std_logic_vector (NUM_WIDTH-1 downto 0);
- MED_READ_IN: in std_logic;
- -- Internal direction port
- INT_DATAREADY_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_OUT: out std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_OUT:out std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATAREADY_IN: in std_logic_vector (2**MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in std_logic_vector ((DATA_WIDTH)*(2**MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in std_logic_vector (2*(2**MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out std_logic_vector (2**MUX_WIDTH-1 downto 0);
- -- Status and control port
- CTRL: in std_logic_vector (31 downto 0);
- STAT: out std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_INIT_READ_IN: in std_logic;
- MED_INIT_DATAREADY_IN: in std_logic;
- MED_INIT_DATA_IN: in std_logic_vector (15 downto 0);
- MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_INIT_READ_OUT: out std_logic;
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
- MED_REPLY_DATAREADY_IN: in std_logic;
- MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0);
- MED_REPLY_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
- MED_REPLY_READ_OUT: out std_logic
- );
- end component;
-signal apl_to_buf_DAT_INIT_DATAREADY: std_logic;
-signal apl_to_buf_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_INIT_READ : std_logic;
-
-signal buf_to_apl_DAT_INIT_DATAREADY: std_logic;
-signal buf_to_apl_DAT_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_INIT_READ : std_logic;
-
-signal apl_to_buf_DAT_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_DAT_REPLY_READ : std_logic;
-
-signal buf_to_apl_DAT_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_DAT_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_DAT_REPLY_READ : std_logic;
-
-signal apl_to_buf_TRG_INIT_DATAREADY: std_logic;
-signal apl_to_buf_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG_INIT_READ : std_logic;
-
-signal buf_to_apl_TRG_INIT_DATAREADY: std_logic;
-signal buf_to_apl_TRG_INIT_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG_INIT_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG_INIT_READ : std_logic;
-
-signal apl_to_buf_TRG_REPLY_DATAREADY: std_logic;
-signal apl_to_buf_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal apl_to_buf_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal apl_to_buf_TRG_REPLY_READ : std_logic;
-
-signal buf_to_apl_TRG_REPLY_DATAREADY: std_logic;
-signal buf_to_apl_TRG_REPLY_DATA : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal buf_to_apl_TRG_REPLY_PACKET_NUM:std_logic_vector (NUM_WIDTH-1 downto 0);
-signal buf_to_apl_TRG_REPLY_READ : std_logic;
-
--- for the connection to the multiplexer
-signal MED_DAT_INIT_DATAREADY_OUT : std_logic;
-signal MED_DAT_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_INIT_READ_IN : std_logic;
-
-signal MED_DAT_INIT_DATAREADY_IN : std_logic;
-signal MED_DAT_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_INIT_READ_OUT : std_logic;
-
-signal MED_DAT_REPLY_DATAREADY_OUT : std_logic;
-signal MED_DAT_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_READ_IN : std_logic;
-
-signal MED_DAT_REPLY_DATAREADY_IN : std_logic;
-signal MED_DAT_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_DAT_REPLY_READ_OUT : std_logic;
-
-signal MED_TRG_INIT_DATAREADY_OUT : std_logic;
-signal MED_TRG_INIT_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_TRG_INIT_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_TRG_INIT_READ_IN : std_logic;
-
-signal MED_TRG_INIT_DATAREADY_IN : std_logic;
-signal MED_TRG_INIT_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_TRG_INIT_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_TRG_INIT_READ_OUT : std_logic;
-
-signal MED_TRG_REPLY_DATAREADY_OUT : std_logic;
-signal MED_TRG_REPLY_DATA_OUT : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_TRG_REPLY_PACKET_NUM_OUT : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_TRG_REPLY_READ_IN : std_logic;
-
-signal MED_TRG_REPLY_DATAREADY_IN : std_logic;
-signal MED_TRG_REPLY_DATA_IN : std_logic_vector (DATA_WIDTH-1 downto 0);
-signal MED_TRG_REPLY_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH-1 downto 0);
-signal MED_TRG_REPLY_READ_OUT : std_logic;
-
-signal m_DATAREADY_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (DATA_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-signal m_DATAREADY_IN : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-signal m_DATA_IN : std_logic_vector (DATA_WIDTH**MUX_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (NUM_WIDTH*2**MUX_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**MUX_WIDTH-1 downto 0);
-
-begin
-
- --Connections for data and trigger channel
- genmuxcon : for i in 0 to 2**(MUX_WIDTH-1)-1 generate
- gendat: if i = DAT_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_DAT_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_DAT_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_DAT_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_DAT_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_DAT_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_DAT_REPLY_PACKET_NUM_OUT;
- MED_DAT_INIT_READ_IN <= m_READ_IN(i*2);
- MED_DAT_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_DAT_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_DAT_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_DAT_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_DAT_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_DAT_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_DAT_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_DAT_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_DAT_REPLY_READ_OUT;
- end generate;
- gentrg: if i = TRG_CHANNEL generate
- m_DATAREADY_OUT(i*2) <= MED_TRG_INIT_DATAREADY_OUT;
- m_DATAREADY_OUT(i*2+1) <= MED_TRG_REPLY_DATAREADY_OUT;
- m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2) <= MED_TRG_INIT_DATA_OUT;
- m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH) <= MED_TRG_REPLY_DATA_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2) <= MED_TRG_INIT_PACKET_NUM_OUT;
- m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2) <= MED_TRG_REPLY_PACKET_NUM_OUT;
- MED_TRG_INIT_READ_IN <= m_READ_IN(i*2);
- MED_TRG_REPLY_READ_IN <= m_READ_IN(i*2+1);
- MED_TRG_INIT_DATAREADY_IN <= m_DATAREADY_IN(i*2);
- MED_TRG_REPLY_DATAREADY_IN <= m_DATAREADY_IN(i*2+1);
- MED_TRG_INIT_DATA_IN <= m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2);
- MED_TRG_REPLY_DATA_IN <= m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH);
- MED_TRG_INIT_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2);
- MED_TRG_REPLY_PACKET_NUM_IN <= m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2);
- m_READ_OUT(i*2) <= MED_TRG_INIT_READ_OUT;
- m_READ_OUT(i*2+1) <= MED_TRG_REPLY_READ_OUT;
- end generate;
- genelse: if i /= DAT_CHANNEL and i /= TRG_CHANNEL generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_IN => m_READ_IN(i*2),
- MED_INIT_DATAREADY_IN => m_DATAREADY_IN(i*2),
- MED_INIT_DATA_IN => m_DATA_IN((i*2+1)*DATA_WIDTH-1 downto i*DATA_WIDTH*2),
- MED_INIT_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+1 downto i*NUM_WIDTH*2),
- MED_INIT_READ_OUT => m_READ_OUT(i*2),
-
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT => m_PACKET_NUM_OUT(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1),
- MED_REPLY_DATAREADY_IN => m_DATAREADY_IN(i*2+1),
- MED_REPLY_DATA_IN => m_DATA_IN((i*2+2)*DATA_WIDTH-1 downto (i*2+1)*DATA_WIDTH),
- MED_REPLY_PACKET_NUM_IN => m_PACKET_NUM_IN(i*NUM_WIDTH*2+3 downto i*NUM_WIDTH*2+2),
- MED_REPLY_READ_OUT => m_READ_OUT(i*2+1)
- );
- end generate;
- end generate;
-
- gen_actapi: if API_TYPE = 1 generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => 1,
- FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT_INIT_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT_INIT_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT_INIT_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT_REPLY_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT_REPLY_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
- );
- end generate;
-
- gen_pasapi: if API_TYPE = 0 generate
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => DAT_FIFO_TO_INT_DEPTH,
- FIFO_TO_APL_DEPTH => DAT_FIFO_TO_APL_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => APL_DATA_IN,
- APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
- APL_WRITE_IN => APL_WRITE_IN,
- APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
- APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => APL_DTYPE_IN,
- APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
- APL_SEND_IN => APL_SEND_IN,
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => APL_DATA_OUT,
- APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT,
- APL_TYP_OUT => APL_TYP_OUT,
- APL_DATAREADY_OUT => APL_DATAREADY_OUT,
- APL_READ_IN => APL_READ_IN,
- -- APL Control port
- APL_RUN_OUT => APL_RUN_OUT,
- APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_MASTER_DATA_OUT => apl_to_buf_DAT_REPLY_DATA,
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_MASTER_READ_IN => apl_to_buf_DAT_REPLY_READ,
- INT_MASTER_DATAREADY_IN => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_MASTER_DATA_IN => buf_to_apl_DAT_REPLY_DATA,
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_MASTER_READ_OUT => buf_to_apl_DAT_REPLY_READ,
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_DAT_INIT_DATAREADY,
- INT_SLAVE_DATA_OUT => apl_to_buf_DAT_INIT_DATA,
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_SLAVE_READ_IN => apl_to_buf_DAT_INIT_READ,
- INT_SLAVE_DATAREADY_IN => buf_to_apl_DAT_INIT_DATAREADY,
- INT_SLAVE_DATA_IN => buf_to_apl_DAT_INIT_DATA,
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_SLAVE_READ_OUT => buf_to_apl_DAT_INIT_READ,
- -- Status and control port
- STAT_FIFO_TO_INT => DAT_api_stat_fifo_to_int,
- STAT_FIFO_TO_APL => DAT_api_stat_fifo_to_apl
- );
- end generate;
-
-STAT_DAT_api_control_signals(2 downto 0) <= APL_DATA_IN(2 downto 0);
-STAT_DAT_api_control_signals(3) <= APL_WRITE_IN;
-STAT_DAT_api_control_signals(4) <= APL_SEND_IN;
-STAT_DAT_api_control_signals(7 downto 5) <= (others => '0');
-STAT_DAT_api_control_signals(10 downto 8) <= apl_to_buf_DAT_INIT_DATA(2 downto 0);
-STAT_DAT_api_control_signals(11) <= apl_to_buf_DAT_INIT_DATAREADY;
-STAT_DAT_api_control_signals(12) <= apl_to_buf_DAT_INIT_READ;
-STAT_DAT_api_control_signals(31 downto 13) <= (others => '0');
-
-
-
-DAT_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => DAT_INIT_DEPTH,
- REPLY_DEPTH => DAT_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_DAT_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_DAT_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_DAT_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_DAT_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_DAT_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_DAT_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_DAT_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_DAT_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_DAT_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_DAT_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_DAT_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_DAT_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_DAT_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_DAT_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_DAT_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_DAT_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_DAT_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_DAT_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_DAT_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_DAT_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_DAT_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_DAT_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_DAT_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_DAT_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_DAT_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_DAT_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_DAT_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_DAT_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_DAT_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_DAT_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_DAT_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_DAT_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_DAT_GEN,
- STAT_LOCKED => STAT_DAT_LOCKED,
- STAT_INIT_BUFFER => STAT_DAT_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_DAT_REPLY_BUFFER,
- CTRL_GEN => CTRL_DAT_GEN,
- CTRL_LOCKED => CTRL_DAT_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_DAT_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_DAT_CTRL_REPLY_BUFFER
- );
-
- TRG_IOBUF: trb_net16_iobuf
- generic map(
- INIT_DEPTH => TRG_INIT_DEPTH,
- REPLY_DEPTH => TRG_REPLY_DEPTH
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_TRG_INIT_DATAREADY_OUT,
- MED_INIT_DATA_OUT => MED_TRG_INIT_DATA_OUT,
- MED_INIT_PACKET_NUM_OUT => MED_TRG_INIT_PACKET_NUM_OUT,
- MED_INIT_READ_IN => MED_TRG_INIT_READ_IN,
- MED_INIT_DATAREADY_IN => MED_TRG_INIT_DATAREADY_IN,
- MED_INIT_DATA_IN => MED_TRG_INIT_DATA_IN,
- MED_INIT_PACKET_NUM_IN => MED_TRG_INIT_PACKET_NUM_IN,
- MED_INIT_READ_OUT => MED_TRG_INIT_READ_OUT,
- MED_INIT_ERROR_IN => (others => '0'),
- MED_REPLY_DATAREADY_OUT => MED_TRG_REPLY_DATAREADY_OUT,
- MED_REPLY_DATA_OUT => MED_TRG_REPLY_DATA_OUT,
- MED_REPLY_PACKET_NUM_OUT=> MED_TRG_REPLY_PACKET_NUM_OUT,
- MED_REPLY_READ_IN => MED_TRG_REPLY_READ_IN,
- MED_REPLY_DATAREADY_IN => MED_TRG_REPLY_DATAREADY_IN,
- MED_REPLY_DATA_IN => MED_TRG_REPLY_DATA_IN,
- MED_REPLY_PACKET_NUM_IN => MED_TRG_REPLY_PACKET_NUM_IN,
- MED_REPLY_READ_OUT => MED_TRG_REPLY_READ_OUT,
- MED_REPLY_ERROR_IN => (others => '0'),
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_apl_TRG_INIT_DATAREADY,
- INT_INIT_DATA_OUT => buf_to_apl_TRG_INIT_DATA,
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_TRG_INIT_PACKET_NUM,
- INT_INIT_READ_IN => buf_to_apl_TRG_INIT_READ,
- INT_INIT_DATAREADY_IN => apl_to_buf_TRG_INIT_DATAREADY,
- INT_INIT_DATA_IN => apl_to_buf_TRG_INIT_DATA,
- INT_INIT_PACKET_NUM_IN => apl_to_buf_TRG_INIT_PACKET_NUM,
- INT_INIT_READ_OUT => apl_to_buf_TRG_INIT_READ,
- INT_REPLY_HEADER_IN => '0',
- INT_REPLY_DATAREADY_OUT => buf_to_apl_TRG_REPLY_DATAREADY,
- INT_REPLY_DATA_OUT => buf_to_apl_TRG_REPLY_DATA,
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_TRG_REPLY_PACKET_NUM,
- INT_REPLY_READ_IN => buf_to_apl_TRG_REPLY_READ,
- INT_REPLY_DATAREADY_IN => apl_to_buf_TRG_REPLY_DATAREADY,
- INT_REPLY_DATA_IN => apl_to_buf_TRG_REPLY_DATA,
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_TRG_REPLY_PACKET_NUM,
- INT_REPLY_READ_OUT => apl_to_buf_TRG_REPLY_READ,
- -- Status and control port
- STAT_GEN => STAT_TRG_GEN,
- STAT_LOCKED => STAT_TRG_LOCKED,
- STAT_INIT_BUFFER => STAT_TRG_INIT_BUFFER,
- STAT_REPLY_BUFFER => STAT_TRG_REPLY_BUFFER,
- CTRL_GEN => CTRL_TRG_GEN,
- CTRL_LOCKED => CTRL_TRG_LOCKED,
- STAT_CTRL_INIT_BUFFER => STAT_TRG_CTRL_INIT_BUFFER,
- STAT_CTRL_REPLY_BUFFER => STAT_TRG_CTRL_REPLY_BUFFER
- );
-
- MPLEX: trb_net16_io_multiplexer
- generic map (
- DATA_WIDTH => DATA_WIDTH,
- NUM_WIDTH => NUM_WIDTH,
- MUX_WIDTH => MUX_WIDTH,
- MUX_SECURE_MODE => MUX_SECURE_MODE
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => m_DATAREADY_IN,
- INT_DATA_OUT =>m_DATA_IN,
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
- INT_READ_IN =>m_READ_OUT,
- INT_DATAREADY_IN =>m_DATAREADY_OUT,
- INT_DATA_IN =>m_DATA_OUT,
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
- INT_READ_OUT =>m_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
- TRG_INIT : trb_net16_term
- generic map (
- SECURE_MODE => TRG_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => apl_to_buf_TRG_REPLY_DATAREADY,
- INT_DATA_OUT => apl_to_buf_TRG_REPLY_DATA,
- INT_PACKET_NUM_OUT => apl_to_buf_TRG_REPLY_PACKET_NUM,
- INT_READ_IN => apl_to_buf_TRG_REPLY_READ,
- INT_DATAREADY_IN => buf_to_apl_TRG_INIT_DATAREADY,
- INT_DATA_IN => buf_to_apl_TRG_INIT_DATA,
- INT_PACKET_NUM_IN => buf_to_apl_TRG_INIT_PACKET_NUM,
- INT_READ_OUT => buf_to_apl_TRG_INIT_READ,
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => TRG_SEQNR_OUT,
- APL_GOT_TRM => TRG_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => TRG_RELEASE_IN,
- APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
- -- Status and control port
- );
-
-
-
-apl_to_buf_TRG_INIT_DATAREADY <= '0';
-apl_to_buf_TRG_INIT_DATA <= (others => '0');
-apl_to_buf_TRG_INIT_PACKET_NUM <= (others => '0');
-buf_to_apl_TRG_REPLY_READ <= '1';
-end architecture;
+++ /dev/null
--- the full endpoint for HADES: trg, data, unused, regio
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
-entity trb_net16_endpoint_hades_full is
- generic (
- USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE);
- IBUF_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6);
- FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6);
- IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
- USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
-
-
-
- SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
- SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- SCTR_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
- --set to 0 for unused ctrl registers to save resources
- SCTR_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- SCTR_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
- --no data / address out?
- SCTR_USE_DATA_PORT : integer := c_NO;
- SCTR_USE_1WIRE_INTERFACE : integer := c_YES;
- SCTR_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- SCTR_INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- SCTR_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- SCTR_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- SCTR_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic;
- MED_ERROR_IN : in std_logic_vector (2 downto 0);
- MED_STAT_OP : in std_logic_vector (15 downto 0);
- MED_CTRL_OP : out std_logic_vector (15 downto 0);
-
- -- LVL1 trigger APL
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL1_GOT_TRIGGER_OUT : out std_logic;
- LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
- LVL1_RELEASE_IN : in std_logic := '0';
-
- -- IPU-Data Channel APL
- IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000";
- IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00";
- IPUD_APL_DATAREADY_IN : in std_logic := '0';
- IPUD_APL_READ_OUT : out std_logic;
- IPUD_APL_SHORT_TRANSFER_IN: in std_logic := '0';
- IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0";
- IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000";
- IPUD_APL_SEND_IN : in std_logic:= '0';
- IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000";
- IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0);
- IPUD_APL_DATAREADY_OUT : out std_logic;
- IPUD_APL_READ_IN : in std_logic:= '0';
- IPUD_APL_RUN_OUT : out std_logic;
- IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- LVL2-Data Channel APL
- LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000";
- LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00";
- LVL2_APL_DATAREADY_IN : in std_logic := '0';
- LVL2_APL_READ_OUT : out std_logic;
- LVL2_APL_SHORT_TRANSFER_IN: in std_logic := '0';
- LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0";
- LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000";
- LVL2_APL_SEND_IN : in std_logic:= '0';
- LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000";
- LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0);
- LVL2_APL_DATAREADY_OUT : out std_logic;
- LVL2_APL_READ_IN : in std_logic:= '0';
- LVL2_APL_RUN_OUT : out std_logic;
- LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
-
- -- Slow Control Data Port
- SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
- SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0) := (others => '0');
- SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0);
- --following ports only used when using internal data port
- SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- SCTR_READ_ENABLE_OUT : out std_logic;
- SCTR_WRITE_ENABLE_OUT : out std_logic;
- SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0);
- SCTR_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- SCTR_DATAREADY_IN : in std_logic := '0';
- SCTR_NO_MORE_DATA_IN : in std_logic := '0';
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0');
- SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000";
- SCTR_IDRAM_WR_IN : in std_logic := '0';
- SCTR_ONEWIRE_INOUT : inout std_logic;
- --Additional r/w access to ctrl registers
- SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- SCTR_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- SCTR_EXT_REG_WRITE_IN : in std_logic := '0';
- SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0');
- -- Status
- MPLEX_CTRL : in std_logic_vector (31 downto 0) := (others => '0');
- STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0');
- STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status
- STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status
- CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0')
- );
-end entity;
-
-
-
-
-
-architecture trb_net16_endpoint_1_trg_2_api_1_regio_arch of trb_net16_endpoint_1_trg_2_api_1_regio is
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_regIO is
- generic (
- REGISTER_WIDTH : integer range 32 to 32 := 32;
- ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 1; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
- --standard values for output registers
- INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '0');
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001";
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) :=
- (others => '1');
- USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port
-
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
-
- --Port to write Unique ID
- IDRAM_DATA_IN : in std_logic_vector(15 downto 0);
- IDRAM_DATA_OUT : out std_logic_vector(15 downto 0);
- IDRAM_ADDR_IN : in std_logic_vector(2 downto 0);
- IDRAM_WR_IN : in std_logic;
- MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
-
- --Common Register in / out
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0);
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- --Custom Register in / out
- REGISTERS_IN : in std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
- REGISTERS_OUT : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
- --Internal Data Port
- DAT_ADDR_OUT : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
- DAT_READ_ENABLE_OUT : out std_logic;
- DAT_WRITE_ENABLE_OUT: out std_logic;
- DAT_DATA_OUT : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
- --Data input can only be used as reaction on read or write access. write operation should return data
- --if successful
- DAT_DATA_IN : in std_logic_vector(REGISTER_WIDTH-1 downto 0);
- DAT_DATAREADY_IN : in std_logic;
- DAT_NO_MORE_DATA_IN : in std_logic;
- --finish transmission, when reading from a fifo and it got empty
- --Additional write access to ctrl registers
- EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
- EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0);
- EXT_REG_WRITE_IN : in std_logic;
- EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component trb_net16_iobuf is
- generic (
- IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
- USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
- USE_CHECKSUM : integer range 0 to 1 := c_YES;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
- REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- Media direction port
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
-
- MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read)
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic;
- MED_ERROR_IN: in std_logic_vector (2 downto 0);
-
-
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT: out std_logic;
- INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_IN: in std_logic;
-
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic;
-
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
-
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_GEN: out std_logic_vector (31 downto 0);
- STAT_IBUF_BUFFER: out std_logic_vector (31 downto 0);
- CTRL_GEN: in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER: in std_logic_vector (31 downto 0)
- );
- end component;
-
- component trb_net16_api_base is
- generic (
- API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
- FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
- FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO
- );
-
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- APL Transmitter port
- APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
- APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); -- Address of
- -- the target (only for active APIs)
-
- -- Receiver port
- APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
-
- -- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
-
- -- Internal direction port
- -- This is just a clone from trb_net_iobuf
-
- INT_MASTER_DATAREADY_OUT: out std_logic;
- INT_MASTER_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_IN: in std_logic;
-
- INT_MASTER_DATAREADY_IN: in std_logic;
- INT_MASTER_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_MASTER_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_MASTER_READ_OUT: out std_logic;
-
-
- INT_SLAVE_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
- -- header (only for the SLAVE path)
- INT_SLAVE_DATAREADY_OUT: out std_logic;
- INT_SLAVE_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_IN: in std_logic;
-
- INT_SLAVE_DATAREADY_IN: in std_logic;
- INT_SLAVE_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_SLAVE_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_SLAVE_READ_OUT: out std_logic;
-
- -- Status and control port
- STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
- STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
- );
- end component;
-
-
-
- component trb_net16_io_multiplexer is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- -- Media direction port
- MED_DATAREADY_IN: in STD_LOGIC;
- MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_OUT: out STD_LOGIC;
-
- MED_DATAREADY_OUT: out STD_LOGIC;
- MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0);
- MED_READ_IN: in STD_LOGIC;
-
- -- Internal direction port
- INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
- INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
- INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
-
- INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN: in STD_LOGIC_VECTOR ((c_DATA_WIDTH)*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (2*(2**c_MUX_WIDTH)-1 downto 0);
- INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-
- -- Status and control port
- CTRL: in STD_LOGIC_VECTOR (31 downto 0);
- STAT: out STD_LOGIC_VECTOR (31 downto 0)
- );
- end component;
-
- component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
- );
- end component;
- component trb_net16_term is
- generic (
- USE_APL_PORT : integer range 0 to 1 := 0;
- SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_IN: in std_logic;
-
- INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_READ_OUT: out std_logic;
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
- end component;
-signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0);
-
-signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0);
-
-signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0);
-
--- for the connection to the multiplexer
-signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);
-signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);
-
-signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);
-signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
-signal MED_IO_READ_IN : std_logic_vector(7 downto 0);
-
-signal buf_APL_DATA_IN : std_logic_vector(3*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_IN : std_logic_vector(3*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_IN : std_logic_vector(2 downto 0);
-signal buf_APL_READ_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(2 downto 0);
-signal buf_APL_DTYPE_IN : std_logic_vector(3*4-1 downto 0);
-signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(3*32-1 downto 0);
-signal buf_APL_SEND_IN : std_logic_vector(2 downto 0);
-signal buf_APL_TARGET_ADDRESS_IN : std_logic_vector(3*16-1 downto 0);
-signal buf_APL_DATA_OUT : std_logic_vector(3*c_DATA_WIDTH-1 downto 0);
-signal buf_APL_PACKET_NUM_OUT : std_logic_vector(3*c_NUM_WIDTH-1 downto 0);
-signal buf_APL_DATAREADY_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_READ_IN : std_logic_vector(2 downto 0);
-signal buf_APL_TYP_OUT : std_logic_vector(3*3-1 downto 0);
-signal buf_APL_RUN_OUT : std_logic_vector(2 downto 0);
-signal buf_APL_SEQNR_OUT : std_logic_vector(3*8-1 downto 0);
-
-signal MY_ADDRESS : std_logic_vector(15 downto 0);
-
-signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
-signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
-signal buf_STAT_CTRL_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-signal SCTR_REGIO_STAT : std_logic_vector(31 downto 0);
-
-signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-
-signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
-signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
-signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
-signal buf_IDRAM_WR_IN : std_logic;
-
-begin
-
- MED_CTRL_OP(15) <= MED_STAT_OP(15);
- MED_CTRL_OP(14 downto 0) <= (others => '0');
-
- --Connections for data channel
- genbuffers : for i in 0 to 3 generate
- geniobuf: if USE_CHANNEL(i) = c_YES generate
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => IBUF_DEPTH(i),
- IBUF_SECURE_MODE => IBUF_SECURE_MODE(i),
- SBUF_VERSION => 0,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),
- USE_VENDOR_CORES => c_YES,
- USE_CHECKSUM => cfg_USE_CHECKSUM(i),
- INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i),
- REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i)
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
-
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
- MED_ERROR_IN => MED_ERROR_IN,
-
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1),
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
-
- INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
-
- INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
-
- INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
-
- -- Status and control port
- STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32),
- STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
- CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
- STAT_CTRL_IBUF_BUFFER => buf_STAT_CTRL_INIT_BUFFER(32*(i+1)-1 downto i*32)
- );
- genactapi : if API_TYPE(i) = c_API_ACTIVE and i /= 0 generate
- DAT_ACTIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(i),
- APL_READ_OUT => buf_APL_READ_OUT(i),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(i),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
- APL_SEND_IN => buf_APL_SEND_IN(i),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(i),
- APL_READ_IN => buf_APL_READ_IN(i),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(i),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- genpasapi : if API_TYPE(i) = c_API_PASSIVE and i /= 0 generate
- constant j : integer := i-1;
- begin
- DAT_PASSIVE_API: trb_net16_api_base
- generic map (
- API_TYPE => API_TYPE(i),
- FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
- FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
- FORCE_REPLY => cfg_FORCE_REPLY(i),
- SBUF_VERSION => 0
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j),
- APL_READ_OUT => buf_APL_READ_OUT(j),
- APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
- APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
- APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
- APL_SEND_IN => buf_APL_SEND_IN(j),
- APL_TARGET_ADDRESS_IN => buf_APL_TARGET_ADDRESS_IN((j+1)*16-1 downto j*16),
- -- Receiver port
- APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
- APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
- APL_READ_IN => buf_APL_READ_IN(j),
- -- APL Control port
- APL_RUN_OUT => buf_APL_RUN_OUT(j),
- APL_MY_ADDRESS_IN => MY_ADDRESS,
- APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i),
- INT_SLAVE_HEADER_IN => '0',
- INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i),
- INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i),
- -- Status and control port
- STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
- STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
- );
- end generate;
- gentrgapi : if i = 0 generate
- apl_to_buf_INIT_DATAREADY(0) <= '0';
- apl_to_buf_INIT_DATA(15 downto 0) <= (others => '0');
- apl_to_buf_INIT_PACKET_NUM(1 downto 0) <= "00";
- buf_to_apl_REPLY_READ(0) <= '1';
- trglvl1 : trb_net16_term
- generic map(
- USE_APL_PORT => c_YES,
- SECURE_MODE => std_TERM_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
-
- INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
- INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_IN => apl_to_buf_REPLY_READ(i),
-
- INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
- INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_OUT => buf_to_apl_INIT_READ(i),
-
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => LVL1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => LVL1_SEQNR_OUT,
- APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => LVL1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN
- );
- end generate;
- end generate;
- gentermbuf: if USE_CHANNEL(i) = c_NO generate
- termbuf: trb_net16_term_buf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
- MED_READ_OUT => MED_IO_READ_OUT(i),
-
- MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1)
- );
- end generate;
- end generate;
-
-
- buf_APL_DATA_IN(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH) <= IPUD_APL_DATA_IN;
- buf_APL_DATA_IN(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH) <= LVL2_APL_DATA_IN;
- buf_APL_PACKET_NUM_IN(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH) <= IPUD_APL_PACKET_NUM_IN;
- buf_APL_PACKET_NUM_IN(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH) <= LVL2_APL_PACKET_NUM_IN;
- buf_APL_DATAREADY_IN(0) <= IPUD_APL_DATAREADY_IN;
- buf_APL_DATAREADY_IN(1) <= LVL2_APL_DATAREADY_IN;
- IPUD_APL_READ_OUT <= buf_APL_READ_OUT(0);
- LVL2_APL_READ_OUT <= buf_APL_READ_OUT(1);
- buf_APL_SHORT_TRANSFER_IN(0) <= IPUD_APL_SHORT_TRANSFER_IN;
- buf_APL_SHORT_TRANSFER_IN(1) <= LVL2_APL_SHORT_TRANSFER_IN;
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN;
- buf_APL_ERROR_PATTERN_IN(1*32-1 downto 0*32) <= IPUD_APL_ERROR_PATTERN_IN;
- buf_APL_ERROR_PATTERN_IN(2*32-1 downto 1*32) <= LVL2_APL_ERROR_PATTERN_IN;
- buf_APL_SEND_IN(0) <= IPUD_APL_SEND_IN;
- buf_APL_SEND_IN(1) <= LVL2_APL_SEND_IN;
- buf_APL_TARGET_ADDRESS_IN(1*16-1 downto 0*16) <= IPUD_APL_TARGET_ADDRESS_IN;
- buf_APL_TARGET_ADDRESS_IN(2*16-1 downto 1*16) <= LVL2_APL_TARGET_ADDRESS_IN;
-
- IPUD_APL_DATA_OUT <= buf_APL_DATA_OUT(1*c_DATA_WIDTH-1 downto 0*c_DATA_WIDTH);
- LVL2_APL_DATA_OUT <= buf_APL_DATA_OUT(2*c_DATA_WIDTH-1 downto 1*c_DATA_WIDTH);
- IPUD_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(1*c_NUM_WIDTH-1 downto 0*c_NUM_WIDTH);
- LVL2_APL_PACKET_NUM_OUT <= buf_APL_DATA_OUT(2*c_NUM_WIDTH-1 downto 1*c_NUM_WIDTH);
- IPUD_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(0);
- LVL2_APL_DATAREADY_OUT <= buf_APL_DATAREADY_OUT(1);
- buf_APL_READ_IN(0) <= IPUD_APL_READ_IN;
- buf_APL_READ_IN(1) <= LVL2_APL_READ_IN;
- IPUD_APL_TYP_OUT <= buf_APL_TYP_OUT(2 downto 0);
- LVL2_APL_TYP_OUT <= buf_APL_TYP_OUT(5 downto 3);
-
- buf_APL_DTYPE_IN(1*4-1 downto 0*4) <= IPUD_APL_DTYPE_IN;
- buf_APL_DTYPE_IN(2*4-1 downto 1*4) <= LVL2_APL_DTYPE_IN;
- IPUD_APL_RUN_OUT <= buf_APL_RUN_OUT(0);
- LVL2_APL_RUN_OUT <= buf_APL_RUN_OUT(1);
- IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8);
- LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8);
-
- gen_regio : if USE_CHANNEL(c_SLOW_CTRL_CHANNEL) = c_YES generate
- regIO : trb_net16_regIO
- generic map(
- REGISTER_WIDTH => 32,
- ADDRESS_WIDTH => 16,
- NUM_STAT_REGS => SCTR_NUM_STAT_REGS,
- NUM_CTRL_REGS => SCTR_NUM_CTRL_REGS,
- --standard values for output registers
- INIT_CTRL_REGS => SCTR_INIT_CTRL_REGS,
- --set to 0 for unused ctrl registers to save resources
- USED_CTRL_REGS => SCTR_USED_CTRL_REGS,
- --set to 0 for each unused bit in a register
- USED_CTRL_BITMASK => SCTR_USED_CTRL_BITMASK,
- --no data / address out?
- USE_DAT_PORT => SCTR_USE_DATA_PORT,
- INIT_ADDRESS => SCTR_INIT_ADDRESS,
- INIT_UNIQUE_ID => SCTR_INIT_UNIQUE_ID,
- COMPILE_TIME => SCTR_COMPILE_TIME,
- COMPILE_VERSION => SCTR_COMPILE_VERSION,
- HARDWARE_VERSION => SCTR_HARDWARE_VERSION
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- -- Port to API
- API_DATA_OUT => buf_APL_DATA_IN(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH),
- API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH),
- API_DATAREADY_OUT => buf_APL_DATAREADY_IN(2),
- API_READ_IN => buf_APL_READ_OUT(2),
- API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(2),
- API_DTYPE_OUT => buf_APL_DTYPE_IN(3*4-1 downto 2*4),
- API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN(3*32-1 downto 2*32),
- API_SEND_OUT => buf_APL_SEND_IN(2),
- API_TARGET_ADDRESS_OUT => buf_APL_TARGET_ADDRESS_IN(3*16-1 downto 2*16),
- API_DATA_IN => buf_APL_DATA_OUT(3*c_DATA_WIDTH-1 downto 2*c_DATA_WIDTH),
- API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT(3*c_NUM_WIDTH-1 downto 2*c_NUM_WIDTH),
- API_TYP_IN => buf_APL_TYP_OUT(3*3-1 downto 2*3),
- API_DATAREADY_IN => buf_APL_DATAREADY_OUT(2),
- API_READ_OUT => buf_APL_READ_IN(2),
- API_RUN_IN => buf_APL_RUN_OUT(2),
- API_SEQNR_IN => buf_APL_SEQNR_OUT(3*8-1 downto 2*8),
- --Port to write Unique ID
- IDRAM_DATA_IN => buf_IDRAM_DATA_IN,
- IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT,
- IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
- IDRAM_WR_IN => buf_IDRAM_WR_IN,
- MY_ADDRESS_OUT => MY_ADDRESS,
- --Common Register in / out
- COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
- COMMON_CTRL_REG_OUT => SCTR_COMMON_CTRL_REG_OUT,
- --Custom Register in / out
- REGISTERS_IN => SCTR_REGISTERS_IN,
- REGISTERS_OUT => SCTR_REGISTERS_OUT,
- --following ports only used when no internal register is accessed
- DAT_ADDR_OUT => SCTR_ADDR_OUT,
- DAT_READ_ENABLE_OUT => SCTR_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_OUT => SCTR_WRITE_ENABLE_OUT,
- DAT_DATA_OUT => SCTR_DATA_OUT,
- DAT_DATA_IN => SCTR_DATA_IN,
- DAT_DATAREADY_IN => SCTR_DATAREADY_IN,
- DAT_NO_MORE_DATA_IN => SCTR_NO_MORE_DATA_IN,
- EXT_REG_DATA_IN => SCTR_EXT_REG_DATA_IN,
- EXT_REG_DATA_OUT => SCTR_EXT_REG_DATA_OUT,
- EXT_REG_WRITE_IN => SCTR_EXT_REG_WRITE_IN,
- EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN,
- STAT => SCTR_REGIO_STAT
- );
- end generate;
-
- gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate
- buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN;
- buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN;
- buf_IDRAM_WR_IN <= SCTR_IDRAM_WR_IN;
- SCTR_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
- SCTR_ONEWIRE_INOUT <= '0';
- buf_COMMON_STAT_REG_IN <= SCTR_COMMON_STAT_REG_IN;
- end generate;
- gen_1wire : if SCTR_USE_1WIRE_INTERFACE = 1 generate
- buf_COMMON_STAT_REG_IN(19 downto 0) <= SCTR_COMMON_STAT_REG_IN(19 downto 0);
- buf_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32) <= SCTR_COMMON_STAT_REG_IN(SCTR_COMMON_STAT_REG_IN'left downto 32);
-
- SCTR_IDRAM_DATA_OUT <= (others => '0');
-
- onewire_interface : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => c_YES,
- CLK_PERIOD => 10
- )
- port map(
- CLK => CLK,
- RESET => RESET,
- --connection to 1-wire interface
- ONEWIRE => SCTR_ONEWIRE_INOUT,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => buf_IDRAM_DATA_IN,
- ADDR_OUT => buf_IDRAM_ADDR_IN,
- WRITE_OUT=> buf_IDRAM_WR_IN,
- TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
- STAT => open
- );
- end generate;
-
-
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN,
- MED_DATA_IN => MED_DATA_IN,
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
- MED_READ_OUT => MED_READ_OUT,
- MED_DATAREADY_OUT => MED_DATAREADY_OUT,
- MED_DATA_OUT => MED_DATA_OUT,
- MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- MED_READ_IN => MED_READ_IN,
- INT_DATAREADY_OUT => MED_IO_DATAREADY_IN,
- INT_DATA_OUT => MED_IO_DATA_IN,
- INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
- INT_READ_IN => MED_IO_READ_OUT,
- INT_DATAREADY_IN => MED_IO_DATAREADY_OUT,
- INT_DATA_IN => MED_IO_DATA_OUT,
- INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT,
- INT_READ_OUT => MED_IO_READ_IN,
- CTRL => MPLEX_CTRL
- );
-
-
-buf_STAT_CTRL_INIT_BUFFER <= STAT_CTRL_INIT_BUFFER;
-buf_CTRL_GEN <= CTRL_GEN;
-STAT_GEN_1 <= (others => '0');
-STAT_GEN_2 <= (others => '0');
-
-end architecture;
-
--- /dev/null
+-- an active api together with an iobuf
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
+--Entity decalaration for clock generator
+entity trb_net16_endpoint_active_4_channel is
+
+ generic (
+ IBUF_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE;
+ API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE;
+ API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_SECURE_MODE;
+ OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic;
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_STAT_OP_IN : in std_logic_vector (15 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector (15 downto 0);
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_READ_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_SHORT_TRANSFER_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_DTYPE_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*4-1 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*32-1 downto 0);
+ APL_SEND_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_TARGET_ADDRESS_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*16-1 downto 0);
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*c_NUM_WIDTH-1 downto 0);
+ APL_TYP_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*3-1 downto 0);
+ APL_DATAREADY_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_READ_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))-1 downto 0);
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector ((2**(c_MUX_WIDTH-1))*8-1 downto 0);
+ APL_LENGTH_IN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*16-1 downto 0);
+
+ -- Status and control port
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ MPLEX_CTRL : in std_logic_vector (31 downto 0);
+ CTRL_GEN : in std_logic_vector ((2**(c_MUX_WIDTH-1))*32-1 downto 0)
+ );
+end entity;
+
+architecture trb_net16_endpoint_active_4_channel_arch of trb_net16_endpoint_active_4_channel is
+
+ component trb_net16_iobuf is
+ generic (
+ IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
+ USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT : out std_logic;
+ MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_INIT_READ_IN : in std_logic;
+
+ MED_REPLY_DATAREADY_OUT : out std_logic;
+ MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_REPLY_READ_IN : in std_logic;
+
+ MED_DATAREADY_IN : in std_logic;
+ MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic;
+ MED_ERROR_IN : in std_logic_vector (2 downto 0);
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT : out std_logic;
+ INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_IN : in std_logic;
+
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
+
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
+
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_GEN : out std_logic_vector (31 downto 0);
+ STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
+ CTRL_GEN : in std_logic_vector (31 downto 0);
+ STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
+ STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_api_base is
+ generic (
+ API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH;
+ FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
+ APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO;
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_IN : in std_logic;
+ APL_READ_OUT : out std_logic;
+ APL_SHORT_TRANSFER_IN : in std_logic;
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_SEND_IN : in std_logic;
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic;
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ APL_LENGTH_IN : in std_logic_vector (15 downto 0);
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component trb_net16_io_multiplexer is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- Media direction port
+ MED_DATAREADY_IN : in STD_LOGIC;
+ MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out STD_LOGIC;
+
+ MED_DATAREADY_OUT : out STD_LOGIC;
+ MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in STD_LOGIC;
+
+ -- Internal direction port
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
+ INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
+
+ INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
+ INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
+
+ -- Status and control port
+ CTRL : in STD_LOGIC_VECTOR (31 downto 0);
+ STAT : out STD_LOGIC_VECTOR (31 downto 0)
+ );
+ end component;
+
+signal apl_to_buf_INIT_DATAREADY: std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal apl_to_buf_INIT_DATA : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal apl_to_buf_INIT_READ : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal buf_to_apl_INIT_DATAREADY: std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal buf_to_apl_INIT_DATA : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal buf_to_apl_INIT_READ : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal apl_to_buf_REPLY_DATAREADY: std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal apl_to_buf_REPLY_DATA : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal apl_to_buf_REPLY_READ : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal buf_to_apl_REPLY_DATAREADY: std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal buf_to_apl_REPLY_DATA : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal buf_to_apl_REPLY_READ : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal MED_INIT_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal MED_INIT_DATA_OUT : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal MED_INIT_PACKET_NUM_OUT : std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal MED_INIT_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal MED_IO_DATAREADY_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal MED_IO_DATA_IN : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal MED_IO_PACKET_NUM_IN : std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal MED_IO_READ_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal MED_REPLY_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal MED_REPLY_DATA_OUT : std_logic_vector (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
+signal MED_REPLY_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto 0);
+signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto 0);
+signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+
+signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
+signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
+
+signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH-1)*32-1 downto 0);
+signal buf_api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH-1)*32-1 downto 0);
+signal api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH-1)*32-1 downto 0);
+signal api_stat_fifo_to_int : std_logic_vector(2**(c_MUX_WIDTH-1)*32-1 downto 0);
+signal reset_internal : std_logic;
+
+signal buf_STAT_GEN : std_logic_vector(127 downto 0);
+signal buf_STAT_IBUF_BUFFER : std_logic_vector(127 downto 0);
+signal buf_CTRL_GEN : std_logic_vector(127 downto 0) := (others => '0');
+signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector(127 downto 0);
+signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector(127 downto 0);
+--signal MPLEX_CTRL : std_logic_vector(31 downto 0) := (others => '0');
+signal STAT_MPLEX : std_logic_vector(31 downto 0) := (others => '0');
+
+
+begin
+
+ reset_internal <= MED_STAT_OP_IN(13) or RESET;
+ MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15);
+ MED_CTRL_OP_OUT(14 downto 0) <= (others => '0');
+
+ --Connections for data channel
+ gen_muxcon : for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
+ m_DATAREADY_OUT(i*2) <= MED_INIT_DATAREADY_OUT(i);
+ m_DATAREADY_OUT(i*2+1) <= MED_REPLY_DATAREADY_OUT(i);
+ m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2) <= MED_INIT_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH);
+ m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH) <= MED_REPLY_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH);
+ m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH*2) <= MED_INIT_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
+ m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH) <= MED_REPLY_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
+ MED_INIT_READ_IN(i) <= m_READ_IN(i*2);
+ MED_REPLY_READ_IN(i) <= m_READ_IN(i*2+1);
+
+ MED_IO_DATAREADY_IN(i) <= m_DATAREADY_IN(i);
+ MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= m_DATA_IN(c_DATA_WIDTH-1 downto 0);
+ MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= m_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0);
+ m_READ_OUT(i) <= MED_IO_READ_OUT(i);
+ end generate;
+
+
+ gen_actapi: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
+ DAT_ACTIVE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FORCE_REPLY => cfg_FORCE_REPLY(i),
+ SBUF_VERSION => SBUF_VERSION,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS => c_NO,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => reset_internal,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_DATA_IN((i+1)*16-1 downto i*16),
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN((i+1)*3-1 downto i*3),
+ APL_DATAREADY_IN => APL_DATAREADY_IN(i),
+ APL_READ_OUT => APL_READ_OUT(i),
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN(i),
+ APL_DTYPE_IN => APL_DTYPE_IN((i+1)*4-1 downto i*4),
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
+ APL_SEND_IN => APL_SEND_IN(i),
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN((i+1)*16-1 downto i*16),
+ -- Receiver port
+ APL_DATA_OUT => APL_DATA_OUT((i+1)*16-1 downto i*16),
+ APL_PACKET_NUM_OUT=> APL_PACKET_NUM_OUT((i+1)*3-1 downto i*3),
+ APL_TYP_OUT => APL_TYP_OUT((i+1)*3-1 downto i*3),
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT(i),
+ APL_READ_IN => APL_READ_IN(i),
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT(i),
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT((i+1)*8-1 downto i*8),
+ APL_LENGTH_IN => APL_LENGTH_IN((i+1)*16-1 downto i*16),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i),
+ INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16),
+ INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i),
+ INT_MASTER_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
+ INT_MASTER_DATA_IN => buf_to_apl_INIT_DATA((i+1)*16-1 downto i*16),
+ INT_MASTER_PACKET_NUM_IN => buf_to_apl_INIT_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_MASTER_READ_OUT => buf_to_apl_INIT_READ(i),
+ INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*16-1 downto i*16),
+ INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i),
+ INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i),
+ INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*16-1 downto i*16),
+ INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
+ -- Status and control port
+ STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
+ STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
+ );
+
+ THE_IOBUF: trb_net16_iobuf
+ generic map (
+ IBUF_DEPTH => IBUF_DEPTH,
+ IBUF_SECURE_MODE => IBUF_SECURE_MODE,
+ SBUF_VERSION => SBUF_VERSION,
+ USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i),
+ USE_CHECKSUM => USE_CHECKSUM,
+ INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA,
+ REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA,
+ REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA
+ )
+ port map (
+ -- Misc
+ CLK => CLK ,
+ RESET => reset_internal,
+ CLK_EN => CLK_EN,
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT => MED_INIT_DATAREADY_OUT(i),
+ MED_INIT_DATA_OUT => MED_INIT_DATA_OUT((i+1)*16-1 downto i*16),
+ MED_INIT_PACKET_NUM_OUT => MED_INIT_PACKET_NUM_OUT((i+1)*3-1 downto i*3),
+ MED_INIT_READ_IN => MED_INIT_READ_IN(i),
+
+ MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
+ MED_DATA_IN => MED_IO_DATA_IN((i+1)*16-1 downto i*16),
+ MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*3-1 downto i*3),
+ MED_READ_OUT => MED_IO_READ_OUT(i),
+ MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0),
+
+ MED_REPLY_DATAREADY_OUT => MED_REPLY_DATAREADY_OUT(i),
+ MED_REPLY_DATA_OUT => MED_REPLY_DATA_OUT((i+1)*16-1 downto i*16),
+ MED_REPLY_PACKET_NUM_OUT=> MED_REPLY_PACKET_NUM_OUT((i+1)*3-1 downto i*3),
+ MED_REPLY_READ_IN => MED_REPLY_READ_IN(i),
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
+ INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*16-1 downto i*16),
+ INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_INIT_READ_IN => buf_to_apl_INIT_READ(i),
+
+ INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i),
+ INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16),
+ INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i),
+
+ INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*16-1 downto i*16),
+ INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i),
+
+ INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i),
+ INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*16-1 downto i*16),
+ INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*3-1 downto i*3),
+ INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i),
+
+ -- Status and control port
+ STAT_GEN => buf_STAT_GEN((i+1)*32-1 downto i*32),
+ STAT_IBUF_BUFFER => buf_STAT_IBUF_BUFFER((i+1)*32-1 downto i*32),
+ CTRL_GEN => buf_CTRL_GEN((i+1)*32-1 downto i*32),
+ STAT_INIT_OBUF_DEBUG => buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32),
+ STAT_REPLY_OBUF_DEBUG => buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32)
+ );
+
+ end generate;
+
+
+
+
+--api_stat_fifo_to_apl <= buf_api_stat_fifo_to_apl;
+--api_stat_fifo_to_int <= buf_api_stat_fifo_to_int;
+-- STAT_INIT_BUFFER <= buf_STAT_INIT_BUFFER;
+
+ MPLEX: trb_net16_io_multiplexer
+
+ port map (
+ CLK => CLK,
+ RESET => reset_internal,
+ CLK_EN => CLK_EN,
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+ INT_DATAREADY_OUT => m_DATAREADY_IN,
+ INT_DATA_OUT => m_DATA_IN,
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN,
+ INT_READ_IN => m_READ_OUT,
+ INT_DATAREADY_IN => m_DATAREADY_OUT,
+ INT_DATA_IN => m_DATA_OUT,
+ INT_PACKET_NUM_IN => m_PACKET_NUM_OUT,
+ INT_READ_OUT => m_READ_IN,
+ CTRL => MPLEX_CTRL,
+ STAT => STAT_MPLEX
+ );
+
+end architecture;
+
APL_MY_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
APL_SEQNR_OUT : out std_logic_vector (VAL(API_NUMBER*8) downto 0);
APL_LENGTH_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
- --TRG interfaces
- TRG_GOT_TRIGGER_OUT : out std_logic_vector (VAL(TRG_NUMBER) downto 0);
- TRG_ERROR_PATTERN_OUT : out std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
- TRG_DTYPE_OUT : out std_logic_vector (VAL(TRG_NUMBER*4) downto 0);
- TRG_SEQNR_OUT : out std_logic_vector (VAL(TRG_NUMBER*8) downto 0);
- TRG_ERROR_PATTERN_IN : in std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
- TRG_RELEASE_IN : in std_logic_vector (VAL(TRG_NUMBER) downto 0);
ONEWIRE : inout std_logic;
--Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
- signal IOBUF_CTRL_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_STAT_INIT_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0);
STAT_GEN : out std_logic_vector (31 downto 0);
STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0);
CTRL_GEN : in std_logic_vector (31 downto 0);
- STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0);
STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0);
STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0)
);
STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32),
CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
- STAT_CTRL_IBUF_BUFFER => IOBUF_CTRL_IBUF_BUFFER((i+1)*32-1 downto i*32),
STAT_INIT_OBUF_DEBUG => IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32),
STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32)
);
end generate;
end generate;
- gen_trgapi : if TRG_NUMBER /= 0 generate
- gen_apis : for i in 2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER to 2**(c_MUX_WIDTH-1)*MII_NUMBER+API_NUMBER+TRG_NUMBER generate
- constant trg_offset : integer := i - (2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER);
- begin
- TRG : trb_net16_term
- generic map (
- SECURE_MODE => TRG_SECURE_MODE
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- INT_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
- INT_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_IN => buf_to_hub_REPLY_READ(i),
- INT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),
- INT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_READ_OUT => hub_to_buf_INIT_READ(i),
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => TRG_DTYPE_OUT((trg_offset+1)*3-1 downto trg_offset*3),
- APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT((trg_offset+1)*32-1 downto trg_offset*32),
- APL_SEQNR_OUT => TRG_SEQNR_OUT((trg_offset+1)*8-1 downto trg_offset*8),
- APL_GOT_TRM => TRG_GOT_TRIGGER_OUT(trg_offset),
- APL_RELEASE_TRM => TRG_RELEASE_IN(trg_offset),
- APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN((trg_offset+1)*32-1 downto trg_offset*32)
- -- Status and control port
- );
- end generate;
- end generate;
+-- gen_trgapi : if TRG_NUMBER /= 0 generate
+-- gen_apis : for i in 2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER to 2**(c_MUX_WIDTH-1)*MII_NUMBER+API_NUMBER+TRG_NUMBER generate
+-- constant trg_offset : integer := i - (2**(c_MUX_WIDTH-1)*MII_NUMBER+1+API_NUMBER);
+-- begin
+-- TRG : trb_net16_term
+-- generic map (
+-- SECURE_MODE => TRG_SECURE_MODE
+-- )
+-- port map(
+-- -- Misc
+-- CLK => CLK,
+-- RESET => RESET,
+-- CLK_EN => CLK_EN,
+-- INT_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
+-- INT_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+-- INT_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+-- INT_READ_IN => buf_to_hub_REPLY_READ(i),
+-- INT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),
+-- INT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+-- INT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+-- INT_READ_OUT => hub_to_buf_INIT_READ(i),
+-- -- "mini" APL, just to see the triggers coming in
+-- APL_DTYPE_OUT => TRG_DTYPE_OUT((trg_offset+1)*3-1 downto trg_offset*3),
+-- APL_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT((trg_offset+1)*32-1 downto trg_offset*32),
+-- APL_SEQNR_OUT => TRG_SEQNR_OUT((trg_offset+1)*8-1 downto trg_offset*8),
+-- APL_GOT_TRM => TRG_GOT_TRIGGER_OUT(trg_offset),
+-- APL_RELEASE_TRM => TRG_RELEASE_IN(trg_offset),
+-- APL_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN((trg_offset+1)*32-1 downto trg_offset*32)
+-- -- Status and control port
+-- );
+-- end generate;
+-- end generate;
--rearrange vectors for hub logic
gen_rearrange : for CHANNEL in 0 to 2**(c_MUX_WIDTH-1)-1 generate
constant api_num : integer := calc_special_number(CHANNEL, API_NUMBER, API_CHANNELS);
- constant trg_num : integer := calc_special_number(CHANNEL, TRG_NUMBER, TRG_CHANNELS);
- constant first_point_num : integer := calc_first_point_number(MII_NUMBER, CHANNEL, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS);
+ constant trg_num : integer := calc_special_number(CHANNEL, 0, TRG_CHANNELS);
+ constant first_point_num : integer := calc_first_point_number(MII_NUMBER, CHANNEL, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, 0, TRG_CHANNELS);
constant is_ctrl_channel : integer := calc_is_ctrl_channel(CHANNEL, HUB_CTRL_CHANNELNUM);
begin
gen_hublogicsignals1 : for mii in 0 to MII_NUMBER-1 generate
end generate;
end generate;
end generate;
- g3: if trg_num /= 0 generate
- gen_hublogicsignals3 : for trg in 0 to TRG_NUMBER-1 generate
- constant hublogic_num : integer := first_point_num + MII_NUMBER + is_ctrl_channel + calc_special_number(CHANNEL, API_NUMBER, API_CHANNELS) + calc_special_number(CHANNEL, trg, TRG_CHANNELS);
- constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1 + API_NUMBER + trg;
- begin
- h1: if TRG_CHANNELS(trg) = CHANNEL generate
- HUB_INIT_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num);
- HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_INIT_READ(buf_to_hub_num)
- <= HUB_INIT_READ_OUT(hublogic_num);
-
- hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
- <= HUB_INIT_DATAREADY_OUT(hublogic_num);
- hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_INIT_READ_IN (hublogic_num)
- <= hub_to_buf_INIT_READ(buf_to_hub_num);
-
- HUB_REPLY_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
- HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_REPLY_READ(buf_to_hub_num)
- <= HUB_REPLY_READ_OUT(hublogic_num);
-
- hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
- <= HUB_REPLY_DATAREADY_OUT(hublogic_num);
- hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_REPLY_READ_IN (hublogic_num)
- <= hub_to_buf_REPLY_READ(buf_to_hub_num);
- end generate;
- end generate;
- end generate;
+-- g3: if trg_num /= 0 generate
+-- gen_hublogicsignals3 : for trg in 0 to TRG_NUMBER-1 generate
+-- constant hublogic_num : integer := first_point_num + MII_NUMBER + is_ctrl_channel + calc_special_number(CHANNEL, API_NUMBER, API_CHANNELS) + calc_special_number(CHANNEL, trg, TRG_CHANNELS);
+-- constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1 + API_NUMBER + trg;
+-- begin
+-- h1: if TRG_CHANNELS(trg) = CHANNEL generate
+-- HUB_INIT_DATAREADY_IN (hublogic_num)
+-- <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num);
+-- HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
+-- <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
+-- HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
+-- <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
+-- buf_to_hub_INIT_READ(buf_to_hub_num)
+-- <= HUB_INIT_READ_OUT(hublogic_num);
+--
+-- hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
+-- <= HUB_INIT_DATAREADY_OUT(hublogic_num);
+-- hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
+-- <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
+-- hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
+-- <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
+-- HUB_INIT_READ_IN (hublogic_num)
+-- <= hub_to_buf_INIT_READ(buf_to_hub_num);
+--
+-- HUB_REPLY_DATAREADY_IN (hublogic_num)
+-- <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
+-- HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
+-- <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
+-- HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
+-- <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
+-- buf_to_hub_REPLY_READ(buf_to_hub_num)
+-- <= HUB_REPLY_READ_OUT(hublogic_num);
+--
+-- hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
+-- <= HUB_REPLY_DATAREADY_OUT(hublogic_num);
+-- hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
+-- <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
+-- hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
+-- <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
+-- HUB_REPLY_READ_IN (hublogic_num)
+-- <= hub_to_buf_REPLY_READ(buf_to_hub_num);
+-- end generate;
+-- end generate;
+-- end generate;
end generate;
gen_MED_CON : for i in 0 to MII_NUMBER-1 generate
--generate hub logic
gen_hub_logic: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS);
- constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, TRG_NUMBER, TRG_CHANNELS);
+ constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, 0, TRG_CHANNELS);
+ constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, API_NUMBER, API_CHANNELS, 0, TRG_CHANNELS);
constant next_point_num : integer := first_point_num + point_num;
begin
gen_logic : if HUB_USED_CHANNELS(i) = 1 generate
signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal reg_IPU_DATA : std_logic_vector (15 downto 0);
signal saved_IPU_READOUT_FINISHED_IN : std_logic;
+ signal state_bits : std_logic_vector(2 downto 0);
begin
buf_API_READ_OUT <= '0';
buf_START_READOUT <= '0';
update_buffers <= '0';
+ waiting_word <= '0';
+ buf_API_DATAREADY_OUT <= '0';
else
buf_API_READ_OUT <= '1';
case state is
PROC_store_IPU_input : process(CLK)
begin
if rising_edge(CLK) then
- if IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then
+ if RESET = '1' then
+ reg_IPU_DATA <= (others => '0');
+ elsif IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then
reg_IPU_DATA <= IPU_DATA_IN(15 downto 0);
end if;
end if;
STAT_DEBUG <= (others => '0');
+ state_bits(0) <= '1' when state = START else '0';
+ state_bits(1) <= '1' when state = WAITING else '0';
+ state_bits(2) <= '1' when state = READING else '0';
+
+
+
end architecture;
\ No newline at end of file
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
-------------------------------------------------------------------------------
-- Single buffer with one more buffer to keep the speed of the datalink
-- The sbuf can be connected to a combinatorial logic (as an output buffer)
-------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-
-
entity trb_net16_sbuf is
generic (
VERSION : integer := 0
architecture trb_net16_sbuf_arch of trb_net16_sbuf is
-component trb_net_sbuf is
- generic (
- DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH;
- VERSION: integer := VERSION);
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
- COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
- COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
- COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_DATAREADY_OUT: out STD_LOGIC;
- SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
- SYN_READ_IN: in STD_LOGIC;
- STAT_BUFFER: out STD_LOGIC
- );
-end component;
+ component trb_net_sbuf is
+ generic (
+ DATA_WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH;
+ VERSION: integer := VERSION);
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ STAT_BUFFER: out STD_LOGIC
+ );
+ end component;
signal comb_in, syn_out : std_logic_vector (c_DATA_WIDTH + c_NUM_WIDTH - 1 downto 0);
begin
-comb_in(c_DATA_WIDTH - 1 downto 0) <= COMB_DATA_IN;
-comb_in(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= COMB_PACKET_NUM_IN;
-SYN_DATA_OUT <= syn_out(c_DATA_WIDTH - 1 downto 0);
-SYN_PACKET_NUM_OUT <= syn_out(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH);
-
-sbuf: trb_net_sbuf
- port map(
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => COMB_DATAREADY_IN,
- COMB_next_READ_OUT => COMB_next_READ_OUT,
- COMB_READ_IN => COMB_READ_IN,
- COMB_DATA_IN => comb_in,
- SYN_DATAREADY_OUT => SYN_DATAREADY_OUT,
- SYN_DATA_OUT => syn_out,
- SYN_READ_IN => SYN_READ_IN,
- STAT_BUFFER => STAT_BUFFER
- );
-
+ comb_in(c_DATA_WIDTH - 1 downto 0) <= COMB_DATA_IN;
+ comb_in(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= COMB_PACKET_NUM_IN;
+ SYN_DATA_OUT <= syn_out(c_DATA_WIDTH - 1 downto 0);
+ SYN_PACKET_NUM_OUT <= syn_out(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH);
+ sbuf: trb_net_sbuf
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => COMB_DATAREADY_IN,
+ COMB_next_READ_OUT => COMB_next_READ_OUT,
+ COMB_READ_IN => COMB_READ_IN,
+ COMB_DATA_IN => comb_in,
+ SYN_DATAREADY_OUT => SYN_DATAREADY_OUT,
+ SYN_DATA_OUT => syn_out,
+ SYN_READ_IN => SYN_READ_IN,
+ STAT_BUFFER => STAT_BUFFER
+ );
end architecture;
begin
if rising_edge(CLK) then
if RESET = '1' then
- transfer_counter <= (others => '0');
+ transfer_counter <= c_H0;
elsif CLK_EN = '1' and buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
if transfer_counter = c_max_word_number then
transfer_counter <= (others => '0');
type BUFFER_STATE is (BUFFER_EMPTY, BUFFER_B2_FULL, BUFFER_B1_FULL);
signal current_buffer_state, next_buffer_state : BUFFER_STATE;
--- signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0);
+ signal current_buffer_state_int : STD_LOGIC_VECTOR (1 downto 0);
signal current_got_overflow, next_got_overflow : std_logic;
signal combined_COMB_DATAREADY_IN: std_logic;
next_got_overflow <= current_got_overflow;
if current_buffer_state = BUFFER_EMPTY then
--- current_buffer_state_int <= "00";
+ current_buffer_state_int <= "00";
if combined_COMB_DATAREADY_IN = '1' then
-- COMB logic is writing into the sbuf
next_buffer_state <= BUFFER_B2_FULL;
next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B2_FULL then
--- current_buffer_state_int <= "01";
+ current_buffer_state_int <= "01";
if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
end if;
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
- elsif combined_COMB_DATAREADY_IN = '1' then
+ elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then
-- ONLY COMB logic is writing into the sbuf
-- this is the case when we should use the additional
-- buffer
next_next_READ_OUT <= '0'; --PLEASE stop writing
move_b1_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
- elsif SYN_READ_IN = '1' then
+ elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then
next_buffer_state <= BUFFER_EMPTY;
next_SYN_DATAREADY_OUT <= '0';
- else
+ else --if combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '0' then
next_next_READ_OUT <= '0';
next_SYN_DATAREADY_OUT <= '1';
end if;
elsif current_buffer_state = BUFFER_B1_FULL then
--- current_buffer_state_int <= "10";
+ current_buffer_state_int <= "10";
next_SYN_DATAREADY_OUT <= '1';
next_next_READ_OUT <= '0';
use_current_b1_buffer <= '1';
move_b1_buffer <= '1';
move_b2_buffer <= '1';
- elsif combined_COMB_DATAREADY_IN = '1' then
+ elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then
-- ONLY COMB logic is writing into the sbuf FATAL ERROR
next_got_overflow <= '1';
- elsif SYN_READ_IN = '1' then
+ elsif combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1' then
next_buffer_state <= BUFFER_B2_FULL;
next_next_READ_OUT <= '1'; --?
use_current_b1_buffer <= '1';
-- almost impossible taking into account that
-- the SYN reader may release the RD signal at any point
-- if this is the case, BREAK
-
+--combined_COMB_DATAREADY_IN = '0' and SYN_READ_IN = '1'
EM_STOP : process(current_next_READ_OUT, SYN_READ_IN, current_SYN_DATAREADY_OUT,
current_buffer_state)
begin
- COMB_next_READ_OUT <= current_next_READ_OUT;
if VERSION = 0 then
- if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1'
- and current_buffer_state = BUFFER_B2_FULL then
+ if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then
COMB_next_READ_OUT <= '0';
+ elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then
+ COMB_next_READ_OUT <= '1';
+ else
+ COMB_next_READ_OUT <= current_next_READ_OUT;
end if;
+ else
+ COMB_next_READ_OUT <= current_next_READ_OUT;
end if;
end process EM_STOP;
jspc29 / trbnet.git / commitdiff