end process PROC_I2C_MASTER_TRANSFER;\r
\r
\r
- PROC_I2C_MASTER: process(STATE)\r
+ PROC_I2C_MASTER: process(STATE,\r
+ spi_start,\r
+ wait_timer_done,\r
+ sendbyte_done,\r
+ readbyte_done\r
+ )\r
\r
begin\r
-- Defaults\r
end if;\r
end process PROC_READ_BYTE_TRANSFER; \r
\r
- PROC_READ_BYTE: process(STATE)\r
+ PROC_READ_BYTE: process(STATE,\r
+ START_IN,\r
+ wait_timer_done,\r
+ bit_ctr\r
+ )\r
begin \r
sclk_o <= '0';\r
sequence_done_o_x <= '0';\r
end if;\r
end process PROC_SEND_BYTE_TRANSFER; \r
\r
- PROC_SEND_BYTE: process(STATE)\r
+ PROC_SEND_BYTE: process(STATE,\r
+ START_IN,\r
+ wait_timer_done,\r
+ bit_ctr\r
+ )\r
begin \r
sdio_o <= '0';\r
sclk_o <= '0';\r
library ieee;
use ieee.std_logic_1164.all;
-use IEEE.numeric_std.ALL;
+use ieee.numeric_std.all;
package adcmv3_components is
-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
-- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -regout -no_enable -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 32 -depth 64 -regout -no_enable -pe -1 -pf -1 -e
--- Mon Oct 15 20:08:21 2012
+-- Sun Dec 2 17:35:19 2012
library IEEE;
use IEEE.std_logic_1164.all;
signal ifcount_5: std_logic;
signal co1: std_logic;
signal ifcount_6: std_logic;
- signal ifcount_7: std_logic;
- signal co2: std_logic;
- signal ifcount_8: std_logic;
- signal ifcount_9: std_logic;
- signal co4: std_logic;
- signal cnt_con: std_logic;
signal co3: std_logic;
+ signal cnt_con: std_logic;
+ signal co2: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal co0_1: std_logic;
signal co1_1: std_logic;
signal co2_1: std_logic;
- signal co3_1: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
signal fcount_2: std_logic;
signal fcount_3: std_logic;
signal co1_2: std_logic;
+ signal wren_i: std_logic;
signal fcount_4: std_logic;
signal fcount_5: std_logic;
signal co2_2: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
- signal co3_2: std_logic;
- signal wren_i: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_8: std_logic;
- signal fcount_9: std_logic;
+ signal fcount_6: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal wcount_5: std_logic;
signal co1_3: std_logic;
signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
+ signal co3_1: std_logic;
signal wcount_6: std_logic;
- signal wcount_7: std_logic;
signal co2_3: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4_1: std_logic;
- signal wcount_8: std_logic;
- signal wcount_9: std_logic;
- signal co3_3: std_logic;
- signal scuba_vlo: std_logic;
signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal rcount_5: std_logic;
signal co1_4: std_logic;
signal ircount_6: std_logic;
- signal ircount_7: std_logic;
+ signal co3_2: std_logic;
signal rcount_6: std_logic;
- signal rcount_7: std_logic;
+ signal scuba_vlo: std_logic;
signal co2_4: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_2: std_logic;
- signal rcount_8: std_logic;
- signal rcount_9: std_logic;
- signal co3_4: std_logic;
-- local component declarations
component AGEB2
attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32_data.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
attribute GSR of FF_22 : label is "ENABLED";
attribute GSR of FF_21 : label is "ENABLED";
attribute GSR of FF_20 : label is "ENABLED";
DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
- ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo,
BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
- ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
- ADR13=>rcount_8, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ ADR10=>rcount_5, ADR11=>scuba_vlo, ADR12=>scuba_vlo,
+ ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
DO34=>Q(16), DO35=>Q(17));
- FF_31: FD1P3DX
+ FF_22: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_30: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_29: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_28: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_27: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_26: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_25: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_24: FD1P3DX
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_7);
-
- FF_23: FD1P3DX
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_8);
-
- FF_22: FD1P3DX
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
- Q=>fcount_9);
-
- FF_21: FD1S3BX
+ FF_15: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_20: FD1S3DX
+ FF_14: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_19: FD1P3DX
+ FF_13: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_18: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_17: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_16: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_15: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_14: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_13: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_12: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_7);
-
- FF_11: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_8);
-
- FF_10: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
- Q=>wcount_9);
-
- FF_9: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_8: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_7: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_6: FD1P3DX
+ FF_3: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_5: FD1P3DX
+ FF_2: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_4: FD1P3DX
+ FF_1: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_3: FD1P3DX
+ FF_0: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
- FF_2: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_7);
-
- FF_1: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_8);
-
- FF_0: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
- Q=>rcount_9);
-
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
- CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
-
- bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
- CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+ port map (CI=>co2, PC0=>fcount_6, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>open);
e_cmp_ci_a: FADD2B
port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
-
- e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+ port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c);
a0: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
- CI=>co2_2, GE=>co3_2);
-
- g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
- CI=>co3_2, GE=>cmp_ge_d1_c);
+ port map (A0=>fcount_6, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co2_2, GE=>cmp_ge_d1_c);
a1: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3_1,
+ NC0=>iwcount_6, NC1=>open);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
- r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
- NC0=>ircount_6, NC1=>ircount_7);
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
- r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
- NC0=>ircount_8, NC1=>ircount_9);
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_2,
+ NC0=>ircount_6, NC1=>open);
Empty <= empty_i;
Full <= full_i;
-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
-- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 9 -depth 64 -rdata_width 36 -regout -no_enable -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -pe -1 -pf -1 -e
--- Tue Nov 13 20:22:07 2012
+-- Sat Nov 24 15:58:10 2012
library IEEE;
use IEEE.std_logic_1164.all;
signal invout_0: std_logic;
signal wcount_r1: std_logic;
signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
signal w_gdata_0: std_logic;
signal w_gdata_1: std_logic;
signal w_gdata_2: std_logic;
signal w_gdata_3: std_logic;
signal w_gdata_4: std_logic;
signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
signal wptr_0: std_logic;
signal wptr_1: std_logic;
signal wptr_2: std_logic;
signal wptr_4: std_logic;
signal wptr_5: std_logic;
signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
signal r_gdata_0: std_logic;
signal r_gdata_1: std_logic;
signal r_gdata_2: std_logic;
signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
signal rptr_0: std_logic;
signal rptr_1: std_logic;
signal rptr_2: std_logic;
signal rptr_3: std_logic;
signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
signal w_gcount_0: std_logic;
signal w_gcount_1: std_logic;
signal w_gcount_2: std_logic;
signal w_gcount_4: std_logic;
signal w_gcount_5: std_logic;
signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
signal r_gcount_0: std_logic;
signal r_gcount_1: std_logic;
signal r_gcount_2: std_logic;
signal r_gcount_3: std_logic;
signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
signal w_gcount_r20: std_logic;
signal w_gcount_r0: std_logic;
signal w_gcount_r21: std_logic;
signal w_gcount_r5: std_logic;
signal w_gcount_r26: std_logic;
signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
signal r_gcount_w20: std_logic;
signal r_gcount_w0: std_logic;
signal r_gcount_w21: std_logic;
signal r_gcount_w3: std_logic;
signal r_gcount_w24: std_logic;
signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
signal empty_i: std_logic;
signal rRst: std_logic;
signal full_i: std_logic;
signal iwcount_5: std_logic;
signal co1: std_logic;
signal iwcount_6: std_logic;
- signal co3: std_logic;
- signal wcount_6: std_logic;
+ signal iwcount_7: std_logic;
signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal co4: std_logic;
+ signal wcount_8: std_logic;
+ signal co3: std_logic;
signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal ircount_3: std_logic;
signal co0_1: std_logic;
signal ircount_4: std_logic;
- signal co2_1: std_logic;
- signal rcount_4: std_logic;
+ signal ircount_5: std_logic;
signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal co3_1: std_logic;
+ signal rcount_6: std_logic;
+ signal co2_1: std_logic;
signal rden_i: std_logic;
signal cmp_ci: std_logic;
signal wcount_r2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r3: std_logic;
signal rcount_0: std_logic;
signal rcount_1: std_logic;
signal co0_2: std_logic;
signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
signal rcount_2: std_logic;
signal rcount_3: std_logic;
signal co1_2: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
signal empty_cmp_clr: std_logic;
signal empty_cmp_set: std_logic;
signal empty_d: std_logic;
signal wcount_1: std_logic;
signal co0_3: std_logic;
signal rcount_w0: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w1: std_logic;
signal wcount_2: std_logic;
signal wcount_3: std_logic;
signal co1_3: std_logic;
signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
signal wcount_4: std_logic;
signal wcount_5: std_logic;
- signal co2_2: std_logic;
+ signal co2_3: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_2: std_logic;
signal full_cmp_clr: std_logic;
signal full_cmp_set: std_logic;
signal full_d: std_logic;
attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is "";
attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
attribute GSR of FF_61 : label is "ENABLED";
attribute GSR of FF_60 : label is "ENABLED";
attribute GSR of FF_59 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t12: AND2
+ AND2_t16: AND2
port map (A=>WrEn, B=>invout_1, Z=>wren_i);
INV_1: INV
port map (A=>full_i, Z=>invout_1);
- AND2_t11: AND2
+ AND2_t15: AND2
port map (A=>RdEn, B=>invout_0, Z=>rden_i);
INV_0: INV
port map (A=>empty_i, Z=>invout_0);
- OR2_t10: OR2
+ OR2_t14: OR2
port map (A=>Reset, B=>RPReset, Z=>rRst);
- XOR2_t9: XOR2
+ XOR2_t13: XOR2
port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
- XOR2_t8: XOR2
+ XOR2_t12: XOR2
port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
- XOR2_t7: XOR2
+ XOR2_t11: XOR2
port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
- XOR2_t6: XOR2
+ XOR2_t10: XOR2
port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
- XOR2_t5: XOR2
+ XOR2_t9: XOR2
port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
- XOR2_t4: XOR2
+ XOR2_t8: XOR2
port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
- XOR2_t3: XOR2
+ XOR2_t7: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t6: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t5: XOR2
port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
- XOR2_t2: XOR2
+ XOR2_t4: XOR2
port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
- XOR2_t1: XOR2
+ XOR2_t3: XOR2
port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
- XOR2_t0: XOR2
+ XOR2_t2: XOR2
port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+ XOR2_t1: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ LUT4_18: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_17: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_16: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_15: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
LUT4_13: ROM16X1A
generic map (initval=> X"6996")
port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_gcount_r26,
- DO0=>w_g2b_xor_cluster_0);
+ AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3);
LUT4_12: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r5);
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2);
LUT4_11: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4);
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1);
LUT4_10: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2);
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0);
LUT4_9: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
- AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1);
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_gcount_w26,
+ DO0=>r_g2b_xor_cluster_0);
LUT4_8: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0);
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w5);
LUT4_7: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
- AD1=>r_gcount_w23, AD0=>r_gcount_w24,
- DO0=>r_g2b_xor_cluster_0);
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4);
LUT4_6: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w3);
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2);
LUT4_5: ROM16X1A
generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2);
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1);
LUT4_4: ROM16X1A
generic map (initval=> X"6996")
port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0);
+ AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0);
LUT4_3: ROM16X1A
generic map (initval=> X"0410")
- port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r26,
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28,
AD0=>scuba_vlo, DO0=>empty_cmp_set);
LUT4_2: ROM16X1A
generic map (initval=> X"1004")
- port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r26,
+ port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28,
AD0=>scuba_vlo, DO0=>empty_cmp_clr);
LUT4_1: ROM16X1A
generic map (initval=> X"0140")
- port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w24,
+ port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26,
AD0=>scuba_vlo, DO0=>full_cmp_set);
LUT4_0: ROM16X1A
generic map (initval=> X"4001")
- port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w24,
+ port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26,
AD0=>scuba_vlo, DO0=>full_cmp_clr);
pdp_ram_0_0_2: DP16KC
DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo,
ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
- ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>scuba_vlo, ADB9=>scuba_vlo,
+ ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
- DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10),
- DOB6=>Q(11), DOB7=>Q(12), DOB8=>open, DOB9=>Q(18),
- DOB10=>Q(19), DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27),
- DOB14=>Q(28), DOB15=>Q(29), DOB16=>Q(30), DOB17=>open);
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
+ DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10), DOB6=>Q(11),
+ DOB7=>Q(12), DOB8=>open, DOB9=>Q(18), DOB10=>Q(19),
+ DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27), DOB14=>Q(28),
+ DOB15=>Q(29), DOB16=>Q(30), DOB17=>open);
pdp_ram_0_1_1: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo,
ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
- ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>scuba_vlo, ADB9=>scuba_vlo,
+ ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
- DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14),
- DOB6=>Q(15), DOB7=>Q(16), DOB8=>open, DOB9=>Q(22),
- DOB10=>Q(23), DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31),
- DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>open);
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6),
+ DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15),
+ DOB7=>Q(16), DOB8=>open, DOB9=>Q(22), DOB10=>Q(23),
+ DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31), DOB14=>Q(32),
+ DOB15=>Q(33), DOB16=>Q(34), DOB17=>open);
pdp_ram_0_2_0: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
- ADA8=>scuba_vlo, ADA9=>scuba_vlo, ADA10=>scuba_vlo,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo,
ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo,
CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi,
CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
- ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>scuba_vlo, ADB9=>scuba_vlo,
+ ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
- OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
- CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8),
- DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>Q(17), DOB5=>open,
- DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>Q(26), DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>Q(35), DOB14=>open,
- DOB15=>open, DOB16=>open, DOB17=>open);
-
- FF_61: FD1P3BX
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(8), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>Q(17), DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>Q(26), DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>Q(35), DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ FF_81: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
Q=>wcount_0);
- FF_60: FD1P3DX
+ FF_80: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_1);
- FF_59: FD1P3DX
+ FF_79: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_2);
- FF_58: FD1P3DX
+ FF_78: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_3);
- FF_57: FD1P3DX
+ FF_77: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_4);
- FF_56: FD1P3DX
+ FF_76: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_5);
- FF_55: FD1P3DX
+ FF_75: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_6);
- FF_54: FD1P3DX
+ FF_74: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_73: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_72: FD1P3DX
port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_0);
- FF_53: FD1P3DX
+ FF_71: FD1P3DX
port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_1);
- FF_52: FD1P3DX
+ FF_70: FD1P3DX
port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_2);
- FF_51: FD1P3DX
+ FF_69: FD1P3DX
port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_3);
- FF_50: FD1P3DX
+ FF_68: FD1P3DX
port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_4);
- FF_49: FD1P3DX
+ FF_67: FD1P3DX
port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_5);
- FF_48: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ FF_66: FD1P3DX
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_6);
- FF_47: FD1P3DX
+ FF_65: FD1P3DX
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_64: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_63: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_0);
- FF_46: FD1P3DX
+ FF_62: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_1);
- FF_45: FD1P3DX
+ FF_61: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_2);
- FF_44: FD1P3DX
+ FF_60: FD1P3DX
port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_3);
- FF_43: FD1P3DX
+ FF_59: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_4);
- FF_42: FD1P3DX
+ FF_58: FD1P3DX
port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_5);
- FF_41: FD1P3DX
+ FF_57: FD1P3DX
port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_6);
- FF_40: FD1P3BX
+ FF_56: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_55: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_54: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
Q=>rcount_0);
- FF_39: FD1P3DX
+ FF_53: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_1);
- FF_38: FD1P3DX
+ FF_52: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_2);
- FF_37: FD1P3DX
+ FF_51: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_3);
- FF_36: FD1P3DX
+ FF_50: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_4);
- FF_35: FD1P3DX
+ FF_49: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_48: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_47: FD1P3DX
port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_0);
- FF_34: FD1P3DX
+ FF_46: FD1P3DX
port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_1);
- FF_33: FD1P3DX
+ FF_45: FD1P3DX
port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_2);
- FF_32: FD1P3DX
+ FF_44: FD1P3DX
port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_3);
- FF_31: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ FF_43: FD1P3DX
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_4);
- FF_30: FD1P3DX
+ FF_42: FD1P3DX
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_41: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_40: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_0);
- FF_29: FD1P3DX
+ FF_39: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_1);
- FF_28: FD1P3DX
+ FF_38: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_2);
- FF_27: FD1P3DX
+ FF_37: FD1P3DX
port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_3);
- FF_26: FD1P3DX
+ FF_36: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_4);
- FF_25: FD1S3DX
+ FF_35: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_34: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_33: FD1S3DX
port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
- FF_24: FD1S3DX
+ FF_32: FD1S3DX
port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
- FF_23: FD1S3DX
+ FF_31: FD1S3DX
port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
- FF_22: FD1S3DX
+ FF_30: FD1S3DX
port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
- FF_21: FD1S3DX
+ FF_29: FD1S3DX
port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
- FF_20: FD1S3DX
+ FF_28: FD1S3DX
port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
- FF_19: FD1S3DX
+ FF_27: FD1S3DX
port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
- FF_18: FD1S3DX
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_24: FD1S3DX
port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
- FF_17: FD1S3DX
+ FF_23: FD1S3DX
port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
- FF_16: FD1S3DX
+ FF_22: FD1S3DX
port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
- FF_15: FD1S3DX
+ FF_21: FD1S3DX
port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
- FF_14: FD1S3DX
+ FF_20: FD1S3DX
port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
- FF_13: FD1S3DX
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_17: FD1S3DX
port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r20);
- FF_12: FD1S3DX
+ FF_16: FD1S3DX
port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r21);
- FF_11: FD1S3DX
+ FF_15: FD1S3DX
port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r22);
- FF_10: FD1S3DX
+ FF_14: FD1S3DX
port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r23);
- FF_9: FD1S3DX
+ FF_13: FD1S3DX
port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r24);
- FF_8: FD1S3DX
+ FF_12: FD1S3DX
port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r25);
- FF_7: FD1S3DX
+ FF_11: FD1S3DX
port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r26);
- FF_6: FD1S3DX
+ FF_10: FD1S3DX
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_9: FD1S3DX
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_8: FD1S3DX
port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
- FF_5: FD1S3DX
+ FF_7: FD1S3DX
port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
- FF_4: FD1S3DX
+ FF_6: FD1S3DX
port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
- FF_3: FD1S3DX
+ FF_5: FD1S3DX
port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
- FF_2: FD1S3DX
+ FF_4: FD1S3DX
port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+ FF_3: FD1S3DX
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_2: FD1S3DX
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
FF_1: FD1S3BX
port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
NC0=>iwcount_4, NC1=>iwcount_5);
w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3,
- NC0=>iwcount_6, NC1=>open);
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4,
+ NC0=>iwcount_8, NC1=>open);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
NC0=>ircount_2, NC1=>ircount_3);
r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1,
- NC0=>ircount_4, NC1=>open);
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1,
+ NC0=>ircount_6, NC1=>open);
empty_cmp_ci_a: FADD2B
port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
empty_cmp_0: AGEB2
port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
- B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2);
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_2);
empty_cmp_1: AGEB2
port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co0_2, GE=>co1_2);
+ B1=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2);
empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c);
+ B1=>scuba_vlo, CI=>co2_2, GE=>empty_d_c);
a0: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
full_cmp_1: AGEB2
port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
- B1=>r_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3);
+ B1=>rcount_w1, CI=>co0_3, GE=>co1_3);
full_cmp_2: AGEB2
port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co1_3, GE=>co2_2);
+ B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3);
full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co2_3, GE=>co3_2);
+
+ full_cmp_4: AGEB2
port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co2_2, GE=>full_d_c);
+ B1=>scuba_vlo, CI=>co3_2, GE=>full_d_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
-- Gray EnCcoder
--
-----------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
entity Gray_Encoder is
generic (
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
entity level_to_pulse is
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
library work;
use work.nxyter_components.all;
RESET_IN : in std_logic;
-- Data Buffer FIFO
- FIFO_DATA_IN : std_logic_vector(31 downto 0);
- FIFO_WRITE_ENABLE_IN : std_logic;
- FIFO_READ_ENABLE_IN : std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ NEW_DATA_IN : in std_logic;
+
+ -- Control
+ FIFO_WRITE_ENABLE_IN : in std_logic;
+ FIFO_READ_ENABLE_IN : in std_logic;
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end nx_data_buffer;
architecture Behavioral of nx_data_buffer is
+ -- FIFO Input Handler
+ signal fifo_next_word : std_logic_vector(31 downto 0);
+ signal fifo_full : std_logic;
+ signal fifo_write_enable : std_logic;
+ signal fifo_fill : std_logic;
+
+ -- FIFO Read Handler
+ signal fifo_o : std_logic_vector(31 downto 0);
+ signal fifo_empty : std_logic;
+ signal fifo_read_start : std_logic;
+
+ signal fifo_read_enable : std_logic;
+ signal fifo_read_busy : std_logic;
+ signal fifo_no_data : std_logic;
+ signal fifo_read_done : std_logic;
+ signal fifo_data : std_logic_vector(31 downto 0);
+
+ signal fifo_read_enable_x : std_logic;
+ signal fifo_read_busy_x : std_logic;
+ signal fifo_no_data_x : std_logic;
+ signal fifo_read_done_x : std_logic;
+ signal fifo_data_x : std_logic_vector(31 downto 0);
+
+ type STATES is (S_IDLE,
+ S_NOP1,
+ S_NOP2,
+ S_READ_WORD
+ );
--- FIFO Handler
- signal fifo_o : std_logic_vector(31 downto 0);
- signal fifo_empty : std_logic;
- signal fifo_full : std_logic;
- signal fifo_read_enable : std_logic;
- signal fifo_write_enable : std_logic;
+ signal STATE, NEXT_STATE: STATES;
--- Slave Bus
+ -- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal register_fifo_status : std_logic_vector(31 downto 0);
signal register_write_enable : std_logic;
+ signal data_wait : std_logic;
+
begin
--------------------------------------------------------------------------------
--- FIFO Handler
--------------------------------------------------------------------------------
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= fifo_fill;
+ DEBUG_OUT(2) <= data_wait;
+ DEBUG_OUT(3) <= fifo_read_done;
+ DEBUG_OUT(4) <= fifo_read_busy;
+ DEBUG_OUT(5) <= fifo_write_enable;
+ DEBUG_OUT(6) <= fifo_full;
+ DEBUG_OUT(7) <= fifo_empty;
+ DEBUG_OUT(8) <= fifo_read_enable;
+ DEBUG_OUT(9) <= slv_ack_o;
+ DEBUG_OUT(10) <= fifo_no_data;
+ DEBUG_OUT(11) <= fifo_read_start;
+ DEBUG_OUT(15 downto 12) <= fifo_o(3 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- FIFO Input Handler
+ -----------------------------------------------------------------------------
+
+ -- Send data to FIFO
fifo_32_data_1: fifo_32_data
port map (
- Data => FIFO_DATA_IN,
+ Data => fifo_next_word,
Clock => CLK_IN,
WrEn => fifo_write_enable,
RdEn => fifo_read_enable,
Full => fifo_full
);
- PROC_FIFO_HANDLER: process(CLK_IN)
+ PROC_FIFO_WRITE_HANDLER: process(CLK_IN)
begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- fifo_write_enable <= '0';
- fifo_read_enable <= '0';
+ if(rising_edge(CLK_IN)) then
+ if(RESET_IN = '1') then
+ fifo_write_enable <= '0';
+ fifo_fill <= '0';
else
- fifo_write_enable <= '1';
- fifo_read_enable <= '1';
+ fifo_write_enable <= '0';
+ fifo_next_word <= x"deadbeef";
+
+ if (NEW_DATA_IN = '1' and fifo_fill = '1') then
+ fifo_next_word <= DATA_IN;
+ fifo_write_enable <= '1';
+ end if;
- if (fifo_full = '1'
- or FIFO_WRITE_ENABLE_IN = '0'
- or register_write_enable <= '0') then
- fifo_write_enable <= '0';
+ if (fifo_empty = '1') then
+ fifo_fill <= '1';
end if;
- if (fifo_empty = '1' or FIFO_READ_ENABLE_IN = '0') then
- fifo_read_enable <= '0';
+ if (fifo_full = '1') then
+ fifo_fill <= '0';
end if;
-
end if;
end if;
- end process PROC_FIFO_HANDLER;
+ end process PROC_FIFO_WRITE_HANDLER;
+
+ -----------------------------------------------------------------------------
+ -- FIFO Output Handler
+ -----------------------------------------------------------------------------
+
+ PROC_FIFO_READ_TRANSFER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ fifo_read_enable <= '0';
+ fifo_read_busy <= '0';
+ fifo_data <= (others => '0');
+ fifo_read_done <= '0';
+ fifo_no_data <= '1';
+ STATE <= S_IDLE;
+ else
+ fifo_read_enable <= fifo_read_enable_x;
+ fifo_read_busy <= fifo_read_busy_x;
+ fifo_data <= fifo_data_x;
+ fifo_read_done <= fifo_read_done_x;
+ fifo_no_data <= fifo_no_data_x;
+ STATE <= NEXT_STATE;
+ end if;
+ end if;
+ end process PROC_FIFO_READ_TRANSFER;
+
+ PROC_FIFO_READ_WORD: process(STATE,
+ fifo_read_start,
+ fifo_empty
+ )
+ begin
+ fifo_read_busy_x <= '0';
+ fifo_no_data_x <= '0';
+ fifo_read_done_x <= '0';
+ fifo_data_x <= (others => '0');
+ fifo_read_enable_x <= '0';
+
+ case STATE is
+ when S_IDLE =>
+ if (fifo_read_start = '1') then
+ if (fifo_empty = '0') then
+ fifo_read_enable_x <= '1';
+ fifo_read_busy_x <= '1';
+ NEXT_STATE <= S_NOP1;
+ else
+ fifo_no_data_x <= '1';
+ fifo_read_done_x <= '1';
+ NEXT_STATE <= S_IDLE;
+ end if;
+ else
+ NEXT_STATE <= S_IDLE;
+ end if;
+
+ when S_NOP1 =>
+ fifo_read_busy_x <= '1';
+ NEXT_STATE <= S_NOP2;
+
+ when S_NOP2 =>
+ fifo_read_busy_x <= '1';
+ NEXT_STATE <= S_READ_WORD;
+
+ when S_READ_WORD =>
+ fifo_read_busy_x <= '0';
+ fifo_data_x <= fifo_o;
+ fifo_read_done_x <= '1';
+ NEXT_STATE <= S_IDLE;
+
+ end case;
+
+ end process PROC_FIFO_READ_WORD;
--------------------------------------------------------------------------------
--- Slave Bus Slow Control
--------------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- Slave Bus Slow Control
+ -----------------------------------------------------------------------------
register_fifo_status(0) <= fifo_write_enable;
register_fifo_status(1) <= fifo_full;
register_fifo_status(7 downto 6) <= (others => '0');
register_fifo_status(31 downto 8) <= (others => '0');
-
PROC_SLAVE_BUS: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
register_write_enable <= '0';
+
+ fifo_read_start <= '0';
+ data_wait <= '0';
else
slv_data_out_o <= (others => '0');
- slv_ack_o <= '1';
+ slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- if (SLV_READ_IN = '1') then
+ fifo_read_start <= '0';
+ data_wait <= '0';
+
+ if (data_wait = '1') then
+ if (fifo_read_done = '0') then
+ data_wait <= '1';
+ else
+ if (fifo_no_data = '0') then
+ slv_data_out_o <= fifo_data;
+ slv_ack_o <= '1';
+ else
+ slv_no_more_data_o <= '1';
+ slv_ack_o <= '0';
+ end if;
+ data_wait <= '0';
+ end if;
+
+ elsif (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
- when x"0000" => if (fifo_empty = '1') then
- slv_no_more_data_o <= '1';
- else
- slv_data_out_o <= fifo_o;
- slv_ack_o <= '1';
- end if;
- when x"0001" => slv_data_out_o <= register_fifo_status;
- when others => slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ when x"0000" =>
+ fifo_read_start <= '1';
+ data_wait <= '1';
+
+ when x"0001" =>
+ slv_data_out_o <= register_fifo_status;
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
end case;
+
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
- when x"0001" => register_write_enable <= SLV_DATA_IN(0);
- slv_ack_o <= '1';
- when others => slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ when x"0001" =>
+ register_write_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end case;
+
else
slv_ack_o <= '0';
end if;
end process PROC_I2C_MASTER_TRANSFER;\r
\r
\r
- PROC_I2C_MASTER: process(STATE)\r
+ PROC_I2C_MASTER: process(STATE,\r
+ i2c_start,\r
+ startstop_done,\r
+ read_seq_ctr,\r
+ sendbyte_done,\r
+ sendbyte_ack,\r
+ readbyte_done,\r
+ startstop_done)\r
\r
begin\r
-- Defaults\r
end if;\r
end process PROC_READ_BYTE_TRANSFER; \r
\r
- PROC_READ_BYTE: process(STATE)\r
+ PROC_READ_BYTE: process(STATE,\r
+ START_IN,\r
+ wait_timer_done,\r
+ bit_ctr\r
+ )\r
begin \r
sda_o <= '1';\r
scl_o <= '1';\r
end if;\r
end process PROC_SEND_BYTE_TRANSFER; \r
\r
- PROC_SEND_BYTE: process(STATE)\r
+ PROC_SEND_BYTE: process(STATE,\r
+ START_IN,\r
+ wait_timer_done,\r
+ bit_ctr\r
+ )\r
begin \r
sda_o <= '1';\r
scl_o <= '1';\r
end if;\r
end process PROC_START_STOP_TRANSFER;\r
\r
- PROC_START_STOP: process(STATE)\r
+ PROC_START_STOP: process(STATE,\r
+ START_IN,\r
+ SELECT_IN,\r
+ wait_timer_done\r
+ )\r
begin\r
sda_o <= '1';\r
scl_o <= '1';\r
end if;\r
end process PROC_TIMER_TRANSFER;\r
\r
- PROC_TIMER: process(STATE)\r
+ PROC_TIMER: process(STATE,\r
+ TIMER_START_IN,\r
+ timer_ctr\r
+ )\r
begin \r
\r
timer_done_o_x <= '0';\r
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.nxyter_components.all;\r
signal frame_clock_ctr_inc_l : std_logic;\r
signal frame_clock_ctr_inc : std_logic;\r
\r
-\r
-----------------------------------------------------------------------------\r
-- CLK_IN Domain\r
-----------------------------------------------------------------------------\r
\r
-- FIFO Output Handler\r
- type STATES is (S_IDLE,\r
- S_READ_FIFO\r
- );\r
-\r
- signal STATE, NEXT_STATE : STATES;\r
-\r
signal fifo_out : std_logic_vector(35 downto 0);\r
signal fifo_empty : std_logic;\r
- signal fifo_read_enable_x : std_logic;\r
+ signal fifo_empty_prev : std_logic;\r
signal fifo_read_enable : std_logic;\r
+ signal fifo_data_valid_x1 : std_logic;\r
+ signal fifo_data_valid_x : std_logic;\r
+ signal fifo_data_valid : std_logic;\r
+ \r
signal register_fifo_data_x : std_logic_vector(31 downto 0);\r
signal register_fifo_data : std_logic_vector(31 downto 0);\r
- signal fifo_new_frame_x : std_logic;\r
signal fifo_new_frame_o : std_logic;\r
\r
signal frame_clock_ctr_inc_o : std_logic;\r
signal frame_clock_ctr_inc_r : std_logic;\r
\r
begin\r
- \r
+\r
DEBUG_OUT(0) <= CLK_IN;\r
- \r
DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;\r
- DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT;\r
- DEBUG_OUT(3) <= NX_FRAME_SYNC_OUT;\r
- DEBUG_OUT(4) <= NX_NEW_FRAME_OUT;\r
- DEBUG_OUT(5) <= frame_clock_ctr_inc_o;\r
- DEBUG_OUT(6) <= frame_tag_o;\r
- DEBUG_OUT(7) <= '0';\r
- DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN(7 downto 0);\r
+ DEBUG_OUT(2) <= fifo_empty;\r
+ DEBUG_OUT(3) <= fifo_read_enable;\r
+ DEBUG_OUT(4) <= fifo_data_valid;\r
+ DEBUG_OUT(5) <= fifo_new_frame_o;\r
+ DEBUG_OUT(6) <= NX_NEW_FRAME_OUT;\r
+ DEBUG_OUT(7) <= frame_tag_o;\r
+ -- DEBUG_OUT(15 downto 8) <= NX_TIMESTAMP_IN;\r
+ DEBUG_OUT(15 downto 8) <= fifo_out(7 downto 0);\r
+ \r
+-- DEBUG_OUT(0) <= CLK_IN;\r
+-- \r
+-- DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN;\r
+-- DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT;\r
+-- DEBUG_OUT(3) <= NX_FRAME_SYNC_OUT;\r
+-- -- DEBUG_OUT(4) <= NX_NEW_FRAME_OUT;\r
+-- -- DEBUG_OUT(5) <= frame_clock_ctr_inc_o;\r
+-- -- DEBUG_OUT(6) <= frame_tag_o;\r
+-- -- DEBUG_OUT(7) <= '0';\r
+-- DEBUG_OUT(7 downto 4) <= fifo_out(3 downto 0);\r
+-- DEBUG_OUT(15 downto 8) <= fifo_out(34 downto 27);\r
\r
-----------------------------------------------------------------------------\r
-- Dual Clock FIFO 9bit to 36bit\r
Full => fifo_full\r
);\r
\r
- -- Write only in case FIFO is not full\r
- fifo_write_enable <= '0' when fifo_full = '1' else '1';\r
+ fifo_write_enable <= not RESET_IN;\r
\r
-----------------------------------------------------------------------------\r
-- FIFO Input Handler\r
-----------------------------------------------------------------------------\r
\r
-- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal\r
- -- fifo_skip_write\r
+ -- frame_clock_ctr_inc\r
PROC_FIFO_IN_HANDLER_SYNC: process(NX_TIMESTAMP_CLK_IN)\r
begin\r
if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
LEVEL_IN => frame_clock_ctr_inc_l,\r
PULSE_OUT => frame_clock_ctr_inc\r
);\r
-\r
+ \r
PROC_FRAME_CLOCK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)\r
begin\r
if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
else\r
frame_clock_ctr <= frame_clock_ctr + 1;\r
end if;\r
-\r
+ \r
end if;\r
end if;\r
end process PROC_FRAME_CLOCK_GENERATOR;\r
+\r
\r
-----------------------------------------------------------------------------\r
-- FIFO Output Handler and Sync FIFO\r
-----------------------------------------------------------------------------\r
\r
- PROC_FIFO_READ_TRANSFER: process (CLK_IN)\r
- begin \r
+ PROC_FIFO_READ_ENABLE: process(CLK_IN)\r
+ begin\r
if( rising_edge(CLK_IN) ) then\r
- if (RESET_IN = '1') then\r
- fifo_read_enable <= '0';\r
- fifo_new_frame_o <= '0';\r
- register_fifo_data <= (others => '0');\r
- STATE <= S_IDLE;\r
- register_fifo_data <= (others => '0');\r
+ if( RESET_IN = '1' ) then\r
+ fifo_empty_prev <= '0';\r
+ fifo_read_enable <= '0';\r
+ --fifo_data_valid_x1 <= '0';\r
+ fifo_data_valid_x <= '0';\r
+ fifo_data_valid <= '0';\r
else\r
- fifo_read_enable <= fifo_read_enable_x;\r
- fifo_new_frame_o <= fifo_new_frame_x;\r
- register_fifo_data <= register_fifo_data_x;\r
- STATE <= NEXT_STATE;\r
+ if (fifo_empty = '0' and fifo_empty_prev = '1') then\r
+ fifo_read_enable <= '1';\r
+ else\r
+ fifo_read_enable <= '0';\r
+ end if;\r
+ fifo_empty_prev <= fifo_empty; \r
+ fifo_data_valid_x <= fifo_read_enable;\r
+ --fifo_data_valid_x <= fifo_data_valid_x1; \r
+ fifo_data_valid <= fifo_data_valid_x;\r
end if;\r
end if;\r
- end process PROC_FIFO_READ_TRANSFER;\r
-\r
- -- Read only in case FIFO is not empty\r
- PROC_FIFO_READ: process(STATE)\r
-\r
- variable frame_tag : std_logic_vector(3 downto 0);\r
+ end process PROC_FIFO_READ_ENABLE;\r
+ \r
+ -- Read only in case FIFO is not empty, i.e. data_valid is set\r
+ PROC_FIFO_READ: process(CLK_IN)\r
\r
+ variable frame_tag : std_logic_vector(3 downto 0);\r
+ variable frame_data : std_logic_vector(31 downto 0);\r
+ \r
begin\r
- fifo_read_enable_x <= '0';\r
- fifo_new_frame_x <= '0';\r
- register_fifo_data_x <= register_fifo_data;\r
+ \r
+ frame_tag := fifo_out( 8) & fifo_out(17) &\r
+ fifo_out(26) & fifo_out(35);\r
\r
- frame_tag := fifo_out(35) & fifo_out(26) &\r
- fifo_out(17) & fifo_out(8);\r
+ frame_data := fifo_out( 7 downto 0) & fifo_out(16 downto 9) &\r
+ fifo_out(25 downto 18) & fifo_out(34 downto 27);\r
\r
- case STATE is\r
+ if( rising_edge(CLK_IN) ) then\r
+ if (RESET_IN = '1') then\r
+ fifo_new_frame_o <= '0';\r
+ register_fifo_data <= (others => '0');\r
+ else\r
+ fifo_new_frame_o <= '0';\r
+ register_fifo_data <= x"deadbeef";\r
+\r
+ if (fifo_data_valid = '1') then\r
+\r
+ case frame_tag is\r
+\r
+ when "1000" =>\r
+ register_fifo_data(31 downto 24) <= fifo_out( 7 downto 0);\r
+ register_fifo_data(23 downto 16) <= fifo_out(16 downto 9);\r
+ register_fifo_data(15 downto 8) <= fifo_out(25 downto 18);\r
+ register_fifo_data( 7 downto 0) <= fifo_out(34 downto 27);\r
+ fifo_new_frame_o <= '1'; \r
+\r
+ when "0100" => \r
+ register_fifo_data(31 downto 24) <= fifo_out(16 downto 9);\r
+ register_fifo_data(23 downto 16) <= fifo_out(25 downto 18);\r
+ register_fifo_data(15 downto 8) <= fifo_out(34 downto 27);\r
+ register_fifo_data( 7 downto 0) <= fifo_out( 7 downto 0);\r
+ fifo_new_frame_o <= '1'; \r
+\r
+ when "0010" => \r
+ register_fifo_data(31 downto 24) <= fifo_out(25 downto 18);\r
+ register_fifo_data(23 downto 16) <= fifo_out(34 downto 27);\r
+ register_fifo_data(15 downto 8) <= fifo_out( 7 downto 0);\r
+ register_fifo_data( 7 downto 0) <= fifo_out(16 downto 9);\r
+ fifo_new_frame_o <= '1'; \r
+\r
+ when "0001" => \r
+ register_fifo_data(31 downto 24) <= fifo_out(34 downto 27);\r
+ register_fifo_data(23 downto 16) <= fifo_out( 7 downto 0);\r
+ register_fifo_data(15 downto 8) <= fifo_out(16 downto 9);\r
+ register_fifo_data( 7 downto 0) <= fifo_out(25 downto 18);\r
+ fifo_new_frame_o <= '1'; \r
+\r
+ when others => null;\r
+ \r
+ end case;\r
\r
- when S_IDLE =>\r
- if (fifo_empty = '1') then\r
- NEXT_STATE <= S_IDLE;\r
- else\r
- fifo_read_enable_x <= '1';\r
- NEXT_STATE <= S_READ_FIFO;\r
end if;\r
- \r
- when S_READ_FIFO =>\r
- fifo_new_frame_x <= '1';\r
- case frame_tag is\r
- when "1000" =>\r
- register_fifo_data_x(31 downto 24) <= fifo_out(34 downto 27);\r
- register_fifo_data_x(23 downto 16) <= fifo_out(25 downto 18);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(16 downto 9);\r
- register_fifo_data_x( 7 downto 0) <= fifo_out( 7 downto 0);\r
- when "0100" => \r
- register_fifo_data_x(31 downto 24) <= fifo_out( 7 downto 0);\r
- register_fifo_data_x(23 downto 16) <= fifo_out(34 downto 27);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(25 downto 18);\r
- register_fifo_data_x( 7 downto 0) <= fifo_out(16 downto 9);\r
- when "0010" => \r
- register_fifo_data_x(31 downto 24) <= fifo_out(16 downto 9);\r
- register_fifo_data_x(23 downto 16) <= fifo_out( 7 downto 0);\r
- register_fifo_data_x(15 downto 8) <= fifo_out(34 downto 27);\r
- register_fifo_data_x( 7 downto 0) <= fifo_out(25 downto 18);\r
- when "0001" => \r
- register_fifo_data_x(31 downto 24) <= fifo_out(25 downto 18);\r
- register_fifo_data_x(23 downto 16) <= fifo_out(16 downto 9);\r
- register_fifo_data_x(15 downto 8) <= fifo_out( 7 downto 0);\r
- register_fifo_data_x( 7 downto 0) <= fifo_out(34 downto 27);\r
-\r
- when others =>\r
- register_fifo_data_x <= (others => '1');\r
- fifo_new_frame_x <= '0';\r
- end case;\r
- NEXT_STATE <= S_IDLE;\r
- \r
- when others => null;\r
- end case;\r
+ end if;\r
+ end if;\r
end process PROC_FIFO_READ;\r
\r
\r
-- Frame Sync process\r
PROC_SYNC_TO_NX_FRAME_TRANSFER: process(CLK_IN)\r
begin\r
- \r
-\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
rs_sync_set <= '0';\r
end if;\r
end process PROC_SYNC_TO_NX_FRAME_TRANSFER;\r
\r
- PROC_SYNC_TO_NX_FRAME: process(STATE_SYNC)\r
+ PROC_SYNC_TO_NX_FRAME: process(STATE_SYNC,\r
+ fifo_out(35),\r
+ fifo_out(26),\r
+ fifo_out(17),\r
+ fifo_out(8),\r
+ fifo_new_frame_o,\r
+ register_fifo_data,\r
+ frame_sync_wait_done\r
+ )\r
\r
variable fifo_tag_given : std_logic_vector(3 downto 0);\r
\r
\r
fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
fifo_out(17) & fifo_out(8);\r
- \r
+\r
case STATE_SYNC is\r
- \r
when S_SYNC_CHECK =>\r
- case register_fifo_data is\r
- when x"7f7f7f06" =>\r
- rs_sync_set_x <= '1';\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
-\r
- when x"067f7f7f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ if (fifo_new_frame_o = '1') then \r
+ case register_fifo_data is\r
+ when x"7f7f7f06" =>\r
+ rs_sync_set_x <= '1';\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+\r
+ when x"067f7f7f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
\r
- when x"7f067f7f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ when x"7f067f7f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
\r
- when x"7f7f067f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
+ when x"7f7f067f" =>\r
+ NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
\r
- when others =>\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+ when others =>\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
\r
- end case;\r
+ end case;\r
+ else\r
+ NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
+ end if;\r
\r
when S_SYNC_RESYNC =>\r
rs_sync_reset_x <= '1';\r
-- TRBNet Slave Bus\r
-----------------------------------------------------------------------------\r
\r
- register_fifo_status(0) <= fifo_write_enable;\r
- register_fifo_status(1) <= fifo_full;\r
- register_fifo_status(3 downto 2) <= (others => '0');\r
- register_fifo_status(4) <= fifo_read_enable;\r
- register_fifo_status(5) <= fifo_empty;\r
- register_fifo_status(7 downto 6) <= (others => '0');\r
- register_fifo_status(15 downto 8) <= (others => '0');\r
+ register_fifo_status(0) <= fifo_full;\r
+ register_fifo_status(1) <= fifo_empty;\r
+ register_fifo_status(2) <= fifo_data_valid;\r
+ register_fifo_status(3) <= fifo_new_frame_o;\r
+ register_fifo_status(15 downto 4) <= (others => '0');\r
register_fifo_status(23 downto 16) <= nx_frame_resync_ctr;\r
register_fifo_status(30 downto 24) <= (others => '0');\r
register_fifo_status(31) <= nx_frame_synced_o;\r
\r
NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
NX_TIMESTAMP_OUT <= register_fifo_data;\r
- NX_NEW_FRAME_OUT <= fifo_new_frame_o;\r
+ NX_NEW_FRAME_OUT <= '1' when (fifo_new_frame_o = '1'\r
+ and register_fifo_data /= x"7f7f7f06"\r
+ )\r
+ else '0';\r
\r
end Behavioral;\r
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.nxyter_components.all;\r
\r
signal timestamp_n : std_logic_vector(7 downto 0);\r
signal timestamp_g : std_logic_vector(7 downto 0);\r
- signal timestamp : unsigned(31 downto 0);\r
signal counter : unsigned(1 downto 0);\r
- \r
-begin\r
+ signal counter2 : unsigned(3 downto 0);\r
+ signal counter3 : unsigned(1 downto 0);\r
\r
- timestamp <= x"7f7f7f06";\r
+begin\r
\r
PROC_NX_TIMESTAMP: process(CLK_IN)\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
timestamp_n <= (others => '0');\r
--- timestamp <= (others => '0');\r
counter <= (others => '0');\r
+ counter2 <= (others => '0');\r
+ counter3 <= (others => '0');\r
+\r
else\r
- case counter is\r
- -- when "00" => timestamp_n <= timestamp(7 downto 0);\r
- -- when "01" => timestamp_n <= timestamp(15 downto 8);\r
- -- when "10" => timestamp_n <= timestamp(23 downto 16);\r
- -- when "11" => timestamp_n <= timestamp(31 downto 24);\r
- -- timestamp <= timestamp + 1;\r
- when "00" => timestamp_n <= timestamp(7 downto 0);\r
- when "01" => timestamp_n <= timestamp(15 downto 8);\r
- when "10" => timestamp_n <= timestamp(23 downto 16);\r
- when "11" => timestamp_n <= timestamp(31 downto 24);\r
\r
- when others => null; \r
- end case;\r
+ if (counter3 /= 0) then\r
+ case counter is\r
+ when "11" => timestamp_n <= x"06";\r
+ counter3 <= counter3 + 1;\r
+\r
+ when "10" => timestamp_n <= x"7f";\r
+\r
+ when "01" => timestamp_n <= x"7f";\r
+\r
+ when "00" => timestamp_n <= x"7f";\r
+ end case;\r
+\r
+ else\r
+ case counter is\r
+ when "11" =>\r
+ timestamp_n(7) <= '0';\r
+ timestamp_n(6 downto 4) <= (others => '0');\r
+ timestamp_n(3 downto 0) <= counter2;\r
+ counter3 <= counter3 + 1;\r
+ \r
+ when "10" =>\r
+ timestamp_n(7) <= '0';\r
+ timestamp_n(6 downto 4) <= (others => '0');\r
+ timestamp_n(3 downto 0) <= counter2;\r
+ \r
+ when "01" =>\r
+ timestamp_n(7) <= '0';\r
+ timestamp_n(6 downto 4) <= (others => '0');\r
+ timestamp_n(3 downto 0) <= counter2;\r
+\r
+ when "00" =>\r
+ timestamp_n(7) <= '0';\r
+ timestamp_n(6 downto 4) <= (others => '0');\r
+ timestamp_n(3 downto 0) <= counter2;\r
+\r
+ end case;\r
+ counter2 <= counter2 + 1;\r
+ end if;\r
\r
- counter <= counter + 1;\r
+ counter <= counter + 1;\r
end if;\r
end if; \r
end process PROC_NX_TIMESTAMP;\r
-- GRAY_OUT => timestamp_g \r
-- );\r
-- \r
- timestamp_g <= timestamp_n;\r
+-- timestamp_g <= timestamp_n;\r
\r
\r
-- Output Signals\r
- TIMESTAMP_OUT <= timestamp_g;\r
+ TIMESTAMP_OUT <= timestamp_n;\r
CLK128_OUT <= CLK_IN;\r
\r
end Behavioral;\r
signal nx_ts_reset_o : std_logic;
signal nx_frame_clock_o : std_logic;
signal nx_frame_sync_o : std_logic;
-
-
+
-- Timestamp Handlers
signal nx_timestamp_o : std_logic_vector(31 downto 0);
+ signal nx_new_frame : std_logic;
+
+ -- FPGA Timestamp
+ signal timestamp_latched : unsigned(13 downto 0);
+ signal nx_timestamp_sync_o : std_logic;
+ -- Testpulse Generator
+ signal nx_testpulse_o : std_logic;
begin
-------------------------------------------------------------------------------
-- DEBUG
-------------------------------------------------------------------------------
--- DEBUG_LINE_OUT(0) <= CLK_IN;
--- DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
--- DEBUG_LINE_OUT(2) <= ADC_SC_CLK32_OUT;
--- DEBUG_LINE_OUT(3) <= ADC_FCLK_IN;
+ DEBUG_LINE_OUT(0) <= CLK_IN;
+ DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
+ DEBUG_LINE_OUT(2) <= NX_RESET_OUT;
+ DEBUG_LINE_OUT(3) <= NX_TESTPULSE_OUT;
+ DEBUG_LINE_OUT(4) <= clk_256_o;
+-- DEBUG_LINE_OUT(5) <= clk_lock;
+
+
+
+
-- DEBUG_LINE_OUT(4) <= ADC_DCLK_IN;
-- DEBUG_LINE_OUT(5) <= ADC_NX_IN;
-- DEBUG_LINE_OUT(6) <= ADC_A_IN;
--
-- DEBUG_LINE_OUT(15 downto 9) <= (others => '0');
--
--- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
--- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
+ DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
-- DEBUG_LINE_OUT(8) <= i2c_sda_o;
-- DEBUG_LINE_OUT(9) <= i2c_sda_i;
-- DEBUG_LINE_OUT(10) <= i2c_scl_o;
-- DEBUG_LINE_OUT(4) <= i2c_reg_reset_o;
--
-- DEBUG_LINE_OUT(5 downto 5) <= (others => '0');
-
+
-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------
);
NX_CLK256A_OUT <= clk_256_o;
- NX_TESTPULSE_OUT <= '0';
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 5,
+ PORT_NUMBER => 6,
PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
1 => x"0040", -- I2C master
2 => x"0100", -- Timestamp Fifo
3 => x"0200", -- Data Buffer
4 => x"0060", -- SPI Master
+ 5 => x"0080", -- Trigger Generator
others => x"0000"),
PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
1 => 0, -- I2C master
2 => 1, -- Timestamp Fifo
3 => 1, -- Data Buffer
- 4 => 0, -- Master
+ 4 => 0, -- SPI Master
+ 5 => 0, -- Trigger Generator
others => 0)
)
port map(
BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4),
BUS_UNKNOWN_ADDR_IN(4) => slv_unknown_addr(4),
+ -- Trigger Generator
+ BUS_READ_ENABLE_OUT(5) => slv_read(5),
+ BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
+ BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
+ BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => open,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATAREADY_IN(5) => slv_ack(5),
+ BUS_WRITE_ACK_IN(5) => slv_ack(5),
+ BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5),
+ BUS_UNKNOWN_ADDR_IN(5) => slv_unknown_addr(5),
+
---- SPI control registers
--BUS_READ_ENABLE_OUT(4) => slv_read(4),
--BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
I2C_SM_RESET_OUT => i2c_sm_reset_o,
I2C_REG_RESET_OUT => i2c_reg_reset_o,
NX_TS_RESET_OUT => nx_ts_reset_o,
- -- DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8)
+ --DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8)
DEBUG_OUT => open
);
DEBUG_OUT => open
);
--------------------------------------------------------------------------------
--- SPI master block to access the ADC
--------------------------------------------------------------------------------
-
- adc_spi_master_1: adc_spi_master
- generic map (
- SPI_SPEED => x"32"
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- SCLK_OUT => SPI_SCLK_OUT,
- SDIO_INOUT => SPI_SDIO_INOUT,
- CSB_OUT => SPI_CSB_OUT,
- SLV_READ_IN => slv_read(4),
- SLV_WRITE_IN => slv_write(4),
- SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
- SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
- SLV_ACK_OUT => slv_ack(4),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
- DEBUG_OUT => DEBUG_LINE_OUT
- -- DEBUG_OUT => open
- );
-
-------------------------------------------------------------------------------
-- nXyter TimeStamp Read
-------------------------------------------------------------------------------
NX_FRAME_CLOCK_OUT => nx_frame_clock_o,
NX_FRAME_SYNC_OUT => nx_frame_sync_o,
NX_TIMESTAMP_OUT => nx_timestamp_o,
- NX_NEW_FRAME_OUT => open,
+ NX_NEW_FRAME_OUT => nx_new_frame,
SLV_READ_IN => slv_read(2),
SLV_WRITE_IN => slv_write(2),
SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
- -- DEBUG_OUT => DEBUG_LINE_OUT
+ --DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(7 downto 0)
+ DEBUG_OUT => open
+ );
+
+
+-------------------------------------------------------------------------------
+-- Timestamp Decoder and Valid Data Filter
+-------------------------------------------------------------------------------
+
+ nx_timestamp_decode_1: nx_timestamp_decode
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_NEW_FRAME_IN => nx_new_frame,
+ NX_TIMESTAMP_IN => nx_timestamp_o,
+ TIMESTAMP_DATA_OUT => open,
+ TIMESTAMP_VALID_OUT => open,
+
+ -- DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
-
+
+
-------------------------------------------------------------------------------
-- Data Buffer FIFO
-------------------------------------------------------------------------------
- nx_data_buffer_1: nx_data_buffer
+
+
+ nx_data_buffer_2: nx_data_buffer
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
-
- FIFO_DATA_IN => nx_timestamp_o,
+ DATA_IN => nx_timestamp_o,
+ NEW_DATA_IN => nx_new_frame,
+
FIFO_WRITE_ENABLE_IN => '1',
FIFO_READ_ENABLE_IN => '1',
-
+
SLV_READ_IN => slv_read(3),
SLV_WRITE_IN => slv_write(3),
SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
SLV_ACK_OUT => slv_ack(3),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3)
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+
+ -- DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
);
+-------------------------------------------------------------------------------
+-- SPI master block to access the ADC
+-------------------------------------------------------------------------------
+
+ adc_spi_master_1: adc_spi_master
+ generic map (
+ SPI_SPEED => x"32"
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SCLK_OUT => SPI_SCLK_OUT,
+ SDIO_INOUT => SPI_SDIO_INOUT,
+ CSB_OUT => SPI_CSB_OUT,
+ SLV_READ_IN => slv_read(4),
+ SLV_WRITE_IN => slv_write(4),
+ SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
+ SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
+ SLV_ACK_OUT => slv_ack(4),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
+ -- DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
+ );
-------------------------------------------------------------------------------
--- nXyter Signals
+-- FPGA Timestamp
-------------------------------------------------------------------------------
- NX_RESET_OUT <= not nx_ts_reset_o;
+
+ nx_fpga_timestamp_1: nx_fpga_timestamp
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TIMESTAMP_CLK_IN => clk_256_o,
+ TIMESTAMP_SYNC_IN => RESET_IN,
+ LATCH_IN => nx_testpulse_o,
+ TIMESTAMP_OUT => timestamp_latched,
+ NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync_o,
+ SLV_READ_IN => open,
+ SLV_WRITE_IN => open,
+ SLV_DATA_OUT => open,
+ SLV_DATA_IN => open,
+ SLV_ACK_OUT => open,
+ SLV_NO_MORE_DATA_OUT => open,
+ SLV_UNKNOWN_ADDR_OUT => open,
+ -- DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
+ );
-------------------------------------------------------------------------------
+-- NX Trigger Generator
+-------------------------------------------------------------------------------
+
+ nx_trigger_generator_1: nx_trigger_generator
+ generic map (
+ TRIGGER_SPEED => x"ffff"
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_OUT => nx_testpulse_o,
+ SLV_READ_IN => slv_read(5),
+ SLV_WRITE_IN => slv_write(5),
+ SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
+ SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
+ SLV_ACK_OUT => slv_ack(5),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
+ -- DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
+ );
+
+
+-------------------------------------------------------------------------------
+-- nXyter Signals
+-------------------------------------------------------------------------------
+ NX_RESET_OUT <= '1';--nx_ts_reset_o;
+ NX_TESTPULSE_OUT <= nx_testpulse_o;
+-------------------------------------------------------------------------------
-- I2C Signals
-------------------------------------------------------------------------------
ADC_SC_CLK32_OUT <= nx_frame_clock_o;
+
+
+
+
+
-------------------------------------------------------------------------------
-- END
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
package nxyter_components is
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- FIFO_DATA_IN : std_logic_vector(31 downto 0);
- FIFO_WRITE_ENABLE_IN : std_logic;
- FIFO_READ_ENABLE_IN : std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ NEW_DATA_IN : in std_logic;
+ FIFO_WRITE_ENABLE_IN : in std_logic;
+ FIFO_READ_ENABLE_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
+component nx_timestamp_decode
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NX_NEW_FRAME_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector(31 downto 0);
+ TIMESTAMP_DATA_OUT : out std_logic_vector(27 downto 0);
+ TIMESTAMP_VALID_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
component pll_nx_clk256
port (
LOCK : out std_logic);
end component;
+component nx_fpga_timestamp
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMESTAMP_CLK_IN : in std_logic;
+ TIMESTAMP_SYNC_IN : in std_logic;
+ LATCH_IN : in std_logic;
+ TIMESTAMP_OUT : out unsigned(13 downto 0);
+ NX_TIMESTAMP_SYNC_OUT : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+component nx_trigger_generator
+ generic (
+ TRIGGER_SPEED : unsigned(15 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TRIGGER_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
-------------------------------------------------------------------------------
-- Misc Tools
-------------------------------------------------------------------------------
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
\r
library work;\r
use work.nxyter_components.all;\r
end if;\r
end process PROC_I2C_SM_RESET_TRANSFER;\r
\r
- PROC_I2C_SM_RESET: process(STATE)\r
+ PROC_I2C_SM_RESET: process(STATE,\r
+ i2c_sm_reset_start,\r
+ i2c_reg_reset_start,\r
+ nx_ts_reset_start,\r
+ wait_timer_done\r
+ )\r
begin\r
i2c_sm_reset_o <= '0';\r
i2c_reg_reset_o <= '0';\r
jspc29 / trb3.git / commitdiff