med_sync_control: Add reset sync for RXI/TXI clock

Previously, the reset_i signal (synchronous to the system clock) was
used for rx_control and tx_control.

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index 6df14ad0658c2596ed33df0ad519e64e615f6bfb..a692953c6cf471c6599a31eacfd4aa7437e66da2 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -61,6 +61,11 @@ end entity;
 
 architecture med_sync_control_arch of med_sync_control is
 
+signal reset_rxi_meta : std_logic := '0';
+signal reset_rxi : std_logic := '0';
+signal reset_txi_meta : std_logic := '0';
+signal reset_txi : std_logic := '0';
+
 signal rx_fsm_state : std_logic_vector(3 downto 0);
 signal tx_fsm_state : std_logic_vector(3 downto 0);
 signal wa_position_rx : std_logic_vector(3 downto 0);
@@ -114,6 +119,28 @@ signal quad_rst_i             : std_logic;
 
 begin
 
+process (reset_i, CLK_RXI) is
+begin
+  if reset_i = '1' then
+    reset_rxi_meta <= '1';
+    reset_rxi <= '1';
+  elsif rising_edge(CLK_RXI) then
+    reset_rxi_meta <= '0';
+    reset_rxi <= reset_rxi_meta;
+  end if;
+end process;
+
+process (reset_i, CLK_TXI) is
+begin
+  if reset_i = '1' then
+    reset_txi_meta <= '1';
+    reset_txi <= '1';
+  elsif rising_edge(CLK_TXI) then
+    reset_txi_meta <= '0';
+    reset_txi <= reset_txi_meta;
+  end if;
+end process;
+
 rst_n_tx  <=       not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1)
               else not (CLEAR or make_link_reset_real_i or RESET);
 
@@ -230,7 +257,7 @@ THE_TX : tx_control
   port map(
     CLK_200                => CLK_TXI,
     CLK_100                => CLK_SYS,
-    RESET_IN               => reset_i,
+    RESET_IN               => reset_txi,
 
     TX_DATA_IN             => MEDIA_INT2MED.data,
     TX_PACKET_NUMBER_IN    => MEDIA_INT2MED.packet_num,
@@ -266,7 +293,7 @@ THE_RX_CONTROL : rx_control
   port map(
     CLK_200                        => CLK_RXI,
     CLK_100                        => CLK_SYS,
-    RESET_IN                       => reset_i,
+    RESET_IN                       => reset_rxi,
 
     RX_DATA_OUT                    => media_med2int_i.data,
     RX_PACKET_NUMBER_OUT           => media_med2int_i.packet_num,
@@ -302,20 +329,20 @@ MEDIA_MED2INT <= media_med2int_i;
 THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync
 port map(
   CLK_A_IN        => CLK_RXI,
-  RESET_A_IN      => reset_i,
+  RESET_A_IN      => reset_rxi,
   PULSE_A_IN      => request_retr_i,
   CLK_B_IN        => CLK_TXI,
-  RESET_B_IN      => reset_i,
+  RESET_B_IN      => reset_txi,
   PULSE_B_OUT     => request_retr_tx
 );
 
 THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync
 port map(
   CLK_A_IN        => CLK_RXI,
-  RESET_A_IN      => reset_i,
+  RESET_A_IN      => reset_rxi,
   PULSE_A_IN      => start_retr_i,
   CLK_B_IN        => CLK_TXI,
-  RESET_B_IN      => reset_i,
+  RESET_B_IN      => reset_txi,
   PULSE_B_OUT     => start_retr_tx
 );