& 27 -- 24 & & Type \\
& 23 -- 0 & & Information \\
\hline
-INFO & 31 -- 28 & 0x2 & Configuration of the device. Information about ADC status. Only sent in trigger type 0xe events. Config words are sent for each ADC, the corresponding device is given in a HDR word.\\
+INFO & 31 -- 28 & 0x2 & Configuration of the device. Information about ADC status. Only sent in trigger type 0xe events. Configuration words are sent for each ADC, the corresponding device is given in a HDR word.\\
& 27 -- 20 & & Word type, see separate table\\
& 19 -- 0 & & Data \\
\hline
0x03 & 17 -- 0 & Trigger threshold \\
0x04 & 17 -- 0 & Readout threshold \\
0x05 & 7 -- 0 & Number of ADC samples to sum before storing in Fifo \\
- & 11 -- 8 & Samples to average for baseline calculation (actual numer is 2**N of given value) \\
+ & 11 -- 8 & Samples to average for baseline calculation (actual number is 2**N of given value) \\
& 13 -- 12 & Number of blocks to process\\
0x06 & 7 -- 0 & Samples to sum before sending data (first block) \\
& 15 -- 8 & Number of sums to be sent (first block) \\
\clearpage
\subsection{SubSubEvent Format}
The read-out data-stream starts with a header word, that is present even if no data follows.
- If the event is active, memory words 0 to $n$ follow, where $n$ is the length specified when commiting.
+ If the event is active, memory words 0 to $n$ follow, where $n$ is the length specified when committing.
In case of an inactive event, the length indicator still shows $n$ but the ActiveEvent-bit is 0.
This allows you to check, whether the slow-control update have been successful.
Both share a common first word, containing the received running number as well as status- and the error-bits.
If indicated in the header, two additional words storing information to reconstruct the arrival time of this MBS data follow:
-In this case, the first additional word (2nd in stream) holds a timestamp with a granularity of 5~ns.
-The timestamp was reset by the arrival of the timing trigger belonging to the LVL1 trigger as indicated by the 3rd word in the data stream.
+In this case, the first additional word (2nd in stream) holds a time-stamp with a granularity of 5~ns.
+The time-stamp was reset by the arrival of the timing trigger belonging to the LVL1 trigger as indicated by the 3rd word in the data stream.
Observe that this information is only valid, if a timing trigger was received not more than 20~s before the arrival of the data word.
{\small
\quad MBSError & & 31 & MBS-Error bit (high-active)\\
\rowcolor{light-gray}
\textbf{Timestamp} & 1 & 0--31 & Time (in 5~ns steps) since timing trigger of event indicated in next word\\
- \textbf{LVL1Info} & 2 & & LVL1-Trigger information of timestamp \\
+ \textbf{LVL1Info} & 2 & & LVL1-Trigger information of time-stamp \\
\quad TriggerNumber& & 0--15 & Trigger number sent by CTS\\
\quad TriggerCode & & 16--23& Trigger code sent by CTS\\
\bottomrule
The bridge offers two high-level features:
it enables TRB3 installations to tunnel their complete ``TrbNet data stream'' via CBMNet and send it to the FLES..
-Data of all CBMNet and TrbNet frontends is therefore available from a common source and can be processed for online monitoring and analysis.
+Data of all CBMNet and TrbNet front-ends is therefore available from a common source and can be processed for online monitoring and analysis.
The bridge additionally provides the means to synchronise both networks, i.e. to achieve a fixed delay between two networks that remains during operation and after a restart of the DAQ.
\subsection{Synthesising the Bridge}
By default the bridge listens on the Streaming API Bus between hub and Gbe and ignores all data.
To active the uplink, set bit Listen of the ReadoutCtrl register (see XML-DB).
The bridge will now try to uplink TrbNet events via CBMNet.
-If the FLES invokes backpressure, the events are discarded and no pressure is put onto TrbNet.
+If the FLES invokes back-pressure, the events are discarded and no pressure is put onto TrbNet.
-By deselecting the EnableGBE bit in the ReadoutCtrl register, GBE does not receive data anymore and the possible CBMNet uplink rate will increase.
-Even in this configuration, the bridge refrains from forwarding backpressure into TrbNet.
+By deselecting the EnableGBE bit in the ReadoutCtrl register, GBE does not receive data any more and the possible CBMNet uplink rate will increase.
+Even in this configuration, the bridge refrains from forwarding back-pressure into TrbNet.
Thus, events still can get lost (around 1 to 10 ppm during for high data rates).
An unpacker for the CBMNet bridge is included into CbmRoot; this section is hence only included for completeness.
As shown in Figure \ref{fig:cbmnet_frame_header}, there are two types of frame headers \texttt{uint16\_t hdr}.
In both the MSB \texttt{(hdr>>15)\&1} indicates the last frame of a transaction, while \texttt{(hdr>>14)\&1} marks the start frame.
-Note, that both bits are set, iff the transaction consists of a single frame.
+Note, that both bits are set, if the transaction consists of a single frame.
\begin{itemize}
\item
The arrival time of this signal gives the means to synchronise the system and gives a $T_0$ for each event .
The reference time is also sampled in the 125~MHz CBMNet clock domain.
-Its leading edge triggers the storage of the CBMNet timestamp (1 word, incremented with each clock cycle), yielding a granularity of 8~ns.
-To increase the accuracy, the moment of timestamping is measured using TDC channel 3.
+Its leading edge triggers the storage of the CBMNet time-stamp (1 word, incremented with each clock cycle), yielding a granularity of 8~ns.
+To increase the accuracy, the moment of time-stamping is measured using TDC channel 3.
Hence, the accurate time is given by
\[
- T^\text{event}_\text{cbm} = 8\text{~ns} \cdot T^\text{timestamp}_\text{cbm} - (T^\text{ref}_\text{cbm} - T^\text{ref}_\text{trb}),
+ T^\text{event}_\text{cbm} = 8\text{~ns} \cdot T^\text{time-stamp}_\text{cbm} - (T^\text{ref}_\text{cbm} - T^\text{ref}_\text{trb}),
\]
-where $T^\text{timestamp}_\text{cbm}$ is given in the sync-module (2nd word), $T^\text{ref}_\text{cbm}$ is provided by TDC-channel 3 and $T^\text{ref}_\text{trb}$ by TDC-channel 0.
+where $T^\text{time-stamp}_\text{cbm}$ is given in the sync-module (2nd word), $T^\text{ref}_\text{cbm}$ is provided by TDC-channel 3 and $T^\text{ref}_\text{trb}$ by TDC-channel 0.
The difference between the two TDC measurements should be in the order of $16$~ns to $32$~ns.
In lab tests, the RMS jitter $j$ of the $T^\text{event}_\text{cbm}$ measurement was found the be $40\text{~ps} < j < 60\text{~ps}$.
The Sync-Module can be configured to receive any DLM (but DLM0 which is reserved for CBMNet purposes).
-After enabling the $i$-th bit in the DLMSenseMask (see XML-DB), the sync-module begins listening to the DLMs of type $i$ and store the arrival with with a CBMNet timestamp (see read-out format).
+After enabling the $i$-th bit in the DLMSenseMask (see XML-DB), the sync-module begins listening to the DLMs of type $i$ and store the arrival with with a CBMNet time-stamp (see read-out format).
Additionally a TDC hit is registers for any active DLM; this, however, should not be required when using the aforementioned approach based on the TrbNet reference time.
\subsubsection{Read-Out Format}
\item \texttt{(hdr >> 26) \& 0x3 == 0} -- \textsc{NoData}: section's length (incl. header): 4 bytes\\
The CBMNet link is not active, so no data follows.
\item \texttt{(hdr >> 26) \& 0x3 == 3} -- \textsc{ExtendedData}: section's length (incl. header): 44 bytes\\
- This type is transmitted for all timining-less triggers (i.e. status triggers). The header is followed by 10 words
+ This type is transmitted for all timing-less triggers (i.e. status triggers). The header is followed by 10 words
as shown in Table \ref{tab:cbmnet_sync_mod_rdo}.
\item \texttt{(hdr >> 26) \& 0x3 == 1} -- \textsc{ShortData}: section's length (incl. header): 20 bytes\\
All physics trigger include only a shortened version, i.e. the first four data words of the \textsc{ExtendedData} format (Timestamps \& Pulser Timestamp).
0 & & \textbf{Header} \\
& 1--0 & Epoch ID defined by: \\
& & \hspace{1em} 0x0: Incremented epoch \\
- & & \hspace{1em} 0x1: Preset via TrbNet slow control \\
- & & \hspace{1em} 0x2: Preset via CBMNet DCM \\
+ & & \hspace{1em} 0x1: Pre-set via TrbNet slow control \\
+ & & \hspace{1em} 0x2: Pre-set via CBMNet DCM \\
& 3 & Low, if slow control update was chosen and no update between last two DLM \\
& 7--4 & Barrel shifter position of CBMNet PHY (always 0 in default config) \\
& 23--8& Lower half-word of CBMNet pulser threshold (in clock cycles) \\
\subsection{VHDL}
\begin{description*}
- \item[Trb3 Vhdl]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trb3.git
- \item[TrbNet Vhdl]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trbnet.git
+ \item[Trb3 VHDL]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trb3.git
+ \item[TrbNet VHDL]~\\git clone git://jspc29.x-matter.uni-frankfurt.de/projects/trbnet.git
\end{description*}
\subsection{Software / Documentation}
\subsection{Additional Resources}
\begin{description*}
- \item[Dabc Eventbuilder]~\\http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/EventBuilderDabc
+ \item[DABC Eventbuilder]~\\http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/EventBuilderDabc
\end{description*}
\netname{TrgFanoutAddOn} & LVDS Out & -- & 4+8 & trigger signal to fan-out chip. Available on RJ-45 and pinhead \\
\hline
\netname{LedBank} & & & 8 & 8 yellow LED in a row\\
- \netname{LedFan*} & & & 4 & 4 colorful LED next to fan-out chip\\
+ \netname{LedFan*} & & & 4 & 4 colourful LED next to fan-out chip\\
\netname{LedRj} & & & 2x6 & red and green LED for each RJ-45 connector. Order is JIn1, JIn2, JOut1, JOut2, JFan2, EclIn\\
\hline
\end{tabularx}
\end{center}
\end{table}
-An AddOn for the central FPGA featuring some CTS I/O connections. Since it was not forseen to actually use such an AddOn when the TRB3 was designed, there are several possible issues with the design:
+An AddOn for the central FPGA featuring some CTS I/O connections. Since it was not foreseen to actually use such an AddOn when the TRB3 was designed, there are several possible issues with the design:
\begin{itemize*}
\item All LVDS outputs from the FPGA to the AddOn do not use standard LVDS-outputs, but emulated signals (FPGA produces differential TTL signals which are sent through three resistors to adjust signal heights and impedance. The performance might be somewhat lower than on dedicated LVDS lines (e.g. on the two RJ-45 connectors on the TRB3 itself)
\item Most of the differential lines on the AddOn are not routed differentially on the TRB3 which might have an influence on the signal quality
The logic's behaviour is modelled using two FSMs, one controlling the trigger distribution and one for the readout
process. Both are connected by the so-called readout queue, a FIFO storing the identification of event that have been
- triggered, but not yet read out. In case of a malfunction during read out causing a timeout this queue is likely to
+ triggered, but not yet read out. In case of a malfunction during read out causing a time-out this queue is likely to
overflow which inhibits the distribution of further trigger events.
If your CTS does not accept further events and has a full read-out queue, consider to check the
In this case take care, that the line is pulled down before the busy-release is send over the network.
Using a bitmask in the CTS, each FPGA line can be selected individually. If any selected line fires, the trigger is
- propageted using to the ITC. Atmost one module can be synthesised.
+ propagated using to the ITC. Utmost one module can be synthesised.
\subsubsection{Coincidence detection}
\label{sec:cts_bb_trigger_logic_coin}
a resolution of 10~ns ranging from a continuously asserted signal to one event per 42.9~s. In the frequency domain, the
discretisation error growths with shorter intervals. The relative error, however, is less $< 10^{-3}$ for rates below 100~KHz.
- The \emph{pseudorandom pulser} available in the CTS employs a 32~bit~CRC unit with a fixed data word at its input to
+ The \emph{pseudo random pulser} available in the CTS employs a 32~bit~CRC unit with a fixed data word at its input to
generate pseudo random numbers (PRN). If multiple instance of the pulser are synthesised with different constants. As
simulations suggest, the values generated are nearly uniform deviates.
Furthermore, the distance between two successive numbers is also distributed almost uniformly and
is produced. Since the numbers are uniform deviates, the average duty cycle of the pulser is given
by the threshold divided by the maximum value possible. % (see figure~\ref{fig:cts_bb_trigger_logic_pseudorand}a).
In addition, the uniformly distributed distances prevent the clustering of events that can be observed with
- other pseudorandom number generators, such as linear feedback shift registers.
+ other pseudo random number generators, such as linear feedback shift registers.
\subsubsection{External Trigger Logic}
\label{sec:cts_bb_trigger_logic_external_logic}
\end{figure}
If supported by the experimental set-up it might be beneficial to reduce the trigger frequency of a free-running system during offspill phase.
- Especially if there are many frontends in the DAQ, substantial data reductions can be achieved.
+ Especially if there are many front-ends in the DAQ, substantial data reductions can be achieved.
As shown in Figure~\ref{fig:cts_free_running}, you need two pulsers, two coincidence modules, four input modules and a spill-indicator, that is available to an input module (e.g. any input of the CTS-Addon or an appropriate pin of the onboard RJ45-jacks):
In the diagram \texttt{Pulser3} is engaged during spill time: While its ITC is disabled, the signal is received from \texttt{InputModule2} and forwarded to \texttt{Coincidence1}.
\includegraphics[width=0.495\textwidth]{figures/cts_latency_mbs.png}
\caption[Latency and Jitter measurements]{Latency and jitter measurement ...
\textbf{(a) Left:} ... using trigger input. Yellow: Input,\\ Green: Time Reference signal,
- Purple: Arrival at frontend (on board)
+ Purple: Arrival at front-end (on board)
\textbf{(b) Right:} ... using MBS module. Aqua (blue): MBS data stream (input), Purple: Time Reference.
The first falling edge of the MBS data stream starts the trigger message.}
\label{fig:cts_bb_latency}
linearly, if either of those values is increased. The ITC handling further requires 2 cycle, followed by
additional 2 cycles until the time reference signal is available. In total, this
sums up to a delay of 80~ns. On a TRB3 board, the TrbNet stack requires another 450~ns to deliver the LVL1 packet.
- While this number significantly influences the system's dead time, frontends with critical timing constraints typically
+ While this number significantly influences the system's dead time, front-ends with critical timing constraints typically
use the time reference.
\item The MBS input module is an external trigger module sampling a serial data stream of 50~Mbits$^{-1}$. It
It is experienced that the GUI is not displayed correctly with some browsers
or some versions of the browsers. If you can not see the GUI correctly (no
plot, no trigger registers etc.), but you are sure, that everything is set
- correctly in your set up and the output of the cts\_gui script doesn't show
+ correctly in your set up and the output of the cts\_GUI script doesn't show
any error messages, then you should try to connect with a different browser.
If available, a recent Firefox version is recommended.
\end{warning}
\end{tabularx}
\caption[RJ45 Connections of the Central FPGA]{All signals are
LVDS, hence P/N pins. The column signal refers to the name in
- \files{trb3/cts/trb3\_central.vhd}. The color coding standard of
+ \files{trb3/cts/trb3\_central.vhd}. The colour coding standard of
the RJ45 cable is T568B. The parenthesis in column denote the
index of a std\_logic\_vector signal.}
\label{tab:trb3_central_rj45_connections}
introducing a jitter of several 100~ns.
\item If your module has to send information to the event build, you need to implement the read-out channel. Otherwise
- just leave it unconnected - the default values instruct the frontend to send no data. The Read-Out Channel is directly
+ just leave it unconnected - the default values instruct the front-end to send no data. The Read-Out Channel is directly
connected to a FEE IPU Channel. See the HADES DAQ manual for more information.
\item \signal{cts\_ext\_control} offers you a 32~bit control register without any restrictions on the mapping. Bit 0 should be
The later source of uncertainty does not occur when using the counters sent to the event builders.
\item \textbf{\addr{0x12} AddOn Input Multiplexer}. This block is only present, when the CTS was synthesised with
- atleast one AddOn Input Multiplexer. It contains one word per module, which is interpreted as an unsigned index for
+ at least one AddOn Input Multiplexer. It contains one word per module, which is interpreted as an unsigned index for
the multiplexer. The mapping is defined in table \ref{tab:cts_addon_input_mapping}.
- \item \textbf{\addr{0x13} Peripherial FPGA Trigger Inputs}. This block is present, when CTS was synthesised with
+ \item \textbf{\addr{0x13} Peripheral FPGA Trigger Inputs}. This block is present, when CTS was synthesised with
\texttt{PERIPH\_TRIGGER\_COUNT} = 1 and contains a single word payload of which the lower four bit are used as
- a bitmask to select the active FPGAs. The LSB correspondins to FPGA 1, the MSB to FPGA 4.
+ a bitmask to select the active FPGAs. The LSB corresponds to FPGA 1, the MSB to FPGA 4.
\item \textbf{\addr{0x20} Coincidence Configuration}. Each coincidence detection module (see
~\ref{sec:cts_bb_trigger_logic_coin}) has one configuration register. Thus, the number of registers
\item \textbf{\addr{0x60} External logic - CBM/MBS}. This module indicates the presence of the CBM adapter
module. If set, the lowest bit of the control registers prevents the module from sending data to the
- event builder. The lower 24~bit of the status register contains the timestamp of the last event seen. The
+ event builder. The lower 24~bit of the status register contains the time-stamp of the last event seen. The
MSB holds the error flag.
\item \textbf{\addr{0x61} External logic - Mainz A2}. This module
indicates the presence of the Mainz A2 adapter module. If set,
the lowest bit of the control registers prevents the module from
sending data to the event builder. The lower 31~bit of the
- status register contains the timestamp of the last event seen.
+ status register contains the time-stamp of the last event seen.
The MSB holds the error flag.
\end{itemize}
\paragraph*{VHDL Configuration}
The number of bits per word can be set with a generic in the VHDL component instantiation. If a value below 32 is chosen, the upper bits in all registers are ignored.
-The number of waitcycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz.
+The number of wait-cycles between two edges on SCK can be selected as well. The default for LTC2600 and Padiwa is 7 wait cycles, I.e. 6.25 MHz.
\paragraph*{Configuration File}
The software takes a text file as input and generates the correct SPI sequence to load and activate the DAC.
- For the experiments with trigger, where the coarse and epoch counters are reset after every event, the asynchronous trigger is used to start the data acquisition. This asynchronous trigger from the detector is processed and synchronised at the Central Trigger System (CTS) and a data readout trigger is sent to the End Points, e.g. TDCs. The arrival of this readout trigger is measured and stored at the Reference Channels (Channel 0) of the TDCs. However, as this data readout trigger is synchronised to the system clock at the CTS, it doesn't carry real time information of the trigger from the detector. The time information at the Reference Channel should be used to synchronise all of the TDCs in the system. In order to calculate the relative hit times to the asynchronous trigger from the detector, the asynchronous trigger must be physically applied to a channel input of a TDC and the time information must be gathered. In future designs the measurement of the asynchronous trigger signal will be done in the CTS by an embedded TDC but confirm the design version you are using by contacting one of the developers!
\ No newline at end of file
+ For the experiments with trigger, where the coarse and epoch counters are
+ reset after every event, the asynchronous trigger is used to start the data
+ acquisition. This asynchronous trigger from the detector is processed and
+ synchronised at the Central Trigger System (CTS) and a data readout trigger
+ is sent to the End Points, e.g. TDCs. The arrival of this readout trigger is
+ measured and stored at the Reference Channels (Channel 0) of the
+ TDCs. However, as this data readout trigger is synchronised to the system
+ clock at the CTS, it doesn't carry real time information of the trigger from
+ the detector. The time information at the Reference Channel should be used to
+ synchronise all of the TDCs in the system. In order to calculate the relative
+ hit times to the asynchronous trigger from the detector, the asynchronous
+ trigger must be physically applied to a channel input of a TDC and the time
+ information must be gathered. In future designs the measurement of the
+ asynchronous trigger signal will be done in the CTS by an embedded TDC but
+ confirm the design version you are using by contacting one of the developers!
\label{sec:GbeGettingStarted}
In order to control TRB3 or a larger system with TRB3 as slow control client
via Ethernet link, one needs to properly install and compile the trbcmd
-server, load a correct FPGA design and configure DHCP deamon on the server
+server, load a correct FPGA design and configure DHCP daemon on the server
PC.Follow the instructions described in the next points.
\subsubsection{FPGA design}
part: 02:00:BE:UNIQUE$\_$ID(31 downto 8)
\begin{itemize*}
-\item Open /etc/dhcpd.conf and add an entry specifing hostname and MAC address
-\item Open /etc/hosts and add an etry specifing hostanme and an selected IP address
+\item Open /etc/dhcpd.conf and add an entry specifying hostname and MAC address
+\item Open /etc/hosts and add an entry specifying hostanme and an selected IP address
\item Restart DHCP daemon
\end{itemize*}
-Now you can reload the central FPGA and it should automatically aquire the IP
+Now you can reload the central FPGA and it should automatically acquire the IP
address from the server. One can verify that by monitoring the network traffic
or system log file.
way is to use a trbnetd running on any machine in the network, which has
direct UDP access to the TRB3 to be controlled. This daemon then collects all
requests from many different clients and takes care of the correct
-arbritration (doesn't work for non atomic accesses, like SPI-interface which
+arbitration (doesn't work for non atomic accesses, like SPI-interface which
needs to access several registers one after the other). The trbnetd needs to
know the ip-address of the TRB3 and *can* additionally be identified via a 8
bit number. So, to start the trbnetd which connects to the TRB3 with the
Installation:
-For security reasons normally RPC-calls are only accepted from the loopback
+For security reasons normally RPC-calls are only accepted from the loop-back
interface, so we have to tell the rpcbind daemon running on the machine where
the trbnetd should run, that it should accept connections from anywhere.
This is the option "-i".
\label{sec:GbeDataReadout}\r
-Communication with TRB3 is handled by the Gigabit Ethernet interface (SPF8 by default). It can be used for Slow Control connection (see next section) and for the readout of collected data. In order to act as standard network device, there are several protocols that share the same link. The basic ones for the network discovery are DHCP, ARP and ICMP. Protocols typical for data handling in standard TRB3 implementation are SCTRL and TrbNetData. Even though they all can run in parallel, processing data, they all share the same input and output link, distributing 125MBps bandwidth. \r
+Communication with TRB3 is handled by the Gigabit Ethernet interface (SFP8 by default). It can be used for Slow Control connection (see next section) and for the readout of collected data. In order to act as standard network device, there are several protocols that share the same link. The basic ones for the network discovery are DHCP, ARP and ICMP. Protocols typical for data handling in standard TRB3 implementation are SCTRL and TrbNetData. Even though they all can run in parallel, processing data, they all share the same input and output link, distributing 125MBps bandwidth. \r
\r
\begin{figure}[!htbp]\r
\begin{center}\r
0x8300 + offset & Description & Default value\\ \hline\r
0 & Subevent ID value for the header field & 0x000000cf \\ \hline\r
1 & Subevent decoding value for the header field & 0x00020001 \\ \hline\r
- 2 & Queue decoding valuke for the header field & 0x00030064 \\ \hline\r
+ 2 & Queue decoding value for the header field & 0x00030064 \\ \hline\r
4 & Max Ethernet frame size (MTU) can be set up to 4kB & 0x00000578 \\ \hline\r
5 & Enable GbE data transport & 0x0 (DISABLED BY DEFAULT) \\ \hline\r
- 7 & Enable multievent mode & 0x0 \\ \hline\r
+ 7 & Enable multi-event mode & 0x0 \\ \hline\r
8 & Update readout counter value & 0x000000 \\ \hline\r
9 & Enable RX channel & 0x1 \\ \hline\r
A & Include additional SlowControl data header & 0x1 \\ \hline\r
\r
\newpage\r
\r
-Additionally there are two register groups, one for SlowControl and another for TrbNetData that can be used for histograming of outgoing packet sizes. Each group consists of 32 x 32bits registers, where each register represents a counter of packets with size within a specified range. The size difference between two regiters is 2kB, so the first register is a counter for packets with sizes from 0 to 2kB and so on.\r
+Additionally there are two register groups, one for SlowControl and another for TrbNetData that can be used for monitoring of outgoing packet sizes. Each group consists of 32 x 32bits registers, where each register represents a counter of packets with size within a specified range. The size difference between two registers is 2kB, so the first register is a counter for packets with sizes from 0 to 2kB and so on.\r
\r
\begin{table}[!htbp]\r
\begin{center}\r
\subsection{Mechanics}
\begin{description}
- \item[Plates]{A technical drawing of the holding plates for TRBs can be found on the webpage. 2mm aluminium suits best. Note that plates for TRB2 and TRB3 are slightly different to accomodate position of SFPs and to allow air-flow underneath the AddOns.}
- \item[Fan Holder]{A technical drawing of a small holder for 12cm fans is available on the webpage.}
+ \item[Plates]{A technical drawing of the holding plates for TRBs can be found on the web page. 2mm aluminium suits best. Note that plates for TRB2 and TRB3 are slightly different to accommodate position of SFPs and to allow air-flow underneath the AddOns.}
+ \item[Fan Holder]{A technical drawing of a small holder for 12cm fans is available on the web page.}
\item[Necessary bolts and screws] Necessary material for mounting one TRB3:
\begin{itemize*}
\item 4x M4 distance bolts, 60 -- 120 mm (for stacking plates)
\item[1:10 LVDS fan-out]~\\
The good old ten-fold fan-out board using standard pin-header (with secured connector)
\item[8x 1:4 LVDS fan-out]~\\
- 8 LVDS inputs to 3x 8 outputs. Plus 8 TTL outputs on Lemo connectors for easy connection to a scope. Plus a analog multiplicity output with 100mV amplitude. Fits to TRB3 stack.
+ 8 LVDS inputs to 3x 8 outputs. Plus 8 TTL outputs on LEMO connectors for easy connection to a scope. Plus a analog multiplicity output with 100mV amplitude. Fits to TRB3 stack.
\item[RJ-45 to pin-header]~\\
Adaptor from RJ-45 to four times dual pin-header (with clips to secure connector). In case one has to connect individual signals to the RJ-45 inputs of the TRB.
\item[Power Switch]~\\
\item[Debug / JTAG Adaptor]~\\
Adaptor from the 20 pin FPC connector next to many FPGAs to a standard pin-header.
\item[LCD]~\\
- The debugging output of the TRB3 can be used to connect a 320x240 color LCD to show the status of some variables. Available for less than 10 Euro, including an adaptor for easy connection. Schematics can be found in the electronics.git.
+ The debugging output of the TRB3 can be used to connect a 320x240 colour LCD to show the status of some variables. Available for less than 10 Euro, including an adaptor for easy connection. Schematics can be found in the electronics.git.
\item[USB for Instek power supplies]~\\
The common Instek PSP-405 power supplies have a peculiar RS232 interface. A matching adaptor to USB as plug-on module. Schematics can be found in the electronics.git.
\item[USB-to-RS232 with optocouplers]~\\
\subsubsection{Known bugs}
\begin{itemize*}
\item The serial interface to ADC 1 is not usable - CSB and PDWN are input-only on the FPGA
- \item SDIO is missing a pull-down. This way the device runs in low-power mode on the digitial outputs.
- \item LVDS\_INP\_2 is the only LVDS port that is terminated by an external resistor. Do not switch on corresponding LVDS termiantion in FPGA
+ \item SDIO is missing a pull-down. This way the device runs in low-power mode on the digital outputs.
+ \item LVDS\_INP\_2 is the only LVDS port that is terminated by an external resistor. Do not switch on corresponding LVDS termination in FPGA
\end{itemize*}
\ No newline at end of file
\subsection{Clock Measurements}
To check the limits of the clock recovery circuitry of the FPGAs a system
-consiting of 5 TRB3 was setup. One master TRB3 with the TRBHub design in one
+consisting of 5 TRB3 was setup. One master TRB3 with the TRBHub design in one
peripheral FPGA, 4 slaves, where 3 of the slaves were in one chain, and the
4th slave was connected to the master as a single board. So, each slave
-reveived the clock of the level above in the central FPGA (FPGA5) where the
+received the clock of the level above in the central FPGA (FPGA5) where the
clock was recovered. This clock is then used to communicate to the peripheral
FPGA, where again a HUB-design was running. This peripheral FPGA again
recovered the clock. And so on.
The time-trend analysis of the measured deviations of the recovered clock to
the ideal clock shows already after the first recovery that there is very
-small random jitter, but a dominant sinodial time deviation with a frequency
+small random jitter, but a dominant synodical time deviation with a frequency
of 4MHz. This suggests that a jitter cleaner (if the time constants are too
short) will not help a lot and that the jitter comes from the power-supply of
the FPGAs-PLL-circuitry. The DC/DC-converters on the TRB3 run with 4MHz, which
can be a coincidence, but directly points to them as the source of the
deterministic ``jitter'' (period length oscillation). This has to be
-investigaed further to be understood in detail.
+investigated further to be understood in detail.
\subsection{Media Interfaces}
\item The master declares the connection active and changes its own idle comma character.
\end{enumerate}
-Using a recovered clock to drive its own transceivers has the implication that if one link is lost and needs to be restarted, the full tree of boards behind the erroneous one needs to be resynchronized. It needs to be investigated if this is possible in a clean way or all these FPGA need to be resetted automatically because of loss of the RX clock. This needs in detail check of the transceiver PLLs in case of an unlock of the clock recovery PLL.
+Using a recovered clock to drive its own transceivers has the implication that if one link is lost and needs to be restarted, the full tree of boards behind the erroneous one needs to be resynchronized. It needs to be investigated if this is possible in a clean way or all these FPGA need to be reset automatically because of loss of the RX clock. This needs in detail check of the transceiver PLLs in case of an unlock of the clock recovery PLL.
The bi-directional hand-shake by changing comma characters is necessary when front-ends are able to actively send data to the read-out - it can be omitted if there is only a central master as in triggered systems.
\paragraph{Comma Characters}~\\
-Each control word consists of two parts, a comma character and a data character. Assignment of individual character is not fixed and can be changed by constants in a vhdl package. CBMnet uses a set of 64 16 bit characters with big Hamming distance for error correction - this will not be done in TrbNet due to additional overhead and low error rates on transmission via SFP.
+Each control word consists of two parts, a comma character and a data character. Assignment of individual character is not fixed and can be changed by constants in a VHDL package. CBMnet uses a set of 64 16 bit characters with big Hamming distance for error correction - this will not be done in TrbNet due to additional overhead and low error rates on transmission via SFP.
\begin{table}[ht]
first bin. For the second bin, it is the summation of the bin width value of
the first bin and half of the bin width value of the second bin, and so
on. After creating the LUT this is used for subsequent measurements. An
-example of calibrated and un-calibrated time values are shown in
+example of calibrated and uncalibrated-calibrated time values are shown in
\autoref{fig:calibration}. As may be seen from the graph, the quantisation
levels of the calibrated data are distributed along the time more evenly than
-the un-calibrated data quantisation steps. As these quantisation steps effect
+the uncalibrated-calibrated data quantisation steps. As these quantisation steps effect
the non-linearities of the TDC, calibration has lowers the non-linearity
values.
\hline
Bit & \multicolumn{1}{|c|}{Explanation} \\
\hline
- 0 & Reserved. \\
- 1 & At least one of the channel FIFOs is full. \\
- 2 & At least one of the channel FIFOs has more than 28 data words. \\
- 3-15 & Reserved. \\
+ 0 & At least one of the channel ring buffers is overwritten. \\
+ 1-15 & Reserved. \\
\hline
\end{tabular}
\caption{TDC Header Error bits.}
\label{fig:tdcTrigWin}
\end{figure}
-Trigger mode is controled by register 0xc800 bit 12. If it is set to triggered
+Trigger mode is controlled by register 0xc800 bit 12. If it is set to triggered
mode ('1'), the epoch and coarse counters are reset after each trigger
-window. If this bit is set to triggerless mode ('0'), the epoch and coarse
+window. If this bit is set to trigger-less mode ('0'), the epoch and coarse
counters are never reset, unless there is a system wide reset. They will run
until they have an overflow.
\hline
0xc804 & Data transfer limit & 7-0 & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout.\\
- & Removed after version 2.1.1 & & \textbf{ATTENTION! This conrol is implemented only for debug readons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\
+ & Removed after version 2.1.1 & & \textbf{ATTENTION! This control is implemented only for debug reasons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\
& & 31-8 & reserved.\\
\hline
& 5 & encoder start pulse\\
& 6 & encoder finished pulse\\
& 7 & valid timing trigger pulse from the endpoint\\
- & 8 & fifo write pulse\\
+ & 8 & FIFO write pulse\\
& 15-9 & fine time bits between 6-0\\
\hline
\multirow{4}{*}{x"3"} & 7-0 & Debug word of the TDC Readout FSM (see \ref{tab:tdcReadoutFsm})\\
x"F" & OTHERS & should never be in this state. If yes, there is a problem.\\
\hline
\end{tabularx}
- \caption{TDC Writeout FSM debug word bitmap.}
+ \caption{TDC Write-out FSM debug word bitmap.}
\label{tab:tdcWriteoutFsm}
\end{center}
\end{table}
\endlastfoot
0xc100 & Basic controls & 3-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
- & & 7-4 & Debug word of the TDC writeout FSM (see \ref{tab:tdcWriteoutFsm})\\
+ & & 7-4 & Debug word of the TDC write-out FSM (see \ref{tab:tdcWriteoutFsm})\\
& & 15-8 & Implemented channel number.\\
& & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\
& & 27-17 & reserved\\
& & 31-24 & reserved\\ \hline
0xc10f & Release number & 23-0 & Number of release signals sent\\
& & 31-24 & reserved\\ \hline
- 0xc110 & Readout time & 23-0 & Total time length, that the readout occured (with granularity of 10~ns)\\
+ 0xc110 & Readout time & 23-0 & Total time length, that the readout occurred (with granularity of 10~ns)\\
& & 31-24 & reserved\\ \hline
- 0xc111 & Timeout number & 23-0 & Number of timeouts detected (too long delay after the timing trigger)\\
+ 0xc111 & Time-out number & 23-0 & Number of time-outs detected (too long delay after the timing trigger)\\
& & 31-24 & reserved\\ \hline
0xc112 & Finished number & 23-0 & Number of sent finished signals\\
& & 31-24 & reserved\\ \hline
e.g. \verb|trbcmd r 0xc001| would give the hits detected by channel 1. In the
same register the MSB shows the logic level of the output of the input LVDS
buffers. This bit is useful for the designs, which use the LVDS buffers as
-discriminators, e.g. cbmrich and padiwa projects. The data format of the
+discriminators, e.g. cbmrich and Padiwa projects. The data format of the
register is shown below:
\hline \hline
\endlastfoot
- tdc\_v2.1.0 & 15.12.2014 & The ring buffer almost full threshold is made dynamic in order to "mimic" a adjustable ring buffer size.\\\hline
- tdc\_v2.0.1 & 05.12.2014 & Calibration-physik trigger switching problem is fixed.\\
- & & With the calibration trigger 50ns pulses are sent to the channels in order to calibrate the ToT measurements in the channels. There are some grass hits around the main peak.\\\hline
- tdc\_v2.0 & 01.12.2014 & Double edge detection in a single channel is implemented.\\\hline
- tdc\_v1.7.3 & 15.08.2014 & Hit scaler register size is increased to 31 bits.\\\hline
- tdc\_v1.7.1 & 29.07.2014 & Feature Bit support.\\
- & & Tidy up the entities.\\\hline
- tdc\_v1.7 & 24.06.2014 & Paralel working Readouts are implemented.\\
- & & Trigger time calculation is done in the trigger handler.\\\hline
- tdc\_v1.6.3 & 24.06.2014 & Bug fix in the hit rate counters (syncronisation problem).\\\hline
- tdc\_v1.6.2 & 08.05.2014 & Small bug fix in the wait time for data transfer to buffer.\\\hline
- tdc\_v1.6.1 & 06.05.2014 & Less EPOCH counter - unnecessary EPOCH words, which occur with enabled trigger window, are eliminated from the data stream.\\
- & & FSM initialisation problem by the Channel\_200 entity is solved.\\
- & & Channel FSM debug words are written to bus 0xc200.\\
- & & Number of coarse counters is increased to 16 to ease the fanout.\\
- & & Bug fix for the missing data with the calibration trigger.\\
- & & Bug fix for the duplicate data when trigger window is enabled.\\\hline
- tdc\_v1.6 & 20.01.2014 & Epoch counter bug fix (data word - epoch word place swap).\\
- & & Trigger window bug fix (epoch counter more than 24 bit had integer conversion problem. Trigger window right side control is enabled).\\
- & & Readout algorith change (the channel fifos are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time).\\
- & & Trigger on TDC channel (the feature for triggering on TDC channel is implemented).\\
- & & Reference channel hit rate counter implemented.\\
- & & The channels (incl. ch0) can be calibrated with the internal oscillator with different frequencies (see manual slow control registers).\\
- & & The coarse counter can be set to reset via slow control. The action will take place when the first valid trigger arrives.\\\hline
- tdc\_v1.5.1 & 20.06.2013 & Efficiency bug fix (epoch counter update - hit at the same time).\\
- & & Hit level bit bug fix for the web server.\\
- & & Reference Channel coarse counter alignmet fix.\\\hline
- tdc\_v1.5 & 03.05.2013 & TDC calibration trigger is implemented in order to shoot every channel with sufficient \# of hits for proper calibration.\\
- & & TDC is adapted for short pulses.\\\hline
- tdc\_v1.4 & 18.04.2013 & Limiting data transfer functionality is added. Use 0xc804 register to define the \# of word per channel to be read-out.\\\hline
- tdc\_v1.3 & 05.03.2013 & Encoder efficiency is increased to 100\%.\\
- & & Extra bits are encoded in the data (low resolution and no successfull binary conversion, see the manual).\\
- & & Channel block during the readout is removed. Only the relevant hits per trigger are readout.\\
- & & Control registers are moved to 0xc800.\\\hline
- tdc\_v1.2 & 12.11.2012 & First strecher prototype is successfully implemented.\\
- & & Some bugs are fixed.\\\hline
- tdc\_v1.1.1 & 07.11.2012 & The status registers are moved to the bus address 0xc100.\\
- & & Also debug registers (encoder start, fifo write, lost hits) are included in the bus - 0xc200 0xc300 0xc400.\\\hline
- tdc\_v1.1 & 26.10.2012 & Readout process is collected in an individual entity.\\\hline
- tdc\_v1.0 & 25.10.2012 & The time measurement interval is extended with a 28-bit epoch counter.\\\hline
- tdc\_v0.5 & 22.10.2012 & Hit counter registers and LVDS receiver output.\\\hline
+
+ tdc\_v2.1.1 & 02.02.2015 & - The dead time of the TDC is decreased to 20~ns.\\
+ & & - Small bug fix with "Light Mode".\\
+ & & - "Data Limit" parameter is removed, as it is not needed due to the dynamic buffer size.\\
+ & & - Coarse/Epoch counter misalignment bug fix.\\
+ & & - Channel input is blocked until the falling edge information is written in the ring buffer to avoid data mismatch.\\
+ & & - Ring buffer overwrite bit is implemented.\\\hline
+ tdc\_v2.1.0 & 15.12.2014 & - The ring buffer almost full threshold is made dynamic in order to "mimic" a adjustable ring buffer size.\\\hline
+ tdc\_v2.0.1 & 05.12.2014 & - Calibration-physic trigger switching problem is fixed.\\
+ & & - With the calibration trigger 50~ns pulses are sent to the channels in order to calibrate the ToT measurements in the channels. There are some grass hits around the main peak.\\\hline
+ tdc\_v2.0 & 01.12.2014 & - Double edge detection in a single channel is implemented.\\\hline
+ tdc\_v1.7.3 & 15.08.2014 & - Hit scaler register size is increased to 31 bits.\\\hline
+ tdc\_v1.7.1 & 29.07.2014 & - Feature Bit support.\\
+ & & - Tidy up the entities.\\\hline
+ tdc\_v1.7 & 24.06.2014 & - Parallel working Readouts are implemented.\\
+ & & - Trigger time calculation is done in the trigger handler.\\\hline
+ tdc\_v1.6.3 & 24.06.2014 & - Bug fix in the hit rate counters (synchronisation problem).\\\hline
+ tdc\_v1.6.2 & 08.05.2014 & - Small bug fix in the wait time for data transfer to buffer.\\\hline
+ tdc\_v1.6.1 & 06.05.2014 & - Less EPOCH counter - unnecessary EPOCH words, which occur with enabled trigger window, are eliminated from the data stream.\\
+ & & - FSM initialisation problem by the Channel\_200 entity is solved.\\
+ & & - Channel FSM debug words are written to bus 0xc200.\\
+ & & - Number of coarse counters is increased to 16 to ease the fanout.\\
+ & & - Bug fix for the missing data with the calibration trigger.\\
+ & & - Bug fix for the duplicate data when trigger window is enabled.\\\hline
+ tdc\_v1.6 & 20.01.2014 & - Epoch counter bug fix (data word - epoch word place swap).\\
+ & & - Trigger window bug fix (epoch counter more than 24 bit had integer conversion problem. Trigger window right side control is enabled).\\
+ & & - Readout algorithm change (the channel FIFOs are readout to intermediate buffer, so the later channels in the readout order are kept as the trigger arrival time).\\
+ & & - Trigger on TDC channel (the feature for triggering on TDC channel is implemented).\\
+ & & - Reference channel hit rate counter implemented.\\
+ & & - The channels (incl. ch0) can be calibrated with the internal oscillator with different frequencies (see manual slow control registers).\\
+ & & - The coarse counter can be set to reset via slow control. The action will take place when the first valid trigger arrives.\\\hline
+ tdc\_v1.5.1 & 20.06.2013 & - Efficiency bug fix (epoch counter update - hit at the same time).\\
+ & & - Hit level bit bug fix for the web server.\\
+ & & - Reference Channel coarse counter alignment fix.\\\hline
+ tdc\_v1.5 & 03.05.2013 & - TDC calibration trigger is implemented in order to shoot every channel with sufficient \# of hits for proper calibration.\\
+ & & - TDC is adapted for short pulses.\\\hline
+ tdc\_v1.4 & 18.04.2013 & - Limiting data transfer functionality is added. Use 0xc804 register to define the \# of word per channel to be read-out.\\\hline
+ tdc\_v1.3 & 05.03.2013 & - Encoder efficiency is increased to 100\%.\\
+ & & - Extra bits are encoded in the data (low resolution and no successful binary conversion, see the manual).\\
+ & & - Channel block during the readout is removed. Only the relevant hits per trigger are readout.\\
+ & & - Control registers are moved to 0xc800.\\\hline
+ tdc\_v1.2 & 12.11.2012 & - First stretcher prototype is successfully implemented.\\
+ & & - Some bugs are fixed.\\\hline
+ tdc\_v1.1.1 & 07.11.2012 & - The status registers are moved to the bus address 0xc100.\\
+ & & - Also debug registers (encoder start, FIFO write, lost hits) are included in the bus - 0xc200 0xc300 0xc400.\\\hline
+ tdc\_v1.1 & 26.10.2012 & - Readout process is collected in an individual entity.\\\hline
+ tdc\_v1.0 & 25.10.2012 & - The time measurement interval is extended with a 28-bit epoch counter.\\\hline
+ tdc\_v0.5 & 22.10.2012 & - Hit counter registers and LVDS receiver output.\\\hline
\hline
\end{longtable}
-\end{center}
\ No newline at end of file
+\end{center}
experienced failures happen according to Murphy always when you really don't
need them :-)...
So, please don't go to a beam time with {\bf one} TRB3 and no replacement module and
-always be sure that you have a Lattice Download Cable available to reflash the
+always be sure that you have a Lattice Download Cable available to re-flash the
TRB3 if something goes wrong in the fever of a beam time.
\item[0040] {\color{darkgray}sends triggers to optical link SFP1}
\item[0080] {\color{darkgray}sends slow-control to optical link SFP1}
\end{description*}
-\item[Peripheral FPGA (also CBM-RICH and other derivates)]~
+\item[Peripheral FPGA (also CBM-RICH and other derivatives)]~
\begin{description*}
\item[0XXX] use with ADA adapter board AddOn version 1
\item[1XXX] use with ADA adapter board AddOn version 2
- \item[2XXX] use with multipurpose test AddOn
+ \item[2XXX] use with multi-purpose test AddOn
\item[3XXX] use with SFP hub AddOn
\item[4XXX] use with Padiwa adapter AddOn
\item[5XXX] use with General Purpose AddOn - with NIM connectors
\item[7] GND (n/c)
\item[8] GND (n/c)
\end{description*}
-Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards. If you experience strange behavior of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
+Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards. If you experience strange behaviour of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
Note that the programming cable can only be used as root by default in most Linux flavours. You can either change permissions on the device in /dev/ by hand or put this (as one line!)
\\\verb!SUBSYSTEMS=="usb", ATTRS{idVendor}=="1134", SYMLINK+="lattice_cable",!
\subsection{Data Unpacker}
\label{Data_Unpacking}
-The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender of each block of data. While SubSubEvent-IDs are equal to the network address of the corresponding board by design, the SubEvent-IDs can be choosen freely, but are defined to be equal to the network address of the board sending the SubEvent via Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine how the following data has to be handled:
+The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender of each block of data. While SubSubEvent-IDs are equal to the network address of the corresponding board by design, the SubEvent-IDs can be chosen freely, but are defined to be equal to the network address of the board sending the SubEvent via Gigabit Ethernet. The first digit of each SubSubEvent-ID is sufficient to determine how the following data has to be handled:
\begin{description*}
\item[0..1] Unpack as TDC data
\item[5555] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.
\item SPARE\_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL
\item On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now.
\item Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
-\item The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa.
+\item The JTAG Connector is wrong. The line labelled TDI is TDO and vice versa.
\item The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one.
\end{itemize*}
The program is invoked by the other \files{compile*.pl} scripts and the \files{/base/create\_project.pl} tool and has the following tasks:
\begin{itemize*}
\item Create the workdir if not existing
-\item Execute \files{base/linkdesignfiles.sh} with the correct parameters to account for a varing number of \files{../} of the relative links generate
+\item Execute \files{base/linkdesignfiles.sh} with the correct parameters to account for a varying number of \files{../} of the relative links generate
and depending on the position of the workdir relative to the repositories root directory.
\item Combine global and design specific \files{*.lpf}-files into a single file \files{\{workdir\}/\{topname\}.lpf}.
\item Optional: Generate design specific script that are invoked in the build process.
This section briefly outlines an alternative (and maybe easier and
more comfortable) way to configure the TRB boards. It uses dnsmasq to
-provide the IP addresses over DHCP and also automagic DNS resolution.
+provide the IP addresses over DHCP and also auto-magic DNS resolution.
That means that you need to add only one line for every new TRB board.
We assume that your TRB boards are connected to a network reachable
over \verb!eth1!, and that your PC is the only DHCP server on this
So, starting from the default configuration file
\files{/etc/dnsmasq.conf} on Debian/stable, add the following lines
-(or uncomment/change the appropiate existing ones):
+(or uncomment/change the appropriate existing ones):
\begin{lstlisting}[label=,caption=Changes to /etc/dnsmasq.conf]
interface=eth1
dhcp-range=192.168.0.0
dhcp-host=02:00:be:f9:df:37,trb019,192.168.0.19,infinite
dhcp-authoritative
\end{lstlisting}
-You can add more TRB boards with appropiate \verb!dhcp-host=! lines.
+You can add more TRB boards with appropriate \verb!dhcp-host=! lines.
Now restart dnsmasq to make your changes take effect. Monitor the
successful DHCPACK in \files{/var/log/syslog}. If you have an dhclient
on eth0 (maybe your usual, non-TRB network), you can add your
run \verb!./cts_gui!, to be found in \verb!daqtools/web! (must be the working directory!). There
are few option to set the network port the server runs on (default: 1234), configure the
output on the command line or to override the default CTS endpoint. Use the \verb!--help! parameter
-for a short overview. Before executing the script, make sure the DAQOPSERVER enviroment variable
+for a short overview. Before executing the script, make sure the DAQOPSERVER environment variable
is set correctly.
\subsection{Event builder}
\section{Software installation}
For convenience I start each code line with prompt (\verb+$+). If the command
-(in brown) is too long for one line, then its continuity starts with intendation in the
+(in brown) is too long for one line, then its continuity starts with indentation in the
next line. Lines starting with \verb+#+ are comments (in green).
% \subsection{Preparation}
Now you can start with the installation of SUSE. Connect the registered
network card with the GSI-network and put in the USB stick. When you have a
-DELL PC press \textbf{F12} and select \textbf{USB} in the bootmenu. Now you can go thru some self-explanatory steps (choose i.e. language, keyboard language, date/time).
+DELL PC press \textbf{F12} and select \textbf{USB} in the bootmenu. Now you can go through some self-explanatory steps (choose i.e. language, keyboard language, date/time).
When you come to the point \textbf{Partitioning}, choose \textbf{Custom Partitioning} and use the following settings.
\begin{lstlisting}[label=,caption=Custom Partitioning]
jspc29 / daqdocu.git / commitdiff