signal rx_dlm_i : std_logic;
signal destroy_link_i : std_logic;
+ signal enable_dlm_i : std_logic;
signal tx_pll_lol_qd_b_i : std_logic;
signal tx_pll_lol_all_i : std_logic;
end if;
end process THE_DLM_SEND_PROC;
- dlm_send_x <= '1' when (dlm_counter(13) = '1') and (word_sync_i = '1') else '0';
+ dlm_send_x <= '1' when (dlm_counter(13) = '1') and (word_sync_i = '1') and (enable_dlm_i = '1') else '0';
tx_dlm_i <= dlm_send_qq;
-- just for testing
destroy_link_i <= common_ctrl_reg(88);
-
+ enable_dlm_i <= common_ctrl_reg(89);
+
end generate;
---------------------------------------------------------------------------
WORD_SYNC_OUT => word_sync_i,
MASTER_CLK_IN => master_clk_i,
MASTER_CLK_OUT => master_clk_i,
- QUAD_RST_IN => '0',
+ QUAD_RST_IN => global_reset_i, --'0', -- TEST
GLOBAL_RESET_OUT => global_reset_i,
SLAVE_ACTIVE_OUT => slave_active_i,
SLAVE_ACTIVE_IN => slave_active_i,
TX_PLL_LOL_OUT => tx_pll_lol_all_i,
TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
- SYNC_TX_QUAD_OUT => sync_tx_quad_i,
+ SYNC_TX_QUAD_OUT => open, --sync_tx_quad_i, -- TEST
LINK_TX_READY_OUT => link_tx_ready_i,
STATE_OUT => tx_reset_state
);
+ sync_tx_quad_i <= '1';
+
---------------------------------------------------------------------------
-- PCSC 4 downlinks
---------------------------------------------------------------------------
SLAVE_ACTIVE_IN => slave_active_i,
TX_PLL_LOL_IN => tx_pll_lol_all_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_CLK_AVAIL_OUT => open, -- BUGBUGBUG
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,
SLAVE_ACTIVE_IN => slave_active_i,
TX_PLL_LOL_IN => tx_pll_lol_all_i,
TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_CLK_AVAIL_OUT => open, -- BUGBUGBUG
TX_PCS_RST_IN => tx_pcs_rst_i,
SYNC_TX_PLL_IN => sync_tx_quad_i,
LINK_TX_READY_IN => link_tx_ready_i,