]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Mon, 4 Jul 2011 15:38:24 +0000 (15:38 +0000)
committerhadeshyp <hadeshyp>
Mon, 4 Jul 2011 15:38:24 +0000 (15:38 +0000)
special/handler_lvl1.vhd
special/trb_net_bridge_pcie_endpoint_hub.vhd
trb_net16_endpoint_hades_full.vhd
trb_net16_endpoint_hades_full_handler.vhd
trb_net16_hub_logic.vhd
trb_net_components.vhd
trb_net_std.vhd

index 83946393d190e26c2602603e2183572a5e904831..6dfb5d7250038ea36f896113fdd7557f58c72ae9 100644 (file)
@@ -50,7 +50,7 @@ port(
   STATUS_OUT                   : out std_logic_vector (63 downto 0); -- bits for status registers
   TRG_ENABLE_IN                : in  std_logic;                      -- trigger enable flag
   TRG_INVERT_IN                : in  std_logic;                      -- trigger invert flag
-  COUNTERS_STATUS_OUT          : out std_logic_vector (63 downto 0); -- 16b starting missing, multiple, spike, spurious-- gk 29.09.10
+  COUNTERS_STATUS_OUT          : out std_logic_vector (79 downto 0); -- 16b starting missing, multiple, spike, spurious-- gk 29.09.10
   --Debug
   DEBUG_OUT                    : out std_logic_vector (15 downto 0)
 );
@@ -140,6 +140,12 @@ signal spurious_ctr         : unsigned(15 downto 0);
 signal ctr_lock             : std_logic;
 signal wrong_polarity       : std_logic;
 
+signal tmg_edge_ctr         : unsigned(15 downto 0);
+signal tmg_edge_found_i     : std_logic;
+signal sr0                  : std_logic;
+signal tmg_edge_async       : std_logic;
+
+
 begin
 
 
@@ -260,6 +266,34 @@ begin
   end if;
 end process MULTIPLE_TRG_FND_PROC;
 
+
+-------------------------------------------------------------------------------
+-- Tmg Trigger spike detect
+-------------------------------------------------------------------------------
+
+  process (tmg_edge_found_i, LVL1_TIMING_TRG_IN)
+    begin
+      if ( tmg_edge_found_i = '1') then 
+        tmg_edge_async <= '0';
+      elsif rising_edge(LVL1_TIMING_TRG_IN) then 
+        tmg_edge_async <= '1'; 
+      end if;
+  end process;
+  
+  -- Asynchrones Merker-FF eintakten
+  process 
+    begin
+      wait until rising_edge(CLOCK);
+      if(tmg_edge_found_i = '1') then 
+        sr0 <= '0'; 
+        tmg_edge_found_i <= '0'; 
+      else
+        sr0 <= tmg_edge_async; 
+        tmg_edge_found_i <= sr0; 
+      end if;
+  end process;
+
+
 ---------------------------------------------------------------------------
 -- Timeout counter for LVL1
 ---------------------------------------------------------------------------
@@ -517,6 +551,16 @@ begin
   end if;
 end process WRONG_POLAR_PROC;
 
+REAL_EDGE_COUNT_PROC : process(CLOCK)
+  begin
+    if rising_edge(CLOCK) then
+      if RESET_STATS_IN = '1' then
+        tmg_edge_ctr <= (others => '0');
+      elsif tmg_edge_found_i = '1' then
+        tmg_edge_ctr <= tmg_edge_ctr + to_unsigned(1,1);
+      end if;
+    end if;
+  end process;
 
 ---------------------------------------------------------------------------
 -- Error bits
@@ -611,7 +655,7 @@ COUNTERS_STATUS_OUT(15 downto 0)  <= std_logic_vector(missing_ctr);
 COUNTERS_STATUS_OUT(31 downto 16) <= std_logic_vector(multiple_ctr);
 COUNTERS_STATUS_OUT(47 downto 32) <= std_logic_vector(spikes_ctr);
 COUNTERS_STATUS_OUT(63 downto 48) <= std_logic_vector(spurious_ctr);
-
+COUNTERS_STATUS_OUT(79 downto 64) <= std_logic_vector(tmg_edge_ctr);
 ---------------------------------------------------------------------------
 -- Debug signals
 ---------------------------------------------------------------------------
index 8fc0741d786590850e16606da858ee5d4552741f..6082731941b7ca52228997204291e02cc585d3fe 100644 (file)
@@ -133,7 +133,7 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi
   signal timer_ticks             : std_logic_vector(1 downto 0);
   signal hub_ctrl_debug          : std_logic_vector(31 downto 0);
 
-
+  signal link_not_up             : std_logic;
   signal apl_stat                : std_logic_vector(31 downto 0);
 
   signal apl_data_in             : std_logic_vector(3*16-1 downto 0);
@@ -222,6 +222,9 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi
 
   signal wren_addr_fifo      : std_logic;
   signal wren_length_fifo    : std_logic;
+  signal df_data             : std_logic_vector(63 downto 0);
+  signal df_empty            : std_logic_vector(1 downto 0);
+  signal df_read             : std_logic_vector(1 downto 0);
 
 begin
 
@@ -433,7 +436,7 @@ begin
             if channel_address = 0 then
               bus_data_i <= x"0000" & reg_extended_trigger_information;
             else
-              bus_data_i <= x"10000000";
+              bus_data_i <= x"EE000000";
             end if;
           when x"1F" =>
             bus_data_i <= sender_status(channel_address*32+31 downto channel_address*32);
@@ -462,8 +465,12 @@ begin
             bus_data_i <= status_dma_core(127 downto 96);
           when x"78" =>
             bus_data_i <= status_dma_core(159 downto 128);
+          when x"E0" =>
+            bus_data_i <= df_data(31 downto 0);
+          when x"E1" =>
+            bus_data_i <= df_data(63 downto 32);
           when others         =>
-            bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19);
+            bus_data_i <= x"EE000000"; --"1000000000000000000" & CTRL(31 downto 19);
         end case;
     end process;
 
@@ -519,6 +526,9 @@ begin
       end if;
     end process;
 
+df_read(0) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e00" and bus_read_i = '1' else '0';
+df_read(1) <= '1' when BUS_ADDR_IN(15 downto 0) = x"0e01" and bus_read_i = '1' else '0';
+    
 --------------------------------
 -- connection to API
 --------------------------------
@@ -566,16 +576,17 @@ begin
 
       apl_read_in           <= (fifo_net_to_pci_read(3) or apl_read_dma) & fifo_net_to_pci_read(1) & fifo_net_to_pci_read(0);
       fifo_net_to_pci_empty  <= not (apl_dataready_out(2) & '0' & apl_dataready_out(1) & apl_dataready_out(0));
-      fifo_net_to_pci_dout(31 downto 0)   <= "0000000" & fifo_net_to_pci_valid_read(0) & "000000"
+      fifo_net_to_pci_dout(31 downto 0)   <= "000000" & (APL_RUN_OUT(0) or link_not_up) & fifo_net_to_pci_valid_read(0) & "000000"
                                             & apl_packet_num_out(2) & apl_packet_num_out(0) & apl_data_out(15 downto 0);
-      fifo_net_to_pci_dout(63 downto 32)  <= "0000000" & fifo_net_to_pci_valid_read(1) & "000000"
+      fifo_net_to_pci_dout(63 downto 32)  <= "000000" & (APL_RUN_OUT(1) or link_not_up) & fifo_net_to_pci_valid_read(1) & "000000"
                                             & apl_packet_num_out(5) & apl_packet_num_out(3) & apl_data_out(31 downto 16);
       fifo_net_to_pci_dout(95 downto 64)  <= (others => '0');
-      fifo_net_to_pci_dout(127 downto 96) <= "0000000" & fifo_net_to_pci_valid_read(3) & "000000"
+      fifo_net_to_pci_dout(127 downto 96) <= "000000" & (APL_RUN_OUT(2) or link_not_up) & fifo_net_to_pci_valid_read(3) & "000000"
                                             & apl_packet_num_out(8) & apl_packet_num_out(6) & apl_data_out(47 downto 32);
     end process;
 
-
+  link_not_up <= '1' when MED_STAT_OP_IN(2 downto 0) /= ERROR_OK else '0';
+               
   proc_fifo_readwrite : process(BUS_ADDR_IN, bus_read_i, channel_address, apl_dataready_out, fifo_net_to_pci_read)
     begin
       fifo_net_to_pci_valid_read(0) <= fifo_net_to_pci_read(0) and apl_dataready_out(0);
@@ -644,6 +655,10 @@ THE_DMA_CORE : dma_core
     RX_DWEN_IN           => RX_DWEN_IN,
     RX_DATA_IN           => RX_DATA_IN,
 
+    DEBUG_FIFO_DATA_OUT  => df_data,
+    DEBUG_FIFO_EMPTY_OUT => df_empty,
+    DEBUG_FIFO_READ_IN   => df_read,
+           
     STATUS_REG_OUT       => status_dma_core,
     DEBUG_OUT            => debug_dma_core
 
index 823daeeb2efa033a153c1e1662356a5106a6ae0a..1227956a1231e6b087a188b20d3ee32509c6f2e6 100644 (file)
@@ -153,7 +153,7 @@ entity trb_net16_endpoint_hades_full is
     IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
     STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
     STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);
-    STAT_TRIGGER_OUT          : out std_logic_vector (63 downto 0);
+    STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);
     DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)
     );
 end trb_net16_endpoint_hades_full;
@@ -257,7 +257,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
   signal got_timingless_trigger       : std_logic;
   signal trigger_number_match         : std_logic;
   signal buf_TIMER_TICKS_OUT          : std_logic_vector(1 downto 0);
-  signal timing_trigger_missing       : std_logic;
+--   signal timing_trigger_missing       : std_logic;
 
   signal buf_LVL1_VALID_TIMING_TRG_OUT    : std_logic;
   signal buf_LVL1_VALID_NOTIMING_TRG_OUT  : std_logic;
@@ -269,7 +269,7 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
   signal int_trg_reset             : std_logic;
   signal reset_trg_logic           : std_logic;
   signal stat_lvl1_handler         : std_logic_vector(63 downto 0);
-  signal stat_counters_lvl1_handler: std_logic_vector(63 downto 0);
+  signal stat_counters_lvl1_handler: std_logic_vector(79 downto 0);
   signal trg_invert_i              : std_logic;
   signal int_multiple_trg          : std_logic;
   signal int_lvl1_timeout_detected : std_logic;
@@ -286,13 +286,14 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full
   signal reg_timing_trigger : std_logic;
   signal trigger_timing_rising : std_logic;
   signal last_reg_timing_trigger : std_logic;
-  signal timing_trigger_missing_stat : std_logic;
+--   signal timing_trigger_missing_stat : std_logic;
 
   signal link_error_i            : std_logic;
   signal link_and_reset_status   : std_logic_vector(31 downto 0);
 
   signal make_trbnet_reset       : std_logic;
   signal last_make_trbnet_reset  : std_logic;
+  signal lvl1_tmg_trg_missing_flag : std_logic;
 
   component edge_to_pulse is
     port (
@@ -811,7 +812,7 @@ begin
     begin
       buf_COMMON_STAT_REG_IN               <= REGIO_COMMON_STAT_REG_IN;
       buf_COMMON_STAT_REG_IN(4)            <= stat_lvl1_handler(12);
-      buf_COMMON_STAT_REG_IN(8)            <= int_lvl1_missing_tmg_trg;
+      buf_COMMON_STAT_REG_IN(8)            <= lvl1_tmg_trg_missing_flag;
       buf_COMMON_STAT_REG_IN(13)           <= stat_lvl1_handler(7);
       buf_COMMON_STAT_REG_IN(15)           <= link_error_i;
       if REGIO_USE_1WIRE_INTERFACE = c_YES then
@@ -824,7 +825,8 @@ begin
       buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT;
       buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0);
       buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT;
-      buf_COMMON_STAT_REG_IN(255 downto 192) <= stat_counters_lvl1_handler;
+      buf_COMMON_STAT_REG_IN(271 downto 192) <= stat_counters_lvl1_handler;
+      buf_COMMON_STAT_REG_IN(287 downto 272) <= (others => '0');
     end process;
 
 
@@ -838,10 +840,16 @@ begin
           link_error_i <= '1';
         end if;
 
-        if LVL1_TRG_RECEIVED_OUT_falling = '1' then
-          timing_trigger_missing_stat <= timing_trigger_missing;
+        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
+          lvl1_tmg_trg_missing_flag <= '0';
+        elsif int_lvl1_missing_tmg_trg = '1' then
+          lvl1_tmg_trg_missing_flag <= '1';
         end if;
 
+--         if LVL1_TRG_RECEIVED_OUT_falling = '1' then
+--           timing_trigger_missing_stat <= timing_trigger_missing;
+--         end if;
+
         if make_trbnet_reset = '1' then
           link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';
         end if;
@@ -1064,5 +1072,7 @@ begin
   STAT_DEBUG_2(15 downto 12)     <= (others => '0');
   STAT_DEBUG_2(31 downto 16)     <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
 
+  STAT_TRIGGER_OUT               <= stat_counters_lvl1_handler;
+
 end architecture;
 
index e2740dcb7625c39535f221b81b2ad48979b081c1..7928776d4c26fc7e9c59ebfdfbae16427e17eccd 100644 (file)
@@ -133,7 +133,7 @@ entity trb_net16_endpoint_hades_full_handler is
     IOBUF_CTRL_GEN               : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
     STAT_ONEWIRE                 : out std_logic_vector (31 downto 0);
     STAT_ADDR_DEBUG              : out std_logic_vector (15 downto 0);
-    STAT_TRIGGER_OUT             : out std_logic_vector (63 downto 0);
+    STAT_TRIGGER_OUT             : out std_logic_vector (79 downto 0);
     DEBUG_LVL1_HANDLER_OUT       : out std_logic_vector (15 downto 0)
     );
 end entity;
@@ -622,13 +622,16 @@ begin
   TIME_SINCE_LAST_TRG_OUT        <= time_since_last_trg_i;
   TIME_TICKS_OUT                 <= time_ticks_i;
 
-  process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i)
+  process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)
     begin
       common_stat_reg_i(47 downto 0) <= REGIO_COMMON_STAT_REG_IN(47 downto 0);
       common_stat_reg_i(6)       <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6);
-      common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9);
-      common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10);
-      common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11);
+      common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);
+      common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);
+      common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11);
+      if common_ctrl_reg_i(4) = '1' then 
+        common_stat_reg_i(11 downto 9) <= "000";
+      end if;
       common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64);
     end process;
 
index cb76da8f303de092facfbdf57d7d73d856bf2f3b..4db9bbfbe4dd1816c8d319479777a9913c520e61 100644 (file)
@@ -214,6 +214,7 @@ begin
       SYN_PACKET_NUM_OUT => INIT_POOL_PACKET_NUM,
       SYN_READ_IN => INIT_POOL_READ
       );
+
   process(CLK)
     begin
       if rising_edge(CLK) then
index 6dc9477161dfc80095fb5232bb824e409cc5cc77..04f5345d822571a15578d003c40ea9466163e05c 100644 (file)
@@ -628,7 +628,7 @@ end component;
       IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');\r
       STAT_ONEWIRE              : out std_logic_vector (31 downto 0);\r
       STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);\r
-      STAT_TRIGGER_OUT             : out std_logic_vector (63 downto 0);      \r
+      STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);      \r
       DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)\r
       );\r
   end component;\r
@@ -758,7 +758,7 @@ end component;
       IOBUF_CTRL_GEN               : in  std_logic_vector (4*32-1 downto 0) := (others => '0');\r
       STAT_ONEWIRE                 : out std_logic_vector (31 downto 0);\r
       STAT_ADDR_DEBUG              : out std_logic_vector (15 downto 0);\r
-      STAT_TRIGGER_OUT             : out std_logic_vector (63 downto 0);      \r
+      STAT_TRIGGER_OUT             : out std_logic_vector (79 downto 0);      \r
       DEBUG_LVL1_HANDLER_OUT       : out std_logic_vector (15 downto 0)\r
       );\r
   end component;\r
@@ -1195,7 +1195,7 @@ end component;
       STATUS_OUT                   : out std_logic_vector (63 downto 0); -- bits for status registers\r
       TRG_ENABLE_IN                : in  std_logic;                      -- trigger enable flag\r
       TRG_INVERT_IN                : in  std_logic;                      -- trigger invert flag\r
-      COUNTERS_STATUS_OUT          : out std_logic_vector (63 downto 0);\r
+      COUNTERS_STATUS_OUT          : out std_logic_vector (79 downto 0);\r
       --Debug\r
       DEBUG_OUT                    : out std_logic_vector (15 downto 0)\r
     );\r
index b89763a82f9a84389798e555c813aec34bc5c954..7b35e5a901ea81d77714e8642fbb442e82661669 100644 (file)
@@ -111,10 +111,10 @@ package trb_net_std is
 
 --common registers
   --maximum: 4, because of regio implementation
-  constant std_COMSTATREG  : integer := 8;
+  constant std_COMSTATREG  : integer := 9;
   constant std_COMCTRLREG  : integer := 3;
     --needed address width for common registers
-  constant std_COMneededwidth : integer := 3;
+  constant std_COMneededwidth : integer := 4;
   constant c_REGIO_ADDRESS_WIDTH : integer := 16;
   constant c_REGIO_REGISTER_WIDTH : integer := 32;
   constant c_REGIO_REG_WIDTH : integer := 32;