signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0) := (others => '0');
- type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB);
+ type OUTPUT_SELECT is (HDR, DAT, TRM, PAD);
signal out_select: OUTPUT_SELECT;
signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0) := (others => '0');
signal combined_header_F0, combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0) := (others => '0');
case out_select is
when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header;
when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer;
+ when PAD => next_INT_MASTER_DATA_OUT <= (others => '0');
when others => next_INT_MASTER_DATA_OUT <= current_data;
end case;
end process;
next_INT_MASTER_DATAREADY_OUT <= sbuf_free and
((fifo_to_int_read_before or master_counter(2)) or --write data from fifo
(fifo_to_int_empty and not master_counter(2))); --fill with padding words
+ if fifo_to_int_empty = '1' then
+ out_select <= PAD;
+ end if;
if master_counter = c_F3 and fifo_to_int_empty = '1' and sbuf_free = '1' then
next_state_to_int <= SEND_TRAILER;
end if;