+++ /dev/null
-MODULE slv_spi_dpram\r
+++ /dev/null
--- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
--- Module Version: 7.1
---X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
-
--- Mon Aug 24 13:18:12 2009
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp2m;
-use ecp2m.components.all;
--- synopsys translate_on
-
-entity slv_spi_dpram is
- port (
- DataInA: in std_logic_vector(31 downto 0);
- DataInB: in std_logic_vector(7 downto 0);
- AddressA: in std_logic_vector(5 downto 0);
- AddressB: in std_logic_vector(7 downto 0);
- ClockA: in std_logic;
- ClockB: in std_logic;
- ClockEnA: in std_logic;
- ClockEnB: in std_logic;
- WrA: in std_logic;
- WrB: in std_logic;
- ResetA: in std_logic;
- ResetB: in std_logic;
- QA: out std_logic_vector(31 downto 0);
- QB: out std_logic_vector(7 downto 0));
-end slv_spi_dpram;
-
-architecture Structure of slv_spi_dpram is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KB
- -- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
- DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
- -- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute GSR : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute MEM_LPC_FILE of slv_spi_dpram_0_0_1 : label is "slv_spi_dpram.lpc";
- attribute MEM_INIT_FILE of slv_spi_dpram_0_0_1 : label is "";
- attribute CSDECODE_B of slv_spi_dpram_0_0_1 : label is "0b000";
- attribute CSDECODE_A of slv_spi_dpram_0_0_1 : label is "0b000";
- attribute WRITEMODE_B of slv_spi_dpram_0_0_1 : label is "NORMAL";
- attribute WRITEMODE_A of slv_spi_dpram_0_0_1 : label is "NORMAL";
- attribute GSR of slv_spi_dpram_0_0_1 : label is "DISABLED";
- attribute RESETMODE of slv_spi_dpram_0_0_1 : label is "SYNC";
- attribute REGMODE_B of slv_spi_dpram_0_0_1 : label is "NOREG";
- attribute REGMODE_A of slv_spi_dpram_0_0_1 : label is "NOREG";
- attribute DATA_WIDTH_B of slv_spi_dpram_0_0_1 : label is "4";
- attribute DATA_WIDTH_A of slv_spi_dpram_0_0_1 : label is "18";
- attribute MEM_LPC_FILE of slv_spi_dpram_0_1_0 : label is "slv_spi_dpram.lpc";
- attribute MEM_INIT_FILE of slv_spi_dpram_0_1_0 : label is "";
- attribute CSDECODE_B of slv_spi_dpram_0_1_0 : label is "0b000";
- attribute CSDECODE_A of slv_spi_dpram_0_1_0 : label is "0b000";
- attribute WRITEMODE_B of slv_spi_dpram_0_1_0 : label is "NORMAL";
- attribute WRITEMODE_A of slv_spi_dpram_0_1_0 : label is "NORMAL";
- attribute GSR of slv_spi_dpram_0_1_0 : label is "DISABLED";
- attribute RESETMODE of slv_spi_dpram_0_1_0 : label is "SYNC";
- attribute REGMODE_B of slv_spi_dpram_0_1_0 : label is "NOREG";
- attribute REGMODE_A of slv_spi_dpram_0_1_0 : label is "NOREG";
- attribute DATA_WIDTH_B of slv_spi_dpram_0_1_0 : label is "4";
- attribute DATA_WIDTH_A of slv_spi_dpram_0_1_0 : label is "18";
-
-begin
- -- component instantiation statements
- slv_spi_dpram_0_0_1: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
- DIA3=>DataInA(3), DIA4=>DataInA(8), DIA5=>DataInA(9),
- DIA6=>DataInA(10), DIA7=>DataInA(11), DIA8=>scuba_vlo,
- DIA9=>DataInA(16), DIA10=>DataInA(17), DIA11=>DataInA(18),
- DIA12=>DataInA(19), DIA13=>DataInA(24), DIA14=>DataInA(25),
- DIA15=>DataInA(26), DIA16=>DataInA(27), DIA17=>scuba_vlo,
- ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
- ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
- ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
- CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0),
- DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3),
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1),
- ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4),
- ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7),
- ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2),
- DOA3=>QA(3), DOA4=>QA(8), DOA5=>QA(9), DOA6=>QA(10),
- DOA7=>QA(11), DOA8=>open, DOA9=>QA(16), DOA10=>QA(17),
- DOA11=>QA(18), DOA12=>QA(19), DOA13=>QA(24), DOA14=>QA(25),
- DOA15=>QA(26), DOA16=>QA(27), DOA17=>open, DOB0=>QB(0),
- DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- slv_spi_dpram_0_1_0: DP16KB
- -- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
- REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
- DATA_WIDTH_A=> 18)
- -- synopsys translate_on
- port map (DIA0=>DataInA(4), DIA1=>DataInA(5), DIA2=>DataInA(6),
- DIA3=>DataInA(7), DIA4=>DataInA(12), DIA5=>DataInA(13),
- DIA6=>DataInA(14), DIA7=>DataInA(15), DIA8=>scuba_vlo,
- DIA9=>DataInA(20), DIA10=>DataInA(21), DIA11=>DataInA(22),
- DIA12=>DataInA(23), DIA13=>DataInA(28), DIA14=>DataInA(29),
- DIA15=>DataInA(30), DIA16=>DataInA(31), DIA17=>scuba_vlo,
- ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
- ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
- ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
- CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(4),
- DIB1=>DataInB(5), DIB2=>DataInB(6), DIB3=>DataInB(7),
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1),
- ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4),
- ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7),
- ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
- CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
- RSTB=>ResetB, DOA0=>QA(4), DOA1=>QA(5), DOA2=>QA(6),
- DOA3=>QA(7), DOA4=>QA(12), DOA5=>QA(13), DOA6=>QA(14),
- DOA7=>QA(15), DOA8=>open, DOA9=>QA(20), DOA10=>QA(21),
- DOA11=>QA(22), DOA12=>QA(23), DOA13=>QA(28), DOA14=>QA(29),
- DOA15=>QA(30), DOA16=>QA(31), DOA17=>open, DOB0=>QB(4),
- DOB1=>QB(5), DOB2=>QB(6), DOB3=>QB(7), DOB4=>open,
- DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
- DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp2m;
-configuration Structure_CON of slv_spi_dpram is
- for Structure
- for all:VHI use entity ecp2m.VHI(V); end for;
- for all:VLO use entity ecp2m.VLO(V); end for;
- for all:DP16KB use entity ecp2m.DP16KB(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
--- /dev/null
+MODULE spi_dpram_32_to_8\r
CoreStatus=Demo\r
CoreName=RAM_DP_TRUE\r
CoreRevision=7.1\r
-ModuleName=slv_spi_dpram\r
+ModuleName=spi_dpram_32_to_8\r
SourceFormat=VHDL\r
ParameterFileVersion=1.0\r
Date=08/24/2009\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 7.1
+--X:\Programme\ispTOOLS_72\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -cascade -1 -e
+
+-- Mon Aug 24 13:18:12 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity spi_dpram_32_to_8 is
+ port (
+ DataInA: in std_logic_vector(31 downto 0);
+ DataInB: in std_logic_vector(7 downto 0);
+ AddressA: in std_logic_vector(5 downto 0);
+ AddressB: in std_logic_vector(7 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(31 downto 0);
+ QB: out std_logic_vector(7 downto 0));
+end entity;
+
+architecture Structure of spi_dpram_32_to_8 is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of spi_dpram_32_to_8_0_0_1 : label is "spi_dpram_32_to_8.lpc";
+ attribute MEM_INIT_FILE of spi_dpram_32_to_8_0_0_1 : label is "";
+ attribute CSDECODE_B of spi_dpram_32_to_8_0_0_1 : label is "0b000";
+ attribute CSDECODE_A of spi_dpram_32_to_8_0_0_1 : label is "0b000";
+ attribute WRITEMODE_B of spi_dpram_32_to_8_0_0_1 : label is "NORMAL";
+ attribute WRITEMODE_A of spi_dpram_32_to_8_0_0_1 : label is "NORMAL";
+ attribute GSR of spi_dpram_32_to_8_0_0_1 : label is "DISABLED";
+ attribute RESETMODE of spi_dpram_32_to_8_0_0_1 : label is "SYNC";
+ attribute REGMODE_B of spi_dpram_32_to_8_0_0_1 : label is "NOREG";
+ attribute REGMODE_A of spi_dpram_32_to_8_0_0_1 : label is "NOREG";
+ attribute DATA_WIDTH_B of spi_dpram_32_to_8_0_0_1 : label is "4";
+ attribute DATA_WIDTH_A of spi_dpram_32_to_8_0_0_1 : label is "18";
+ attribute MEM_LPC_FILE of spi_dpram_32_to_8_0_1_0 : label is "spi_dpram_32_to_8.lpc";
+ attribute MEM_INIT_FILE of spi_dpram_32_to_8_0_1_0 : label is "";
+ attribute CSDECODE_B of spi_dpram_32_to_8_0_1_0 : label is "0b000";
+ attribute CSDECODE_A of spi_dpram_32_to_8_0_1_0 : label is "0b000";
+ attribute WRITEMODE_B of spi_dpram_32_to_8_0_1_0 : label is "NORMAL";
+ attribute WRITEMODE_A of spi_dpram_32_to_8_0_1_0 : label is "NORMAL";
+ attribute GSR of spi_dpram_32_to_8_0_1_0 : label is "DISABLED";
+ attribute RESETMODE of spi_dpram_32_to_8_0_1_0 : label is "SYNC";
+ attribute REGMODE_B of spi_dpram_32_to_8_0_1_0 : label is "NOREG";
+ attribute REGMODE_A of spi_dpram_32_to_8_0_1_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of spi_dpram_32_to_8_0_1_0 : label is "4";
+ attribute DATA_WIDTH_A of spi_dpram_32_to_8_0_1_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ spi_dpram_32_to_8_0_0_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
+ DIA3=>DataInA(3), DIA4=>DataInA(8), DIA5=>DataInA(9),
+ DIA6=>DataInA(10), DIA7=>DataInA(11), DIA8=>scuba_vlo,
+ DIA9=>DataInA(16), DIA10=>DataInA(17), DIA11=>DataInA(18),
+ DIA12=>DataInA(19), DIA13=>DataInA(24), DIA14=>DataInA(25),
+ DIA15=>DataInA(26), DIA16=>DataInA(27), DIA17=>scuba_vlo,
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
+ ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
+ ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
+ ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
+ CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0),
+ DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3),
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1),
+ ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4),
+ ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7),
+ ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
+ ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2),
+ DOA3=>QA(3), DOA4=>QA(8), DOA5=>QA(9), DOA6=>QA(10),
+ DOA7=>QA(11), DOA8=>open, DOA9=>QA(16), DOA10=>QA(17),
+ DOA11=>QA(18), DOA12=>QA(19), DOA13=>QA(24), DOA14=>QA(25),
+ DOA15=>QA(26), DOA16=>QA(27), DOA17=>open, DOB0=>QB(0),
+ DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>open,
+ DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ spi_dpram_32_to_8_0_1_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>DataInA(4), DIA1=>DataInA(5), DIA2=>DataInA(6),
+ DIA3=>DataInA(7), DIA4=>DataInA(12), DIA5=>DataInA(13),
+ DIA6=>DataInA(14), DIA7=>DataInA(15), DIA8=>scuba_vlo,
+ DIA9=>DataInA(20), DIA10=>DataInA(21), DIA11=>DataInA(22),
+ DIA12=>DataInA(23), DIA13=>DataInA(28), DIA14=>DataInA(29),
+ DIA15=>DataInA(30), DIA16=>DataInA(31), DIA17=>scuba_vlo,
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
+ ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
+ ADA9=>AddressA(5), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
+ ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>ClockEnA,
+ CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(4),
+ DIB1=>DataInB(5), DIB2=>DataInB(6), DIB3=>DataInB(7),
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>AddressB(0), ADB3=>AddressB(1),
+ ADB4=>AddressB(2), ADB5=>AddressB(3), ADB6=>AddressB(4),
+ ADB7=>AddressB(5), ADB8=>AddressB(6), ADB9=>AddressB(7),
+ ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
+ ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>ResetB, DOA0=>QA(4), DOA1=>QA(5), DOA2=>QA(6),
+ DOA3=>QA(7), DOA4=>QA(12), DOA5=>QA(13), DOA6=>QA(14),
+ DOA7=>QA(15), DOA8=>open, DOA9=>QA(20), DOA10=>QA(21),
+ DOA11=>QA(22), DOA12=>QA(23), DOA13=>QA(28), DOA14=>QA(29),
+ DOA15=>QA(30), DOA16=>QA(31), DOA17=>open, DOB0=>QB(4),
+ DOB1=>QB(5), DOB2=>QB(6), DOB3=>QB(7), DOB4=>open,
+ DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of spi_dpram_32_to_8 is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
+++ /dev/null
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-\r
-entity slv_spi_memory is\r
-port( CLK_IN : in std_logic;\r
- CLEAR_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_ADDR_IN : in std_logic_vector(5 downto 0);\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- state machine connections\r
- BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
- BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_WE_IN : in std_logic; \r
- -- Status lines\r
- STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of slv_spi_memory is\r
-\r
--- Components\r
- component slv_spi_dpram is\r
- port( DATAINA : in std_logic_vector(31 downto 0); \r
- DATAINB : in std_logic_vector(7 downto 0); \r
- ADDRESSA : in std_logic_vector(5 downto 0); \r
- ADDRESSB : in std_logic_vector(7 downto 0); \r
- CLOCKA : in std_logic; \r
- CLOCKB : in std_logic; \r
- CLOCKENA : in std_logic; \r
- CLOCKENB : in std_logic; \r
- WRA : in std_logic; \r
- WRB : in std_logic; \r
- RESETA : in std_logic; \r
- RESETB : in std_logic; \r
- QA : out std_logic_vector(31 downto 0); \r
- QB : out std_logic_vector(7 downto 0)\r
- );\r
- end component;\r
-\r
--- Signals\r
- type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- -- slave bus signals\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
- signal wr_data : std_logic_vector(15 downto 0);\r
- signal wr_we : std_logic;\r
- signal buf_slv_data_out : std_logic_vector(31 downto 0);\r
-\r
- signal onewire_bsm : std_logic_vector(7 downto 0);\r
-\r
-begin\r
-\r
--- Fake\r
-stat(63 downto 0) <= (others => '0');\r
-\r
----------------------------------------------------------\r
--- Statemachine --\r
----------------------------------------------------------\r
--- State memory process\r
-STATE_MEM: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- slv_ack <= slv_ack_x;\r
- store_wr <= store_wr_x;\r
- store_rd <= store_rd_x;\r
- end if;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- Transition matrix\r
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in )\r
-begin\r
- NEXT_STATE <= SLEEP;\r
- slv_ack_x <= '0';\r
- store_wr_x <= '0';\r
- store_rd_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP => if ( (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_RDY;\r
- store_rd_x <= '1';\r
- elsif( (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_RDY;\r
- store_wr_x <= '1';\r
- else \r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- slv_ack_x <= '1';\r
- else\r
- NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- slv_ack_x <= '1';\r
- else\r
- NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
- end case;\r
-end process TRANSFORM;\r
-\r
-\r
----------------------------------------------------------\r
--- data handling --\r
----------------------------------------------------------\r
-\r
-THE_SLV_SPI_DPRAM: slv_spi_dpram\r
-port map( DATAINA => slv_data_in,\r
- ADDRESSA => slv_addr_in,\r
- CLOCKA => clk_in,\r
- CLOCKENA => '1',\r
- WRA => store_wr,\r
- RESETA => reset_in,\r
- QA => buf_slv_data_out,\r
- -- B side is state machine\r
- DATAINB => bram_rd_d_in,\r
- ADDRESSB => bram_addr_in,\r
- CLOCKB => clk_in,\r
- CLOCKENB => '1',\r
- WRB => bram_we_in,\r
- RESETB => reset_in,\r
- QB => bram_wr_d_out\r
- );\r
-\r
--- output signals\r
-slv_data_out <= buf_slv_data_out;\r
-slv_ack_out <= slv_ack;\r
-\r
-end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+\r
+entity spi_databus_memory is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- state machine connections\r
+ BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WE_IN : in std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of spi_databus_memory is\r
+\r
+-- Components\r
+ component spi_dpram is\r
+ port(\r
+ DATAINA : in std_logic_vector(31 downto 0);\r
+ DATAINB : in std_logic_vector(7 downto 0);\r
+ ADDRESSA : in std_logic_vector(5 downto 0);\r
+ ADDRESSB : in std_logic_vector(7 downto 0);\r
+ CLOCKA : in std_logic;\r
+ CLOCKB : in std_logic;\r
+ CLOCKENA : in std_logic;\r
+ CLOCKENB : in std_logic;\r
+ WRA : in std_logic;\r
+ WRB : in std_logic;\r
+ RESETA : in std_logic;\r
+ RESETB : in std_logic;\r
+ QA : out std_logic_vector(31 downto 0);\r
+ QB : out std_logic_vector(7 downto 0)\r
+ );\r
+ end component;\r
+\r
+-- Signals\r
+ type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ -- slave bus signals\r
+ signal BUS_ack_x : std_logic;\r
+ signal BUS_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+\r
+ signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
+ signal wr_data : std_logic_vector(15 downto 0);\r
+ signal wr_we : std_logic;\r
+ signal buf_BUS_data_out : std_logic_vector(31 downto 0);\r
+\r
+ signal onewire_bsm : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+---------------------------------------------------------\r
+-- Debugging --\r
+---------------------------------------------------------\r
+stat(63 downto 0) <= (others => '0');\r
+\r
+---------------------------------------------------------\r
+-- Statemachine --\r
+---------------------------------------------------------\r
+ STATE_MEM: process( clk_in)\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ BUS_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ BUS_ack <= BUS_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+-- Transition matrix\r
+ TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in )\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ BUS_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP =>\r
+ if ( (BUS_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (BUS_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+\r
+ when RD_RDY =>\r
+ NEXT_STATE <= RD_ACK;\r
+\r
+ when WR_RDY =>\r
+ NEXT_STATE <= WR_ACK;\r
+\r
+ when RD_ACK =>\r
+ if( BUS_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ BUS_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ BUS_ack_x <= '1';\r
+ end if;\r
+\r
+ when WR_ACK =>\r
+ if( BUS_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ BUS_ack_x <= '1';\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ BUS_ack_x <= '1';\r
+ end if;\r
+\r
+ when DONE =>\r
+ NEXT_STATE <= SLEEP;\r
+\r
+ when others =>\r
+ NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
+\r
+\r
+---------------------------------------------------------\r
+-- data handling --\r
+---------------------------------------------------------\r
+\r
+THE_BUS_SPI_DPRAM: spi_dpram_32_to_8\r
+ port map(\r
+ DATAINA => BUS_data_in,\r
+ ADDRESSA => BUS_addr_in,\r
+ CLOCKA => clk_in,\r
+ CLOCKENA => '1',\r
+ WRA => store_wr,\r
+ RESETA => reset_in,\r
+ QA => buf_BUS_data_out,\r
+ -- B side is state machine\r
+ DATAINB => bram_rd_d_in,\r
+ ADDRESSB => bram_addr_in,\r
+ CLOCKB => clk_in,\r
+ CLOCKENB => '1',\r
+ WRB => bram_we_in,\r
+ RESETB => reset_in,\r
+ QB => bram_wr_d_out\r
+ );\r
+\r
+-- output signals\r
+BUS_data_out <= buf_BUS_data_out;\r
+BUS_ack_out <= BUS_ack;\r
+\r
+end Behavioral;\r
use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
\r
library work;\r
-use work.adcmv2_components.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
\r
entity spi_master is\r
-port( CLK_IN : in std_logic;\r
- CLEAR_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_ADDR_IN : in std_logic_vector(0 downto 0);\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- -- BRAM for read/write data\r
- BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WE_OUT : out std_logic;\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ -- Slave bus\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_BUSY_OUT : out std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ -- SPI connections\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ -- BRAM for read/write data\r
+ BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : out std_logic;\r
+ -- Status lines\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ );\r
end entity;\r
\r
architecture Behavioral of spi_master is\r
\r
--- Modules\r
- -- are now in adcmv2_components.vhd\r
\r
-- Signals\r
- type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
- signal status_data : std_logic_vector(31 downto 0);\r
- signal spi_busy : std_logic;\r
- \r
- signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL\r
- signal reg_status_data : std_logic_vector(31 downto 0); -- MAX\r
- \r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- readback\r
- \r
- signal spi_bsm : std_logic_vector(7 downto 0);\r
-\r
- signal spi_start_x : std_logic;\r
- signal spi_start : std_logic;\r
- \r
- -- State machine signals\r
- signal slv_busy_x : std_logic;\r
- signal slv_busy : std_logic;\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+ type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
+ signal CURRENT_STATE, NEXT_STATE: STATES;\r
+\r
+ signal status_data : std_logic_vector(31 downto 0);\r
+ signal spi_busy : std_logic;\r
+\r
+ signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL\r
+ signal reg_status_data : std_logic_vector(31 downto 0); -- MAX\r
+\r
+ signal reg_BUS_data_out : std_logic_vector(31 downto 0); -- readback\r
+\r
+ signal spi_bsm : std_logic_vector(7 downto 0);\r
+\r
+ signal spi_start_x : std_logic;\r
+ signal spi_start : std_logic;\r
+\r
+ -- State machine signals\r
+ signal BUS_busy_x : std_logic;\r
+ signal BUS_busy : std_logic;\r
+ signal BUS_ack_x : std_logic;\r
+ signal BUS_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
\r
begin\r
\r
---------------------------------------------------------\r
\r
THE_SPI_SLIM: spi_slim\r
-port map( SYSCLK => clk_in,\r
- CLEAR => clear_in,\r
- RESET => reset_in,\r
- -- Command interface\r
- START_IN => spi_start, -- not really nice, but should work\r
- BUSY_OUT => spi_busy,\r
- CMD_IN => reg_ctrl_data(31 downto 24),\r
- ADH_IN => reg_ctrl_data(23 downto 16),\r
- ADM_IN => reg_ctrl_data(15 downto 8),\r
- ADL_IN => reg_ctrl_data(7 downto 0),\r
- MAX_IN => reg_status_data(31 downto 24),\r
- TXDATA_IN => bram_wr_d_in,\r
- TX_RD_OUT => open, -- not needed\r
- RXDATA_OUT => bram_rd_d_out,\r
- RX_WR_OUT => bram_we_out,\r
- TX_RX_A_OUT => bram_a_out,\r
- -- SPI interface\r
- SPI_SCK_OUT => spi_sck_out,\r
- SPI_CS_OUT => spi_cs_out,\r
- SPI_SDI_IN => spi_sdi_in,\r
- SPI_SDO_OUT => spi_sdo_out,\r
- -- DEBUG\r
- CLK_EN_OUT => open, -- not needed\r
- BSM_OUT => spi_bsm,\r
- DEBUG_OUT => open -- BUG\r
- );\r
+ port map(\r
+ SYSCLK => clk_in,\r
+ RESET => reset_in,\r
+ -- Command interface\r
+ START_IN => spi_start, -- not really nice, but should work\r
+ BUSY_OUT => spi_busy,\r
+ CMD_IN => reg_ctrl_data(31 downto 24),\r
+ ADH_IN => reg_ctrl_data(23 downto 16),\r
+ ADM_IN => reg_ctrl_data(15 downto 8),\r
+ ADL_IN => reg_ctrl_data(7 downto 0),\r
+ MAX_IN => reg_status_data(31 downto 24),\r
+ TXDATA_IN => bram_wr_d_in,\r
+ TX_RD_OUT => open, -- not needed\r
+ RXDATA_OUT => bram_rd_d_out,\r
+ RX_WR_OUT => bram_we_out,\r
+ TX_RX_A_OUT => bram_a_out,\r
+ -- SPI interface\r
+ SPI_SCK_OUT => spi_sck_out,\r
+ SPI_CS_OUT => spi_cs_out,\r
+ SPI_SDI_IN => spi_sdi_in,\r
+ SPI_SDO_OUT => spi_sdo_out,\r
+ -- DEBUG\r
+ CLK_EN_OUT => open, -- not needed\r
+ BSM_OUT => spi_bsm,\r
+ DEBUG_OUT => open -- BUG\r
+ );\r
\r
---------------------------------------------------------\r
-- Statemachine --\r
---------------------------------------------------------\r
--- State memory process\r
-STATE_MEM: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_busy <= '0';\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_busy <= '0';\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- slv_busy <= slv_busy_x;\r
- slv_ack <= slv_ack_x;\r
- store_wr <= store_wr_x;\r
- store_rd <= store_rd_x;\r
- end if;\r
- end if;\r
-end process STATE_MEM;\r
-\r
--- Transition matrix\r
-TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, spi_busy )\r
-begin\r
- NEXT_STATE <= SLEEP;\r
- slv_busy_x <= '0';\r
- slv_ack_x <= '0';\r
- store_wr_x <= '0';\r
- store_rd_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP => if ( (spi_busy = '0') and (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_RDY;\r
- store_rd_x <= '1';\r
- elsif( (spi_busy = '0') and (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_RDY;\r
- store_wr_x <= '1';\r
- elsif( (spi_busy = '1') and (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_BSY;\r
- slv_busy_x <= '1';\r
- elsif( (spi_busy = '1') and (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_BSY;\r
- slv_busy_x <= '1';\r
- else \r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RD_RDY => NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
- when WR_RDY => NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
- when RD_ACK => if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when WR_ACK => if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
- when RD_BSY => if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_BSY;\r
- slv_busy_x <= '1';\r
- end if;\r
- when WR_BSY => if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_BSY;\r
- slv_busy_x <= '1';\r
- end if;\r
- when DONE => NEXT_STATE <= SLEEP;\r
- \r
- when others => NEXT_STATE <= SLEEP;\r
- end case;\r
-end process TRANSFORM;\r
+ STATE_MEM: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ BUS_busy <= '0';\r
+ BUS_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ BUS_busy <= BUS_busy_x;\r
+ BUS_ack <= BUS_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+ end process STATE_MEM;\r
+\r
+ TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in, spi_busy )\r
+ begin\r
+ NEXT_STATE <= SLEEP;\r
+ BUS_busy_x <= '0';\r
+ BUS_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP =>\r
+ if ( (spi_busy = '0') and (BUS_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (spi_busy = '0') and (BUS_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (spi_busy = '1') and (BUS_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY;\r
+ BUS_busy_x <= '1';\r
+ elsif( (spi_busy = '1') and (BUS_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY;\r
+ BUS_busy_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY =>\r
+ NEXT_STATE <= RD_ACK;\r
+ BUS_ack_x <= '1';\r
+ when WR_RDY =>\r
+ NEXT_STATE <= WR_ACK;\r
+ BUS_ack_x <= '1';\r
+ when RD_ACK =>\r
+ if( BUS_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_ACK;\r
+ BUS_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK =>\r
+ if( BUS_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_ACK;\r
+ BUS_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY =>\r
+ if( BUS_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ BUS_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY =>\r
+ if( BUS_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ BUS_busy_x <= '1';\r
+ end if;\r
+ when DONE =>\r
+ NEXT_STATE <= SLEEP;\r
+\r
+ when others =>\r
+ NEXT_STATE <= SLEEP;\r
+ end case;\r
+ end process TRANSFORM;\r
\r
---------------------------------------------------------\r
-- data handling --\r
---------------------------------------------------------\r
\r
-- register write\r
-THE_WRITE_REG_PROC: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- reg_ctrl_data <= (others => '0');\r
- reg_status_data <= (others => '0');\r
- spi_start <= '0';\r
- elsif( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- reg_ctrl_data <= (others => '0');\r
- reg_status_data <= (others => '0');\r
- spi_start <= '0';\r
- elsif( (store_wr = '1') and (slv_addr_in(0) = '0') ) then\r
- reg_ctrl_data <= slv_data_in;\r
- elsif( (store_wr = '1') and (slv_addr_in(0) = '1') ) then\r
- reg_status_data <= slv_data_in;\r
- end if;\r
- spi_start <= spi_start_x;\r
- end if;\r
-end process THE_WRITE_REG_PROC;\r
-\r
-spi_start_x <= '1' when ( (store_wr = '1') and (slv_addr_in(0) = '0') ) else '0';\r
+THE_WRITE_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_ctrl_data <= (others => '0');\r
+ reg_status_data <= (others => '0');\r
+ spi_start <= '0';\r
+ elsif( (store_wr = '1') and (BUS_addr_in(0) = '0') ) then\r
+ reg_ctrl_data <= BUS_data_in;\r
+ elsif( (store_wr = '1') and (BUS_addr_in(0) = '1') ) then\r
+ reg_status_data <= BUS_data_in;\r
+ end if;\r
+ spi_start <= spi_start_x;\r
+ end if;\r
+ end process THE_WRITE_REG_PROC;\r
+\r
+spi_start_x <= '1' when ( (store_wr = '1') and (BUS_addr_in(0) = '0') ) else '0';\r
\r
-- register read\r
-THE_READ_REG_PROC: process( clk_in, clear_in )\r
-begin\r
- if( clear_in = '1' ) then\r
- reg_slv_data_out <= (others => '0');\r
- elsif( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- reg_slv_data_out <= (others => '0');\r
- elsif( (store_rd = '1') and (slv_addr_in(0) = '0') ) then\r
- reg_slv_data_out <= reg_ctrl_data;\r
- elsif( (store_rd = '1') and (slv_addr_in(0) = '1') ) then\r
- reg_slv_data_out(31 downto 24) <= reg_status_data(31 downto 24);\r
- reg_slv_data_out(23 downto 16) <= x"00";\r
- reg_slv_data_out(15 downto 8) <= x"00";\r
- reg_slv_data_out(7 downto 0) <= spi_bsm;\r
- end if;\r
- end if;\r
-end process THE_READ_REG_PROC;\r
+THE_READ_REG_PROC: process( clk_in )\r
+ begin\r
+ if( rising_edge(clk_in) ) then\r
+ if ( reset_in = '1' ) then\r
+ reg_BUS_data_out <= (others => '0');\r
+ elsif( (store_rd = '1') and (BUS_addr_in(0) = '0') ) then\r
+ reg_BUS_data_out <= reg_ctrl_data;\r
+ elsif( (store_rd = '1') and (BUS_addr_in(0) = '1') ) then\r
+ reg_BUS_data_out(31 downto 24) <= reg_status_data(31 downto 24);\r
+ reg_BUS_data_out(23 downto 16) <= x"00";\r
+ reg_BUS_data_out(15 downto 8) <= x"00";\r
+ reg_BUS_data_out(7 downto 0) <= spi_bsm;\r
+ end if;\r
+ end if;\r
+ end process THE_READ_REG_PROC;\r
\r
-- debug signals\r
status_data(31 downto 24) <= spi_bsm;\r
status_data(22 downto 0) <= (others => '0');\r
\r
-- output signals\r
-slv_ack_out <= slv_ack;\r
-slv_busy_out <= slv_busy;\r
-slv_data_out <= reg_slv_data_out;\r
+BUS_ack_out <= BUS_ack;\r
+BUS_busy_out <= BUS_busy;\r
+BUS_data_out <= reg_BUS_data_out;\r
stat <= status_data;\r
\r
end Behavioral;\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
\r
-- missing: end of PP/RDCMD by data_done signal.\r
\r
entity spi_slim is\r
- port( SYSCLK : in std_logic; -- 100MHz sysclock\r
- CLEAR : in std_logic; -- asynchronous reset\r
- RESET : in std_logic; -- synchronous reset\r
- -- Command interface\r
- START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
- CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
- ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
- ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
- ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
- MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
- TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next \r
- TX_RD_OUT : out std_logic;\r
- RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
- RX_WR_OUT : out std_logic;\r
- TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
- -- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- -- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
- );\r
-end spi_slim;\r
+ port(\r
+ SYSCLK : in std_logic; -- 100MHz sysclock\r
+ RESET : in std_logic; -- synchronous reset\r
+ -- Command interface\r
+ START_IN : in std_logic; -- one start pulse\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
+ ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
+ ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
+ ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
+ MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
+ TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
+ TX_RD_OUT : out std_logic;\r
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
+ RX_WR_OUT : out std_logic;\r
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
+ -- SPI interface\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ -- DEBUG\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+end entity;\r
\r
architecture Behavioral of spi_slim is\r
\r
-- new clock divider\r
-signal div_counter : std_logic_vector(1 downto 0);\r
-signal div_done_x : std_logic;\r
-signal div_done : std_logic; -- same as clk_en\r
-signal clk_en : std_logic; -- same as div_done\r
+signal div_counter : std_logic_vector(1 downto 0);\r
+signal div_done_x : std_logic;\r
+signal div_done : std_logic; -- same as clk_en\r
+signal clk_en : std_logic; -- same as div_done\r
\r
-- Statemachine signals\r
type state_t is (IDLE,CSL,TXCMD,TXADD_H,TXADD_M,TXADD_L,TXDATA,RXDATA,\r
- WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH);\r
-signal STATE, NEXT_STATE : state_t;\r
-\r
-signal rx_ena_x : std_logic;\r
-signal rx_ena : std_logic;\r
-signal tx_ena_x : std_logic;\r
-signal tx_ena : std_logic;\r
-signal busy_x : std_logic;\r
-signal busy : std_logic;\r
-signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
-signal spi_cs : std_logic;\r
-signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
-signal spi_sck : std_logic;\r
-signal tx_load_x : std_logic; -- load TX shift register\r
-signal tx_load : std_logic;\r
-signal tx_done_x : std_logic; -- one memory byte sent\r
-signal tx_done : std_logic;\r
-signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
-signal tx_sel : std_logic_vector(2 downto 0);\r
-signal rx_store_x : std_logic; -- store RX shift register\r
-signal rx_store : std_logic;\r
-signal rx_complete : std_logic;\r
-signal rst_addr_x : std_logic; -- reset address counter\r
-signal rst_addr : std_logic;\r
-\r
-signal inc_addr_rx_x : std_logic;\r
-signal inc_addr_rx : std_logic;\r
-signal inc_addr_tx_x : std_logic;\r
-signal inc_addr_tx : std_logic;\r
-signal ce_addr_x : std_logic;\r
-signal ce_addr : std_logic;\r
-\r
-signal addr_ctr : std_logic_vector(7 downto 0);\r
-signal data_done_x : std_logic;\r
-signal data_done : std_logic_vector(2 downto 0);\r
-\r
-signal last_tx_bit_x : std_logic;\r
-signal last_tx_bit : std_logic;\r
-signal is_data_x : std_logic;\r
-signal is_data : std_logic;\r
+ WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH);\r
+signal STATE, NEXT_STATE : state_t;\r
+\r
+signal rx_ena_x : std_logic;\r
+signal rx_ena : std_logic;\r
+signal tx_ena_x : std_logic;\r
+signal tx_ena : std_logic;\r
+signal busy_x : std_logic;\r
+signal busy : std_logic;\r
+signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
+signal spi_cs : std_logic;\r
+signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
+signal spi_sck : std_logic;\r
+signal tx_load_x : std_logic; -- load TX shift register\r
+signal tx_load : std_logic;\r
+signal tx_done_x : std_logic; -- one memory byte sent\r
+signal tx_done : std_logic;\r
+signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
+signal tx_sel : std_logic_vector(2 downto 0);\r
+signal rx_store_x : std_logic; -- store RX shift register\r
+signal rx_store : std_logic;\r
+signal rx_complete : std_logic;\r
+signal rst_addr_x : std_logic; -- reset address counter\r
+signal rst_addr : std_logic;\r
+\r
+signal inc_addr_rx_x : std_logic;\r
+signal inc_addr_rx : std_logic;\r
+signal inc_addr_tx_x : std_logic;\r
+signal inc_addr_tx : std_logic;\r
+signal ce_addr_x : std_logic;\r
+signal ce_addr : std_logic;\r
+\r
+signal addr_ctr : std_logic_vector(7 downto 0);\r
+signal data_done_x : std_logic;\r
+signal data_done : std_logic_vector(2 downto 0);\r
+\r
+signal last_tx_bit_x : std_logic;\r
+signal last_tx_bit : std_logic;\r
+signal is_data_x : std_logic;\r
+signal is_data : std_logic;\r
\r
-- debug signals\r
-signal bsm_x : std_logic_vector(7 downto 0);\r
-signal debug_x : std_logic_vector(31 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal debug_x : std_logic_vector(31 downto 0);\r
\r
-signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
-signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal max_int : std_logic_vector(7 downto 0);\r
+signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
+signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal max_int : std_logic_vector(7 downto 0);\r
\r
-- transmitter\r
-signal tx_sreg : std_logic_vector(7 downto 0);\r
-signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
-signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
+signal tx_sreg : std_logic_vector(7 downto 0);\r
+signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
+signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
\r
-- receiver\r
-signal rx_sreg : std_logic_vector(7 downto 0);\r
-signal rx_ready_set : std_logic;\r
-signal rx_bit_cnt_clr : std_logic;\r
-signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
+signal rx_sreg : std_logic_vector(7 downto 0);\r
+signal rx_ready_set : std_logic;\r
+signal rx_bit_cnt_clr : std_logic;\r
+signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
\r
-signal rd_data : std_logic;\r
-signal rd_data1 : std_logic;\r
-signal rd_data2 : std_logic;\r
+signal rd_data : std_logic;\r
+signal rd_data1 : std_logic;\r
+signal rd_data2 : std_logic;\r
\r
\r
\r
-- registers\r
-signal rx_data : std_logic_vector(7 downto 0);\r
+signal rx_data : std_logic_vector(7 downto 0);\r
\r
-- FLASH commands\r
-- single byte commands\r
-constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute\r
-constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD \r
-constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
-constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
-constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD \r
-constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
+constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute\r
+constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD\r
+constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
+constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
+constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD\r
+constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
\r
-constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
-constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
+constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
+constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
\r
-constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
+constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
\r
-constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
-constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
+constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
+constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
+constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
+constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
+constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
\r
-constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
-constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
-constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
+constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
+constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
+constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
\r
\r
begin\r
debug_x(6) <= tx_done;\r
debug_x(5) <= tx_load;\r
debug_x(4) <= tx_ena;\r
-debug_x(3) <= is_data; \r
+debug_x(3) <= is_data;\r
debug_x(2 downto 0) <= tx_sel;\r
\r
\r
-----------------------------------------------------------\r
--- \r
+--\r
-----------------------------------------------------------\r
\r
-----------------------------------------------------------\r
-- SPI clock generator\r
-----------------------------------------------------------\r
-THE_CLOCK_DIVIDER: process(clear,sysclk)\r
+THE_CLOCK_DIVIDER: process(sysclk)\r
begin\r
- if( clear = '1' ) then\r
- div_counter <= (others => '0');\r
- div_done <= '0';\r
- spi_sck <= '0';\r
- elsif( rising_edge(sysclk) ) then\r
- if( reset = '1' ) then\r
- div_counter <= (others => '0');\r
- div_done <= '0';\r
- spi_sck <= '0';\r
- else\r
- div_counter <= div_counter + 1;\r
- div_done <= div_done_x;\r
- spi_sck <= spi_sck_x;\r
- end if;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if( reset = '1' ) then\r
+ div_counter <= (others => '0');\r
+ div_done <= '0';\r
+ spi_sck <= '0';\r
+ else\r
+ div_counter <= div_counter + 1;\r
+ div_done <= div_done_x;\r
+ spi_sck <= spi_sck_x;\r
+ end if;\r
+ end if;\r
end process THE_CLOCK_DIVIDER;\r
\r
div_done_x <= '1' when ( div_counter = b"00" ) else '0';\r
\r
spi_sck_x <= '1' when ( ((div_counter = b"11") or (div_counter = b"00")) and\r
- ((tx_ena = '1') or (rx_ena = '1')) ) else '0';\r
+ ((tx_ena = '1') or (rx_ena = '1')) ) else '0';\r
\r
clk_en <= div_done;\r
\r
-----------------------------------------------------------\r
-- start signal and local register sets for CMD and ADR\r
-----------------------------------------------------------\r
-THE_START_PROC: process(clear,sysclk)\r
+THE_START_PROC: process(sysclk)\r
begin\r
- if( clear = '1' ) then\r
- start <= '0';\r
- cmd_int <= (others => '0');\r
- adh_int <= (others => '0');\r
- adm_int <= (others => '0');\r
- adl_int <= (others => '0');\r
- max_int <= (others => '0');\r
- elsif( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- start <= '0';\r
- cmd_int <= (others => '0');\r
- adh_int <= (others => '0');\r
- adm_int <= (others => '0');\r
- adl_int <= (others => '0');\r
- max_int <= (others => '0');\r
- elsif( (start_in = '1') and (busy = '0') ) then\r
- start <= '1';\r
- cmd_int <= cmd_in;\r
- adh_int <= adh_in;\r
- adm_int <= adm_in;\r
- adl_int <= adl_in;\r
- max_int <= max_in;\r
- elsif( busy = '1' ) then\r
- start <= '0';\r
- end if;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ start <= '0';\r
+ cmd_int <= (others => '0');\r
+ adh_int <= (others => '0');\r
+ adm_int <= (others => '0');\r
+ adl_int <= (others => '0');\r
+ max_int <= (others => '0');\r
+ elsif( (start_in = '1') and (busy = '0') ) then\r
+ start <= '1';\r
+ cmd_int <= cmd_in;\r
+ adh_int <= adh_in;\r
+ adm_int <= adm_in;\r
+ adl_int <= adl_in;\r
+ max_int <= max_in;\r
+ elsif( busy = '1' ) then\r
+ start <= '0';\r
+ end if;\r
+ end if;\r
end process THE_START_PROC;\r
\r
-----------------------------------------------------------\r
-- statemachine: clocked process\r
-----------------------------------------------------------\r
-THE_STATEMACHINE: process( clear, sysclk )\r
+THE_STATEMACHINE: process( sysclk )\r
begin\r
- if( clear = '1' ) then\r
- STATE <= IDLE;\r
- rx_ena <= '0';\r
- tx_ena <= '0';\r
- busy <= '0';\r
- spi_cs <= '1';\r
- tx_load <= '0';\r
- tx_sel <= "000";\r
- rx_store <= '0';\r
- rst_addr <= '0';\r
- tx_done <= '0';\r
- is_data <= '0';\r
- elsif( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- STATE <= IDLE;\r
- rx_ena <= '0';\r
- tx_ena <= '0';\r
- busy <= '0';\r
- spi_cs <= '1';\r
- tx_load <= '0';\r
- tx_sel <= "000";\r
- rx_store <= '0';\r
- rst_addr <= '0';\r
- tx_done <= '0';\r
- is_data <= '0';\r
- elsif( clk_en = '1' ) then\r
- STATE <= NEXT_STATE;\r
- rx_ena <= rx_ena_x;\r
- tx_ena <= tx_ena_x;\r
- busy <= busy_x;\r
- spi_cs <= spi_cs_x;\r
- tx_load <= tx_load_x;\r
- tx_sel <= tx_sel_x;\r
- rx_store <= rx_store_x;\r
- rst_addr <= rst_addr_x;\r
- tx_done <= tx_done_x;\r
- is_data <= is_data_x;\r
- end if;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ STATE <= IDLE;\r
+ rx_ena <= '0';\r
+ tx_ena <= '0';\r
+ busy <= '0';\r
+ spi_cs <= '1';\r
+ tx_load <= '0';\r
+ tx_sel <= "000";\r
+ rx_store <= '0';\r
+ rst_addr <= '0';\r
+ tx_done <= '0';\r
+ is_data <= '0';\r
+ elsif( clk_en = '1' ) then\r
+ STATE <= NEXT_STATE;\r
+ rx_ena <= rx_ena_x;\r
+ tx_ena <= tx_ena_x;\r
+ busy <= busy_x;\r
+ spi_cs <= spi_cs_x;\r
+ tx_load <= tx_load_x;\r
+ tx_sel <= tx_sel_x;\r
+ rx_store <= rx_store_x;\r
+ rst_addr <= rst_addr_x;\r
+ tx_done <= tx_done_x;\r
+ is_data <= is_data_x;\r
+ end if;\r
+ end if;\r
end process THE_STATEMACHINE;\r
\r
-----------------------------------------------------------\r
-----------------------------------------------------------\r
THE_STATE_TRANSITIONS: process( STATE, cmd_int, start, tx_bit_cnt, rx_bit_cnt, data_done(2) )\r
begin\r
- rx_ena_x <= '0';\r
- tx_ena_x <= '0';\r
- busy_x <= '1';\r
- spi_cs_x <= '1';\r
- tx_load_x <= '0';\r
- tx_sel_x <= "000";\r
- rx_store_x <= '0';\r
- rst_addr_x <= '0';\r
- tx_done_x <= '0';\r
- is_data_x <= '0';\r
- case STATE is\r
- when IDLE =>\r
- if( start = '1' ) then\r
- NEXT_STATE <= CSL;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "000";\r
- rst_addr_x <= '1'; \r
- else\r
- NEXT_STATE <= IDLE;\r
- busy_x <= '0';\r
- end if;\r
-\r
- when CSL =>\r
- NEXT_STATE <= TXCMD;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXCMD =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXCMD;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when WREN | WRDI | ERASE | DPD | RDPD \r
- => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR \r
- => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "001"; -- ADH\r
- when WRSR => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- is_data_x <= '1';\r
- when RDSR | RDID\r
- => NEXT_STATE <= WAIT1;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "110"; -- "00"\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
-\r
- when WAIT1 =>\r
- case cmd_int is\r
- when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR \r
- => NEXT_STATE <= TXADD_H;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when RDSR | RDID\r
- => NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when WRSR => NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- is_data_x <= '1';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when TXADD_H =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_H;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= WAIT2;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "010"; -- ADM\r
- end if;\r
-\r
- when WAIT2 => \r
- NEXT_STATE <= TXADD_M;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXADD_M =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_M;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= WAIT3;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "011"; -- ADL\r
- end if;\r
-\r
- when WAIT3 => \r
- NEXT_STATE <= TXADD_L;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
-\r
- when TXADD_L =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXADD_L;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when PP => NEXT_STATE <= WAIT6;\r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- spi_cs_x <= '0';\r
- when SE64 | SE32 | SE4 | SECP | SECU \r
- => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- when RDCMD | RDSPR\r
- => NEXT_STATE <= WAIT4;\r
- spi_cs_x <= '0';\r
- tx_load_x <= '1';\r
- tx_sel_x <= "110"; -- "00"\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
-\r
- when WAIT4 =>\r
- case cmd_int is\r
- when RDCMD | RDSPR\r
- => NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when RXDATA =>\r
- if( rx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when RDCMD | RDSR | RDID | RDSPR\r
- => NEXT_STATE <= WAIT7;\r
- spi_cs_x <= '0';\r
- rx_store_x <= '1';\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- rx_store_x <= '1';\r
- end case;\r
- end if;\r
-\r
- when WAIT6 =>\r
- case cmd_int is\r
- when PP => if( data_done(2) = '1' ) then\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- is_data_x <= '1';\r
- end if;\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when TXDATA =>\r
- if( tx_bit_cnt < x"7" ) then\r
- NEXT_STATE <= TXDATA;\r
- tx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- else\r
- case cmd_int is\r
- when PP => NEXT_STATE <= WAIT6;\r
- spi_cs_x <= '0';\r
- tx_done_x <= '1'; \r
- tx_load_x <= '1';\r
- tx_sel_x <= "100"; -- TXDATA\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
- end if;\r
- is_data_x <= '1';\r
-\r
- when WAIT7 => \r
- NEXT_STATE <= WAIT8;\r
- spi_cs_x <= '0';\r
-\r
- when WAIT8 =>\r
- case cmd_int is\r
- when RDCMD | RDID | RDSR | RDSPR\r
- => if( data_done(2) = '1' ) then\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- else\r
- NEXT_STATE <= RXDATA;\r
- rx_ena_x <= '1';\r
- spi_cs_x <= '0';\r
- end if;\r
- when others => NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
- end case;\r
-\r
- when WAIT5 =>\r
- NEXT_STATE <= CSH;\r
- spi_cs_x <= '0';\r
-\r
- when CSH =>\r
- NEXT_STATE <= IDLE;\r
- busy_x <= '0';\r
-\r
- end case;\r
+ rx_ena_x <= '0';\r
+ tx_ena_x <= '0';\r
+ busy_x <= '1';\r
+ spi_cs_x <= '1';\r
+ tx_load_x <= '0';\r
+ tx_sel_x <= "000";\r
+ rx_store_x <= '0';\r
+ rst_addr_x <= '0';\r
+ tx_done_x <= '0';\r
+ is_data_x <= '0';\r
+ case STATE is\r
+ when IDLE =>\r
+ if( start = '1' ) then\r
+ NEXT_STATE <= CSL;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "000";\r
+ rst_addr_x <= '1';\r
+ else\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+ end if;\r
+\r
+ when CSL =>\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXCMD =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXCMD;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when WREN | WRDI | ERASE | DPD | RDPD\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
+ => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "001"; -- ADH\r
+ when WRSR => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ is_data_x <= '1';\r
+ when RDSR | RDID\r
+ => NEXT_STATE <= WAIT1;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "110"; -- "00"\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
+\r
+ when WAIT1 =>\r
+ case cmd_int is\r
+ when SE64 | SE32 | SE4 | PP | RDCMD | SECP | SECU | RDSPR\r
+ => NEXT_STATE <= TXADD_H;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when RDSR | RDID\r
+ => NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when WRSR => NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ is_data_x <= '1';\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when TXADD_H =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_H;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= WAIT2;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "010"; -- ADM\r
+ end if;\r
+\r
+ when WAIT2 =>\r
+ NEXT_STATE <= TXADD_M;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXADD_M =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_M;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= WAIT3;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "011"; -- ADL\r
+ end if;\r
+\r
+ when WAIT3 =>\r
+ NEXT_STATE <= TXADD_L;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+\r
+ when TXADD_L =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXADD_L;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when PP => NEXT_STATE <= WAIT6;\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ spi_cs_x <= '0';\r
+ when SE64 | SE32 | SE4 | SECP | SECU\r
+ => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ when RDCMD | RDSPR\r
+ => NEXT_STATE <= WAIT4;\r
+ spi_cs_x <= '0';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "110"; -- "00"\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
+\r
+ when WAIT4 =>\r
+ case cmd_int is\r
+ when RDCMD | RDSPR\r
+ => NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when RXDATA =>\r
+ if( rx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when RDCMD | RDSR | RDID | RDSPR\r
+ => NEXT_STATE <= WAIT7;\r
+ spi_cs_x <= '0';\r
+ rx_store_x <= '1';\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ rx_store_x <= '1';\r
+ end case;\r
+ end if;\r
+\r
+ when WAIT6 =>\r
+ case cmd_int is\r
+ when PP => if( data_done(2) = '1' ) then\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ is_data_x <= '1';\r
+ end if;\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when TXDATA =>\r
+ if( tx_bit_cnt < x"7" ) then\r
+ NEXT_STATE <= TXDATA;\r
+ tx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ else\r
+ case cmd_int is\r
+ when PP => NEXT_STATE <= WAIT6;\r
+ spi_cs_x <= '0';\r
+ tx_done_x <= '1';\r
+ tx_load_x <= '1';\r
+ tx_sel_x <= "100"; -- TXDATA\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+ end if;\r
+ is_data_x <= '1';\r
+\r
+ when WAIT7 =>\r
+ NEXT_STATE <= WAIT8;\r
+ spi_cs_x <= '0';\r
+\r
+ when WAIT8 =>\r
+ case cmd_int is\r
+ when RDCMD | RDID | RDSR | RDSPR\r
+ => if( data_done(2) = '1' ) then\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ else\r
+ NEXT_STATE <= RXDATA;\r
+ rx_ena_x <= '1';\r
+ spi_cs_x <= '0';\r
+ end if;\r
+ when others => NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+ end case;\r
+\r
+ when WAIT5 =>\r
+ NEXT_STATE <= CSH;\r
+ spi_cs_x <= '0';\r
+\r
+ when CSH =>\r
+ NEXT_STATE <= IDLE;\r
+ busy_x <= '0';\r
+\r
+ end case;\r
end process THE_STATE_TRANSITIONS;\r
\r
-- state machine output table\r
THE_STATEMACHINE_OUT: process( STATE )\r
begin\r
- -- default values\r
- rx_bit_cnt_clr <= '1';\r
-\r
- case STATE is\r
- when IDLE => bsm_x <= x"00";\r
- when CSL => bsm_x <= x"09";\r
- when TXCMD => bsm_x <= x"01";\r
- when TXDATA => bsm_x <= x"02";\r
- when TXADD_H => bsm_x <= x"03";\r
- when TXADD_M => bsm_x <= x"04";\r
- when TXADD_L => bsm_x <= x"05";\r
- when RXDATA => bsm_x <= x"07";\r
- when WAIT1 => bsm_x <= x"10";\r
- when WAIT2 => bsm_x <= x"11";\r
- when WAIT3 => bsm_x <= x"12";\r
- when WAIT4 => bsm_x <= x"13";\r
- when WAIT8 => bsm_x <= x"17";\r
- when WAIT6 => bsm_x <= x"15";\r
- when WAIT5 => bsm_x <= x"14";\r
- when WAIT7 => bsm_x <= x"16";\r
- when CSH => bsm_x <= x"08";\r
- when others => bsm_x <= x"ff";\r
- end case;\r
+ -- default values\r
+ rx_bit_cnt_clr <= '1';\r
+\r
+ case STATE is\r
+ when IDLE => bsm_x <= x"00";\r
+ when CSL => bsm_x <= x"09";\r
+ when TXCMD => bsm_x <= x"01";\r
+ when TXDATA => bsm_x <= x"02";\r
+ when TXADD_H => bsm_x <= x"03";\r
+ when TXADD_M => bsm_x <= x"04";\r
+ when TXADD_L => bsm_x <= x"05";\r
+ when RXDATA => bsm_x <= x"07";\r
+ when WAIT1 => bsm_x <= x"10";\r
+ when WAIT2 => bsm_x <= x"11";\r
+ when WAIT3 => bsm_x <= x"12";\r
+ when WAIT4 => bsm_x <= x"13";\r
+ when WAIT8 => bsm_x <= x"17";\r
+ when WAIT6 => bsm_x <= x"15";\r
+ when WAIT5 => bsm_x <= x"14";\r
+ when WAIT7 => bsm_x <= x"16";\r
+ when CSH => bsm_x <= x"08";\r
+ when others => bsm_x <= x"ff";\r
+ end case;\r
end process THE_STATEMACHINE_OUT;\r
\r
-- TX data register multiplexer\r
THE_TXREG_MUX: process( tx_sel, cmd_int, adh_int, adm_int, adl_int, txdata_in )\r
begin\r
- case tx_sel is\r
- when "000" => tx_reg_comb <= cmd_int;\r
- when "001" => tx_reg_comb <= adh_int;\r
- when "010" => tx_reg_comb <= adm_int;\r
- when "011" => tx_reg_comb <= adl_int;\r
- when "100" => tx_reg_comb <= txdata_in;\r
- when "101" => tx_reg_comb <= x"ee"; -- unused\r
- when "110" => tx_reg_comb <= x"00"; -- fixed value\r
- when "111" => tx_reg_comb <= x"ff"; -- fixed value\r
- when others => tx_reg_comb <= x"00";\r
- end case;\r
+ case tx_sel is\r
+ when "000" => tx_reg_comb <= cmd_int;\r
+ when "001" => tx_reg_comb <= adh_int;\r
+ when "010" => tx_reg_comb <= adm_int;\r
+ when "011" => tx_reg_comb <= adl_int;\r
+ when "100" => tx_reg_comb <= txdata_in;\r
+ when "101" => tx_reg_comb <= x"ee"; -- unused\r
+ when "110" => tx_reg_comb <= x"00"; -- fixed value\r
+ when "111" => tx_reg_comb <= x"ff"; -- fixed value\r
+ when others => tx_reg_comb <= x"00";\r
+ end case;\r
end process THE_TXREG_MUX;\r
\r
-- TXData shift register and bit counter\r
-THE_TX_SHIFT_AND_BITCOUNT: process( clear, sysclk )\r
+THE_TX_SHIFT_AND_BITCOUNT: process( sysclk )\r
begin\r
- if( clear = '1' ) then\r
- tx_sreg <= (others => '0');\r
- tx_bit_cnt <= (others => '0');\r
- last_tx_bit <= '0';\r
- elsif( rising_edge(sysclk) ) then\r
- if ( (clk_en = '1' ) and (tx_load = '1') ) then\r
- tx_bit_cnt <= (others => '0');\r
- tx_sreg <= tx_reg_comb;\r
- elsif( (clk_en = '1') and (tx_ena = '1') ) then\r
- tx_bit_cnt <= tx_bit_cnt + 1;\r
- tx_sreg <= tx_sreg (6 downto 0) & '0';\r
- end if;\r
- last_tx_bit <= last_tx_bit_x;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if( reset = '1' ) then\r
+ tx_sreg <= (others => '0');\r
+ tx_bit_cnt <= (others => '0');\r
+ last_tx_bit <= '0';\r
+ elsif ( (clk_en = '1' ) and (tx_load = '1') ) then\r
+ tx_bit_cnt <= (others => '0');\r
+ tx_sreg <= tx_reg_comb;\r
+ elsif( (clk_en = '1') and (tx_ena = '1') ) then\r
+ tx_bit_cnt <= tx_bit_cnt + 1;\r
+ tx_sreg <= tx_sreg (6 downto 0) & '0';\r
+ end if;\r
+ last_tx_bit <= last_tx_bit_x;\r
+ end if;\r
end process THE_TX_SHIFT_AND_BITCOUNT;\r
\r
last_tx_bit_x <= '1' when ( tx_bit_cnt = x"7" ) else '0';\r
\r
-- receiver shift register and bit counter\r
-THE_RX_SHIFT_AND_BITCOUNT: process( clear, sysclk )\r
+THE_RX_SHIFT_AND_BITCOUNT: process( sysclk )\r
begin\r
- if( clear = '1' ) then\r
- rx_bit_cnt <= (others => '0');\r
- rx_sreg <= (others => '0');\r
- elsif( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- rx_bit_cnt <= (others => '0');\r
- rx_sreg <= (others => '0');\r
- elsif( (clk_en = '1') and (rx_ena = '1') ) then\r
- rx_sreg <= rx_sreg (6 downto 0) & spi_sdi_in;\r
- case rx_bit_cnt is\r
- when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>\r
- rx_bit_cnt <= rx_bit_cnt + 1;\r
- when x"7" =>\r
- rx_bit_cnt <= (others => '0');\r
- when others =>\r
- null;\r
- end case;\r
- end if;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ rx_bit_cnt <= (others => '0');\r
+ rx_sreg <= (others => '0');\r
+ elsif( (clk_en = '1') and (rx_ena = '1') ) then\r
+ rx_sreg <= rx_sreg (6 downto 0) & spi_sdi_in;\r
+ case rx_bit_cnt is\r
+ when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>\r
+ rx_bit_cnt <= rx_bit_cnt + 1;\r
+ when x"7" =>\r
+ rx_bit_cnt <= (others => '0');\r
+ when others =>\r
+ null;\r
+ end case;\r
+ end if;\r
+ end if;\r
end process THE_RX_SHIFT_AND_BITCOUNT;\r
\r
-- the rx_data register\r
-THE_RXDATA_REG: process( clear, sysclk )\r
+THE_RXDATA_REG: process( sysclk )\r
begin\r
- if( clear = '1' ) then\r
- rx_data <= (others => '0');\r
- rx_complete <= '0';\r
- elsif( rising_edge(sysclk) ) then\r
- if ( reset = '1' ) then\r
- rx_data <= (others => '0');\r
- rx_complete <= '0';\r
- elsif( (clk_en = '1') and (rx_store = '1') ) then\r
- rx_data <= rx_sreg;\r
- rx_complete <= '1';\r
- else\r
- rx_complete <= '0';\r
- end if;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( reset = '1' ) then\r
+ rx_data <= (others => '0');\r
+ rx_complete <= '0';\r
+ elsif( (clk_en = '1') and (rx_store = '1') ) then\r
+ rx_data <= rx_sreg;\r
+ rx_complete <= '1';\r
+ else\r
+ rx_complete <= '0';\r
+ end if;\r
+ end if;\r
end process;\r
\r
-- address generator for external BRAM\r
-THE_ADDR_COUNTER: process( clear, sysclk )\r
+THE_ADDR_COUNTER: process( sysclk )\r
begin\r
- if( clear = '1' ) then\r
- addr_ctr <= (others => '0');\r
- data_done <= (others => '0');\r
- inc_addr_rx <= '0';\r
- inc_addr_tx <= '0';\r
- ce_addr <= '0';\r
- elsif( rising_edge(sysclk) ) then\r
- if ( (reset = '1') or (rst_addr = '1') ) then\r
- addr_ctr <= (others => '0');\r
- data_done <= (others => '0');\r
- inc_addr_rx <= '0';\r
- inc_addr_tx <= '0';\r
- ce_addr <= '0';\r
- elsif( ce_addr = '1' ) then\r
- addr_ctr <= addr_ctr + 1;\r
- end if;\r
- data_done(2 downto 1) <= data_done(1 downto 0);\r
- data_done(0) <= data_done_x;\r
- inc_addr_rx <= inc_addr_rx_x;\r
- inc_addr_tx <= inc_addr_tx_x;\r
- ce_addr <= ce_addr_x;\r
- end if;\r
+ if( rising_edge(sysclk) ) then\r
+ if ( (reset = '1') or (rst_addr = '1') ) then\r
+ addr_ctr <= (others => '0');\r
+ data_done <= (others => '0');\r
+ inc_addr_rx <= '0';\r
+ inc_addr_tx <= '0';\r
+ ce_addr <= '0';\r
+ elsif( ce_addr = '1' ) then\r
+ addr_ctr <= addr_ctr + 1;\r
+ end if;\r
+ data_done(2 downto 1) <= data_done(1 downto 0);\r
+ data_done(0) <= data_done_x;\r
+ inc_addr_rx <= inc_addr_rx_x;\r
+ inc_addr_tx <= inc_addr_tx_x;\r
+ ce_addr <= ce_addr_x;\r
+ end if;\r
end process THE_ADDR_COUNTER;\r
\r
inc_addr_rx_x <= '1' when ( rx_complete = '1' ) else '0';\r
+ component spi_databus_memory is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- Slave bus
+ BUS_ADDR_IN : in std_logic_vector(5 downto 0);
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+ BUS_ACK_OUT : out std_logic;
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- state machine connections
+ BRAM_ADDR_IN : in std_logic_vector(7 downto 0);
+ BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);
+ BRAM_RD_D_IN : in std_logic_vector(7 downto 0);
+ BRAM_WE_IN : in std_logic;
+ -- Status lines
+ STAT : out std_logic_vector(63 downto 0) -- DEBUG
+ );
+ end component;
+
+
+ component spi_dpram_32_to_8 is
+ port (
+ DataInA: in std_logic_vector(31 downto 0);
+ DataInB: in std_logic_vector(7 downto 0);
+ AddressA: in std_logic_vector(5 downto 0);
+ AddressB: in std_logic_vector(7 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(31 downto 0);
+ QB: out std_logic_vector(7 downto 0));
+ end component;
+
+ component spi_slim is
+ port(
+ SYSCLK : in std_logic; -- 100MHz sysclock
+ RESET : in std_logic; -- synchronous reset
+ -- Command interface
+ START_IN : in std_logic; -- one start pulse
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing
+ CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte
+ ADL_IN : in std_logic_vector(7 downto 0); -- low address byte
+ ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte
+ ADH_IN : in std_logic_vector(7 downto 0); -- high address byte
+ MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)
+ TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next
+ TX_RD_OUT : out std_logic;
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte
+ RX_WR_OUT : out std_logic;
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD
+ -- SPI interface
+ SPI_SCK_OUT : out std_logic;
+ SPI_CS_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic;
+ SPI_SDO_OUT : out std_logic;
+ -- DEBUG
+ CLK_EN_OUT : out std_logic;
+ BSM_OUT : out std_logic_vector(7 downto 0);
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+
+
+
+ component spi_master is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ -- Slave bus
+ BUS_READ_IN : in std_logic;
+ BUS_WRITE_IN : in std_logic;
+ BUS_BUSY_OUT : out std_logic;
+ BUS_ACK_OUT : out std_logic;
+ BUS_ADDR_IN : in std_logic_vector(0 downto 0);
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);
+ -- SPI connections
+ SPI_CS_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic;
+ SPI_SDO_OUT : out std_logic;
+ SPI_SCK_OUT : out std_logic;
+ -- BRAM for read/write data
+ BRAM_A_OUT : out std_logic_vector(7 downto 0);
+ BRAM_WR_D_IN : in std_logic_vector(7 downto 0);
+ BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);
+ BRAM_WE_OUT : out std_logic;
+ -- Status lines
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG
+ );
+ end component;
jspc29 / trbnet.git / commitdiff