Changing the PLL to 325MHz to cope with 65MS (hopefully)

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 54d52e60e7b86a3c02fd60bbe2f4c9034089d4e2..d569288eaf68e778eea6e88a83817bf51e0cbe98 100644 (file)
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -35,8 +35,8 @@ architecture adc_ad9219_arch of  adc_ad9219 is
 type q_t is array(0 to NUM_DEVICES-1) of std_logic_vector(19 downto 0);
 signal q,qq,qqq,q_q : q_t;
 
-signal clk_adcfast_i : std_logic; --200MHz
-signal clk_data      : std_logic; --100MHz
+signal clk_adcfast_i : std_logic; --200MHz/325MHz
+signal clk_data      : std_logic; --100MHz/162.5MHz
 signal clk_data_half : std_logic;
 signal restart_i     : std_logic;
 
@@ -70,7 +70,13 @@ gen_40MHz : if ADC_SAMPLING_RATE = 40 generate
       CLK   => CLK_ADCRAW,
       CLKOP => ADCCLK_OUT,
       LOCK  => lock(0)
-      );
+    );
+  THE_ADC_PLL_0 : entity work.pll_adc10bit
+    port map(
+      CLK   => CLK_ADCRAW,
+      CLKOP => clk_adcfast_i,
+      LOCK  => lock(1)
+    );
 end generate;
 
 gen_65MHz : if ADC_SAMPLING_RATE = 65 generate
@@ -79,17 +85,14 @@ gen_65MHz : if ADC_SAMPLING_RATE = 65 generate
       CLK   => CLK_ADCRAW,
       CLKOP => ADCCLK_OUT,
       LOCK  => lock(0)
-      );
-end generate;
-
-
-  THE_ADC_PLL_0 : entity work.pll_adc10bit
+    );
+  THE_ADC_PLL_0 : entity work.pll_adc10bit_65
     port map(
       CLK   => CLK_ADCRAW,
       CLKOP => clk_adcfast_i,
       LOCK  => lock(1)
-      );
-
+    );
+end generate;
  
   restart_i <= RESTART_IN when rising_edge(clk_data);
 

diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj
index 62fcb0119e19f757f91ad76d753c4dfb139ae6ee..cf186b5334210276cdbac3ba47e597daeb96ad56 100644 (file)
--- a/ADC/trb3_periph_adc.prj
+++ b/ADC/trb3_periph_adc.prj
@@ -144,6 +144,7 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_in200_out65.vhd"
 add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_65.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
 add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"

diff --git a/base/cores/pll_adc10bit_65.ipx b/base/cores/pll_adc10bit_65.ipx
new file mode 100644 (file)
index 0000000..a895feb
--- /dev/null
+++ b/base/cores/pll_adc10bit_65.ipx
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc10bit_65" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 10 14:29:41.127" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="pll_adc10bit_65.lpc" type="lpc" modified="2015 02 10 14:29:38.000"/>
+               <File name="pll_adc10bit_65.vhd" type="top_level_vhdl" modified="2015 02 10 14:29:38.000"/>
+               <File name="pll_adc10bit_65_tmpl.vhd" type="template_vhdl" modified="2015 02 10 14:29:38.000"/>
+  </Package>
+</DiamondModule>

diff --git a/base/cores/pll_adc10bit_65.lpc b/base/cores/pll_adc10bit_65.lpc
new file mode 100644 (file)
index 0000000..db62bad
--- /dev/null
+++ b/base/cores/pll_adc10bit_65.lpc
@@ -0,0 +1,66 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_adc10bit_65
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/10/2015
+Time=14:29:38
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=8
+ClkOPBp=0
+Post=2
+U_OFrq=325
+OP_Tol=0.0
+OFrq=325.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=13
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.348655
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0

diff --git a/base/cores/pll_adc10bit_65.vhd b/base/cores/pll_adc10bit_65.vhd
new file mode 100644 (file)
index 0000000..3d2b2ca
--- /dev/null
+++ b/base/cores/pll_adc10bit_65.vhd
@@ -0,0 +1,100 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 5.3
+--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit_65 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 325 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e 
+
+-- Tue Feb 10 14:29:38 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc10bit_65 is
+    port (
+        CLK: in std_logic; 
+        CLKOP: out std_logic; 
+        LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc10bit_65 : entity is true;
+end pll_adc10bit_65;
+
+architecture Structure of pll_adc10bit_65 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component EHXPLLF
+        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
+                DELAY_PWD : in String; DELAY_VAL : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
+                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
+                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
+                PHASEADJ : in String; CLKOK_DIV : in Integer; 
+                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
+                CLKI_DIV : in Integer; FIN : in String);
+        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
+            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
+            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
+            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
+            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
+            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
+            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
+            LOCK: out std_logic; CLKINTFB: out std_logic);
+    end component;
+    component VLO
+        port (Z: out std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "325.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute syn_keep : boolean;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLF
+        generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", 
+        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
+        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
+        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
+        CLKOK_DIV=>  2, CLKOP_DIV=>  2, CLKFB_DIV=>  13, CLKI_DIV=>  8, 
+        FIN=> "200.000000")
+        port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, 
+            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
+            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
+            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
+            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
+            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
+            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
+            CLKINTFB=>CLKFB_t);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc10bit_65 is
+    for Structure
+        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on