---------------------------------------------------------------------------
THE_MEDIA_INTERFACE : entity med_ecp3_sfp_sync_all_RS
generic map(
- IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE)
+ IS_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_SLAVE)
)
port map(
-- Clocks and reset
- CLK_REF_FULL => link_clock,
- SYSCLK => clk_sys,
- CLEAR => init_quad,
- RESET => reset_i,
+ CLK_REF_FULL => link_clock,
+ SYSCLK => clk_sys,
+ CLEAR => init_quad,
+ RESET => reset_i,
-- Media Interface TX/RX
- MEDIA_MED2INT(0) => open,
- MEDIA_MED2INT(1) => open,
- MEDIA_MED2INT(2) => open,
- MEDIA_MED2INT(3) => med2int(0),
- MEDIA_INT2MED(0) => open,
- MEDIA_INT2MED(1) => open,
- MEDIA_INT2MED(2) => open,
- MEDIA_INT2MED(3) => int2med(0),
+ MEDIA_MED2INT(0 to 2) => open,
+ MEDIA_MED2INT(3) => med2int(0),
+ MEDIA_INT2MED(0 to 2) => open,
+ MEDIA_INT2MED(3) => int2med(0),
-- Sync operation
- RX_DLM_OUT(0) => open,
- RX_DLM_OUT(1) => open,
- RX_DLM_OUT(2) => open,
- RX_DLM_OUT(3) => rx_dlm_i,
+ RX_DLM_OUT(2 downto 2) => open,
+ RX_DLM_OUT(3) => rx_dlm_i,
RX_DLM_WORD_OUT(23 downto 0) => open,
RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i,
- TX_DLM_IN => rx_dlm_i,
- TX_DLM_WORD_IN => send_dlm_word_i,
- RX_RST_OUT => send_rst_i,
- RX_RST_WORD_OUT => send_rst_word_i,
- TX_RST_IN => '0',
- TX_RST_WORD_IN => x"00",
+ TX_DLM_IN => rx_dlm_i,
+ TX_DLM_WORD_IN => send_dlm_word_i,
+ RX_RST_OUT => send_rst_i,
+ RX_RST_WORD_OUT => send_rst_word_i,
+ TX_RST_IN => send_rst_i, --'0',
+ TX_RST_WORD_IN => send_rst_word_i, --x"00",
-- sync operation
- WORD_SYNC_IN => word_sync_i,
- WORD_SYNC_OUT => word_sync_i,
- MASTER_CLK_IN => master_clk_i,
- MASTER_CLK_OUT => master_clk_i,
- LINK_TX_NULL_IN => global_reset_i,
- LINK_RX_NULL_OUT => global_reset_i,
- TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
- TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- TX_PCS_RST_IN => tx_pcs_rst_i,
- SYNC_TX_PLL_IN => sync_tx_quad_i,
- LINK_TX_READY_IN => link_tx_ready_i,
- DESTROY_LINK_IN => (others => '0'),
- WAP_REQUESTED_IN => x"0",
+ WORD_SYNC_IN => word_sync_i,
+ WORD_SYNC_OUT => word_sync_i,
+ MASTER_CLK_IN => master_clk_i,
+ MASTER_CLK_OUT => master_clk_i,
+ LINK_TX_NULL_IN => global_reset_i,
+ LINK_RX_NULL_OUT => global_reset_i,
+ TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i,
+ TX_CLK_AVAIL_OUT => tx_clk_avail_i,
+ TX_PCS_RST_IN => tx_pcs_rst_i,
+ SYNC_TX_PLL_IN => sync_tx_quad_i,
+ LINK_TX_READY_IN => link_tx_ready_i,
+ DESTROY_LINK_IN => (others => '0'),
+ WAP_REQUESTED_IN => x"0",
--SFP Connection
- SD_PRSNT_N_IN(0) => '1',
- SD_LOS_IN(0) => '1',
- SD_TXDIS_OUT(0) => open,
- SD_PRSNT_N_IN(1) => '1',
- SD_LOS_IN(1) => '1',
- SD_TXDIS_OUT(1) => open,
- SD_PRSNT_N_IN(2) => '1',
- SD_LOS_IN(2) => '1',
- SD_TXDIS_OUT(2) => open,
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN(2 downto 0) => (others => '1'),
+ SD_LOS_IN(2 downto 0) => (others => '1'),
+ SD_TXDIS_OUT(2 downto 0) => open,
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
--Control Interface
- BUS_RX => bussci_rx,
- BUS_TX => bussci_tx,
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
-- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open,
- DEBUG_OUT => debug_i
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open,
+ DEBUG_OUT => debug_i
);
THE_MAIN_TX_RST: main_tx_reset_RS
LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX
-
--- THE_TOGGLE_PROC: process( clk_sys )
--- begin
--- if( rising_edge(clk_sys) ) then
--- toggler <= not toggler;
--- end if;
--- end process THE_TOGGLE_PROC;
---------------------------------------------------------------------------
-- Test Circuits
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
--- THE_TDC : TDC_record
--- generic map (
--- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
--- STATUS_REG_NR => 21, -- Number of status regs
--- DEBUG => c_YES,
--- SIMULATION => c_NO)
--- port map (
--- RESET => reset_i,
--- CLK_TDC => clk_full_osc,
--- CLK_READOUT => clk_sys, -- Clock for the readout
--- REFERENCE_TIME => TRIG_LEFT, -- Reference time input
--- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
--- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
--- -- Trigger signals from handler
--- BUSRDO_RX => readout_rx,
--- BUSRDO_TX => readout_tx(0),
--- -- Slow control bus
--- BUS_RX => bustdc_rx,
--- BUS_TX => bustdc_tx,
--- -- Dubug signals
--- INFO_IN => timer,
--- LOGIC_ANALYSER_OUT => logic_analyser_i
--- );
+ THE_TDC : TDC_record
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => clk_full_osc,
+ CLK_READOUT => clk_sys, -- Clock for the readout
+ REFERENCE_TIME => TRIG_LEFT, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+ -- Trigger signals from handler
+ BUSRDO_RX => readout_rx,
+ BUSRDO_TX => readout_tx(0),
+ -- Slow control bus
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx,
+ -- Dubug signals
+ INFO_IN => timer,
+ LOGIC_ANALYSER_OUT => logic_analyser_i
+ );
gen_normal_pins : if PINOUT = 1 or PINOUT = 2 or PINOUT = 3 generate
end generate Gen_Hit_In_Signals;
end generate;
-
gen_montrg_inputs_normal : if TRIG_GEN_FAST_CHANNELS = c_NO generate
monitor_inputs_i <= trig_gen_out_i & inputs(MONITOR_INPUT_NUM-TRIG_GEN_OUTPUT_NUM -1 downto 0);
trigger_inputs_i <= inputs(TRIG_GEN_INPUT_NUM-1 downto 0);
jspc29 / trb3sc.git / commitdiff