static int hexMode = HEXMODE;
-static const char trbcmd_version[] = "$Revision: 2.35 $";
+static const char trbcmd_version[] = "$Revision: 2.36 $";
/* ---- User Buffer Size ----------------------------------------------- */
uint8_t type;
uint8_t random = 0;
- uint8_t info = 0;
+ uint32_t info = 0;
uint16_t number = 0;
if (cmdLen != 5) {
"Command: SEND_TRIGGER: "
"type: 0x%01x, "
"random: 0x%02x, "
- "info: 0x%02x, "
+ "info: 0x%06x, "
"number: 0x%04x\n",
type, random, info, number);
}
uint8_t input = 0;
uint8_t type = 0;
uint8_t random = 0;
- uint8_t info = 0;
+ uint32_t info = 0;
uint16_t number = 0;
if (cmdLen != 6) {
"input: 0x%01x, "
"type: 0x%01x, "
"random: 0x%02x, "
- "info: 0x%02x, "
+ "info: 0x%06x, "
"number: 0x%04x\n",
input, type, random, info, number);
}
-const char trbnet_version[] = "$Revision: 2.46 $";
+const char trbnet_version[] = "$Revision: 2.47 $";
#include <stdio.h>
#include <stdlib.h>
#define CHANNEL_0_SENDER_ERROR 0x0112
#define CHANNEL_0_SENDER_DATA 0x0113
#define CHANNEL_0_SENDER_FIFO_STATUS 0x0114
+#define CHANNEL_0_SENDER_TRIGGER_INFO 0x0115
#define CHANNEL_0_SENDER_STATUS 0x011f
#define CHANNEL_0_RECEIVER_DATA 0x0213
#define CHANNEL_0_RECEIVER_FIFO_STATUS 0x0214
int trb_send_trigger(uint8_t type,
- uint8_t trg_info,
+ uint32_t trg_info,
uint8_t trg_random,
uint16_t trg_number)
{
}
/* Prepare trigger channel */
- write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) |
+ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) |
((uint32_t)trg_random << 16) |
((uint32_t)trg_number)
));
+
+ write32_to_FPGA(CHANNEL_0_SENDER_TRIGGER_INFO, (trg_info >> 8) & 0xffff);
+
+
/* Send trigger */
write32_to_FPGA(CHANNEL_0_SENDER_CONTROL,
int trb_send_trigger_rich(uint8_t trg_input,
uint8_t type,
- uint8_t trg_info,
+ uint32_t trg_info,
uint8_t trg_random,
uint16_t trg_number)
{
}
/* Prepare trigger channel */
- write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((uint32_t)trg_info << 24) |
+ write32_to_FPGA(CHANNEL_0_SENDER_ERROR, (((trg_info & 0xff) << 24) |
((uint32_t)trg_random << 16) |
((uint32_t)trg_number)
));
-
+
+ write32_to_FPGA(CHANNEL_0_SENDER_TRIGGER_INFO, (trg_info >> 8) & 0xffff);
+
/* Prepare slowcontrol channel */
write32_to_FPGA(CHANNEL_3_TARGET_ADDRESS, 0x0000fffb); /* RICH Subnet only */
write32_to_FPGA(CHANNEL_3_SENDER_ERROR, 0x00000000);
unsigned int dsize);
int trb_send_trigger(uint8_t type,
- uint8_t info,
+ uint32_t info,
uint8_t random,
uint16_t number);
int trb_send_trigger_rich(uint8_t input,
uint8_t type,
- uint8_t info,
+ uint32_t info,
uint8_t random,
uint16_t number);
/************************************************************************/
/* int trb_send_trigger(uint8_t type,
- uint8_t info,
+ uint32_t info,
uint8_t random,
uint16_t number);
*/