\r
library work;\r
use work.trb_net_std.all;\r
---use work.trb_net_components.all;\r
+use work.trb_net_components.all;\r
\r
entity trb_net16_rx_comma_handler is\r
port(\r
signal buf_disperr : std_logic_vector(1 downto 0);\r
\r
signal data_valid_x : std_logic;\r
+signal data_valid : std_logic;\r
signal comma_valid_x : std_logic;\r
\r
signal c_idle_x : std_logic;\r
signal c_error : std_logic; -- 0xF7\r
signal c_stx_x : std_logic;\r
signal c_stx : std_logic; -- 0xFB\r
+signal c_crc_x : std_logic;\r
+signal c_crc : std_logic; -- 0xFD\r
+signal c_invalid_k_x : std_logic;\r
\r
signal comma_idle : std_logic; -- correct IDLE comma (/I1/ or /I2/) received\r
signal comma_idle_x : std_logic;\r
signal comma_stx_x : std_logic;\r
signal comma_error : std_logic; -- correct ErrorDetected comma received\r
signal comma_error_x : std_logic;\r
+signal comma_crc : std_logic; -- correct CRC comma received\r
+signal comma_crc_x : std_logic;\r
+signal comma_crc_q : std_logic;\r
+signal comma_crc_qq : std_logic;\r
+\r
\r
signal comma_toggle : std_logic;\r
signal rst_toggle : std_logic;\r
\r
signal fifo_wr_x : std_logic;\r
signal fifo_wr : std_logic;\r
+signal buf_fifo_wr : std_logic;\r
\r
signal ld_rx_position : std_logic;\r
signal rx_position : std_logic_vector(7 downto 0);\r
signal make_trbnet_reset : std_logic;\r
signal reset_word_cnt : unsigned(4 downto 0);\r
\r
+signal crc_enable : std_logic;\r
+signal crc_active : std_logic;\r
+signal crc_match : std_logic;\r
+signal crc_reset : std_logic;\r
+\r
begin\r
\r
----------------------------------------------------------------------\r
c_reset <= c_reset_x;\r
c_error <= c_error_x;\r
c_stx <= c_stx_x;\r
+ c_crc <= c_crc_x;\r
comma_idle <= comma_idle_x;\r
comma_stx <= comma_stx_x;\r
comma_error <= comma_error_x;\r
comma_locked <= comma_locked_x;\r
+ comma_crc <= comma_crc_x;\r
+ comma_crc_q <= comma_crc;\r
+ data_valid <= data_valid_x;\r
fifo_wr <= fifo_wr_x;\r
+ buf_fifo_wr <= fifo_wr;\r
ld_rx_position <= comma_stx;\r
ld_start_position <= comma_error;\r
if( comma_toggle = '1' ) then\r
if( comma_error = '1' ) then\r
start_position <= buf_data(7 downto 0);\r
end if;\r
+\r
+ if RESET_IN = '1' then\r
+ crc_active <= '0';\r
+ elsif( comma_crc = '1') then\r
+ crc_active <= '1';\r
+ end if;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
c_reset_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fe") ) else '0';\r
c_error_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"f7") ) else '0';\r
c_stx_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fb") ) else '0';\r
+c_crc_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fd") ) else '0';\r
+\r
+c_invalid_k_x <= '1' when buf_rx_k = '1' and\r
+ (c_idle_x = '0' and c_reset_x = '0' and c_error_x = '0' and c_stx_x = '0' and c_crc_x = '0') else '0';\r
\r
-- Comma recognition part II: data part of comma\r
--- IDLE is allows any time\r
+-- IDLE is allowed any time\r
comma_idle_x <= '1' when ( (c_idle = '1') and (buf_rx_k = '0') and ((buf_rx_data = x"50") or (buf_rx_data = x"c5")) )\r
else '0';\r
\r
-- ErrorDetected is only accepted in LOCKED state\r
comma_error_x <= '1' when ( (c_error = '1') and (buf_rx_k = '0') and (comma_locked_x = '1') ) else '0';\r
\r
+-- CRC found is only accepted in LOCKED state\r
+comma_crc_x <= '1' when ( (c_crc = '1') and (buf_rx_k = '0') and (comma_locked_x = '1') ) else '0';\r
+\r
+\r
-- reset toggle bit in case of mismatch during locking phase\r
rst_toggle <= '1' when ( ((comma_idle = '1') and (comma_toggle = '0') and (comma_locked_x = '0')) or\r
((comma_idle = '0') and (comma_toggle = '1') and (comma_locked_x = '0')) or\r
-- check for correct data / comma values\r
----------------------------------------------------------------------\r
\r
-comma_valid_x <= comma_locked and (comma_idle or comma_error or comma_stx)\r
+comma_valid_x <= comma_locked and (comma_idle or comma_error or comma_stx or comma_crc)\r
and not buf_cv(1) and not buf_cv(0) ; --and not buf_disperr(0) and not buf_disperr(1);\r
\r
data_valid_x <= comma_locked and not buf_k(1) and not buf_k(0)\r
\r
THE_FIFO_INHIBIT_PROC: process( CLK_IN )\r
begin\r
- if( rising_edge(CLK_IN) ) then\r
+ if( rising_edge(CLK_IN) ) then\r
if ( (RESET_IN = '1') or (comma_stx = '1') or ENABLE_CORRECTION_IN = '0') then\r
fifo_inhibit <= '0';\r
- elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' ) then\r
+ elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') and c_reset_x = '0' )\r
+ or (crc_match = '0' and comma_crc_x = '1' and crc_active = '1')\r
+ or c_invalid_k_x = '1' then\r
fifo_inhibit <= '1';\r
end if;\r
end if;\r
end process THE_FIFO_INHIBIT_PROC;\r
\r
+----------------------------------------------------------------------\r
+-- CRC\r
+----------------------------------------------------------------------\r
+THE_CRC : trb_net_CRC8\r
+ port map(\r
+ CLK => CLK_IN,\r
+ RESET => crc_reset,\r
+ CLK_EN => crc_enable,\r
+ DATA_IN => buf_rx_data,\r
+ CRC_OUT => open,\r
+ CRC_match => crc_match\r
+ );\r
+\r
+ crc_reset <= RESET_IN or (fifo_inhibit and not comma_stx) or (not crc_active and not comma_crc);\r
+ crc_enable <= (not buf_rx_k and not (comma_idle_x or comma_error_x or comma_stx_x or comma_crc_x)) or comma_crc_x;\r
+\r
+\r
----------------------------------------------------------------------\r
-- Debug signals\r
----------------------------------------------------------------------\r
STAT_REG_OUT(4 downto 0) <= std_logic_vector(reset_word_cnt);\r
STAT_REG_OUT(5) <= fifo_inhibit;\r
STAT_REG_OUT(6) <= comma_locked;\r
-STAT_REG_OUT(7) <= '0';\r
+STAT_REG_OUT(7) <= comma_crc;\r
STAT_REG_OUT(15 downto 8)<= (others => '0');\r
\r
----------------------------------------------------------------------\r
-- Output signals\r
----------------------------------------------------------------------\r
FIFO_DATA_OUT <= buf2_data;\r
-FIFO_WR_OUT <= fifo_wr;\r
+FIFO_WR_OUT <= buf_fifo_wr;\r
FIFO_INHIBIT_OUT <= fifo_inhibit;\r
\r
LD_START_POSITION_OUT <= ld_start_position;\r
RdEn => ct_fifo_read,
Reset => ct_fifo_reset,
RPReset => ct_fifo_reset,
- Q(15 downto 0) => tx_data_25_i,
- Q(16) => load_sop,
- Q(17) => load_eop,
+ Q(17 downto 0) => tx_data_25_i,
Empty => ct_fifo_empty,
Full => ct_fifo_full,
AlmostFull => ct_fifo_afull
ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
-- gk 05.10.10
-save_sop <= '1' when (TX_PACKET_NUMBER_IN = b"100") else '0';
-save_eop <= '1' when (TX_PACKET_NUMBER_IN = b"011") else '0';
+save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
+save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
----------------------------------------------------------------------
-- RAM
when SEND_DATA_L =>
TX_DATA_OUT <= ram_dout(7 downto 0);
+ load_sop <= ram_dout(16);
+ load_eop <= ram_dout(17);
TX_K_OUT <= '0';
current_state <= SEND_DATA_H;
when SEND_CHKSUM_L =>
TX_DATA_OUT <= x"FD";
TX_K_OUT <= '1';
+ load_sop <= '0';
+ load_eop <= '0';
current_state <= SEND_CHKSUM_H;
-- gk 05.10.10
when SEND_CHKSUM_H =>
TX_DATA_OUT <= crc_q;
- TX_K_OUT <= '1';
- current_state <= SEND_IDLE_L;
+ TX_K_OUT <= '0';
+-- current_state <= SEND_IDLE_L;
when SEND_IDLE_L =>
TX_DATA_OUT <= x"BC";
current_state = SEND_IDLE_H or
current_state = SEND_DATA_H or
current_state = SEND_REQUEST_H or
+ current_state = SEND_CHKSUM_H or
current_state = SLEEP then
if tx_allow_qtx = '0' then
current_state <= SEND_IDLE_L;
load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';
-- gk 05.10.10
- crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_IDLE_L)) else '0';
+ crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';
crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';
- crc_data <= ram_dout(15 downto 8) when (current_state = SEND_IDLE_H) else ram_dout(7 downto 0);
+ crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0);
-- gk 05.10.10
CRC_CALC : trb_net_CRC8