-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2015-05-12
+-- Last update: 2024-06-19
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
entity Readout is
generic (
CHANNEL_NUMBER : integer range 2 to 65;
- STATUS_REG_NR : integer range 0 to 31);
+ STATUS_REG_NR : integer range 0 to 31);
port (
RESET_100 : in std_logic;
RESET_200 : in std_logic;
-- miscellaneous
LIGHT_MODE_IN : in std_logic;
DEBUG_MODE_EN_IN : in std_logic;
- STATISTICS_OUT : out std_logic_vector_array_24(0 to 15);
+ --STATISTICS_OUT : out std_logic_vector_array_24(0 to 8);
READOUT_DEBUG : out std_logic_vector(31 downto 0)
);
end entity Readout;
signal wr_info : std_logic;
signal wr_time : std_logic;
signal wr_epoch : std_logic;
- signal stop_status : std_logic;
+ --signal stop_status : std_logic;
-- to endpoint
signal data_out_r : std_logic_vector(31 downto 0);
signal data_wr_r : std_logic;
signal wr_fsm_debug_r : std_logic_vector(3 downto 0);
signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0');
signal any_hit : std_logic := '0';
-
+
begin -- behavioral
trg_win_pre <= unsigned(TRG_WIN_PRE_IN);
READ_EN_OUT <= rd_en;
RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, TRG_DATA_VALID_IN,
- INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status,
+ INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, SPURIOUS_TRG_IN, --stop_status,
DEBUG_MODE_EN_IN, fifo_nr_rd, TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN,
buffer_transfer_done_2r, MISSING_REF_TIME_IN, wrong_readout, isNoHit_r)
begin
case (RD_CURRENT) is
when IDLE =>
if VALID_TIMING_TRG_IN = '1' then -- physical trigger
- RD_NEXT <= WAIT_FOR_TRG_WIND_END;
+ RD_NEXT <= WAIT_FOR_TRG_WIND_END;
--if isLastTriggerNoTiming = '1' then
-- wrong_readout_fsm <= '1';
--end if;
readout_fsm <= '1';
elsif VALID_NOTIMING_TRG_IN = '1' then
- if TRG_TYPE_IN = x"E" then -- status trigger
- wr_header_fsm <= '1';
- RD_NEXT <= SEND_STATUS;
- elsif TRG_TYPE_IN = x"D" then -- tdc calibration trigger
- RD_NEXT <= WAIT_FOR_TRG_WIND_END;
+ -- if TRG_TYPE_IN = x"E" then -- status trigger
+ -- wr_header_fsm <= '1';
+ -- RD_NEXT <= SEND_STATUS;
+ --elsif TRG_TYPE_IN = x"D" then -- tdc calibration trigger
+ if TRG_TYPE_IN = x"D" then -- tdc calibration trigger
+ RD_NEXT <= WAIT_FOR_TRG_WIND_END;
--wr_header_fsm <= '1';
- readout_fsm <= '1';
+ readout_fsm <= '1';
else -- the other triggers
RD_NEXT <= SEND_TRG_RELEASE_A;
data_finished_fsm <= '1';
end if;
idle_fsm <= '1';
rd_fsm_debug_fsm <= x"1";
-
+
when WAIT_FOR_TRG_WIND_END =>
if TRG_WIN_END_RDO_IN = '1' then
RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER;
if MISSING_REF_TIME_IN = '1' or isNoHit_r = '0' then
- wr_header_fsm <= '1';
+ wr_header_fsm <= '1';
if MISSING_REF_TIME_IN = '1' then
missing_ref_time_fsm <= '1';
end if;
fifo_nr_rd_fsm <= fifo_nr_rd;
elsif fifo_nr_rd = CHANNEL_NUMBER-1 then -- the last channel
rd_en_fsm(fifo_nr_rd) <= '0';
- if DEBUG_MODE_EN_IN = '1' then -- send status after channel data
- RD_NEXT <= SEND_STATUS;
- else
- RD_NEXT <= WAIT_FOR_LVL1_TRG_A;
- end if;
+ -- if DEBUG_MODE_EN_IN = '1' then -- send status after channel data
+ -- RD_NEXT <= SEND_STATUS;
+ -- else
+ RD_NEXT <= WAIT_FOR_LVL1_TRG_A;
+ --end if;
else -- go to the next channel
fifo_nr_rd_fsm <= fifo_nr_rd + 1 after 10 ps;
end if;
wait_fsm <= '1';
rd_fsm_debug_fsm <= x"8";
- when SEND_STATUS =>
- if stop_status = '1' then
- if DEBUG_MODE_EN_IN = '1' then
- RD_NEXT <= WAIT_FOR_LVL1_TRG_A;
- else
- RD_NEXT <= SEND_TRG_RELEASE_A;
- data_finished_fsm <= '1';
- end if;
- else
- wr_status_fsm <= '1';
- end if;
- readout_fsm <= '1';
- rd_fsm_debug_fsm <= x"9";
+ -- when SEND_STATUS =>
+ -- if stop_status = '1' then
+ -- if DEBUG_MODE_EN_IN = '1' then
+ -- RD_NEXT <= WAIT_FOR_LVL1_TRG_A;
+ -- else
+ -- RD_NEXT <= SEND_TRG_RELEASE_A;
+ -- data_finished_fsm <= '1';
+ -- end if;
+ -- else
+ -- wr_status_fsm <= '1';
+ -- end if;
+ -- readout_fsm <= '1';
+ -- rd_fsm_debug_fsm <= x"9";
when SEND_TRG_RELEASE_A =>
RD_NEXT <= SEND_TRG_RELEASE_B;
-------------------------------------------------------------------------------
-- Data out mux
-------------------------------------------------------------------------------
- isCalibrationTrigger: process (CLK_100) is
+ isCalibrationTrigger : process (CLK_100) is
begin
- if rising_edge(CLK_100) then -- rising clock edge
+ if rising_edge(CLK_100) then -- rising clock edge
if trg_release = '1' then
isCalTrig <= '0';
elsif VALID_NOTIMING_TRG_IN = '1' and TRG_TYPE_IN = x"D" then
end if;
end if;
end process isCalibrationTrigger;
-
+
-- Trigger window selection
TriggerWindowElimination : process (CLK_100)
begin
if rising_edge(CLK_100) then
if ch_data_3r(fifo_nr_wr_r)(35 downto 32) = x"1" and ch_data_3r(fifo_nr_wr_r)(31) = '1' then --DATA word
- if TRG_WIN_EN_IN = '1' and isCalTrig = '0' then -- trigger window enabled
+ if TRG_WIN_EN_IN = '1' and isCalTrig = '0' then -- trigger window enabled
--elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow
-- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then
-- ch_data_4r <= ch_data_3r(fifo_nr);
begin
if rising_edge(CLK_100) then
if wr_header = '1' then
- data_out_r <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits;
- stop_status <= '0';
+ data_out_r <= "001" & "0" & TRG_TYPE_IN & TRG_CODE_IN & header_error_bits;
+ --stop_status <= '0';
elsif wr_ch_data_r = '1' then
- data_out_r <= ch_data_4r;
- stop_status <= '0';
- elsif wr_status = '1' then
- case i is
- when 0 => data_out_r <= "010" & "00000" & std_logic_vector(trg_number);
- when 1 => data_out_r <= "010" & "00001" & std_logic_vector(release_number);
- when 2 => data_out_r <= "010" & "00010" & std_logic_vector(valid_tmg_trg_number);
- when 3 => data_out_r <= "010" & "00011" & std_logic_vector(valid_NOtmg_trg_number);
- when 4 => data_out_r <= "010" & "00100" & std_logic_vector(invalid_trg_number);
- when 5 => data_out_r <= "010" & "00101" & std_logic_vector(multi_tmg_trg_number);
- when 6 => data_out_r <= "010" & "00110" & std_logic_vector(spurious_trg_number);
- when 7 => data_out_r <= "010" & "00111" & std_logic_vector(wrong_readout_number);
- when 8 => data_out_r <= "010" & "01000" & std_logic_vector(spike_number);
- when 9 => data_out_r <= "010" & "01001" & std_logic_vector(idle_time);
- when 10 => data_out_r <= "010" & "01010" & std_logic_vector(wait_time);
- when 11 => data_out_r <= "010" & "01011" & std_logic_vector(total_empty_channel);
- when 12 => data_out_r <= "010" & "01100" & std_logic_vector(readout_time);
- stop_status <= '1';
- when 13 => data_out_r <= "010" & "01101" & std_logic_vector(timeout_number);
- i := -1;
- when others => null;
- end case;
- i := i+1;
- --elsif wr_trailer = '1' then
- -- data_out_r <= "011" & "0000000000000" & trailer_error_bits;
- -- data_wr_r <= '1';
- -- stop_status<= '0';
+ data_out_r <= ch_data_4r;
+ --stop_status <= '0';
+ -- elsif wr_status = '1' then
+ -- case i is
+ -- when 0 => data_out_r <= "010" & "00000" & std_logic_vector(trg_number);
+ -- when 1 => data_out_r <= "010" & "00001" & std_logic_vector(release_number);
+ -- when 2 => data_out_r <= "010" & "00010" & std_logic_vector(valid_tmg_trg_number);
+ -- when 3 => data_out_r <= "010" & "00011" & std_logic_vector(valid_NOtmg_trg_number);
+ -- --when 4 => data_out_r <= "010" & "00100" & std_logic_vector(invalid_trg_number);
+ -- --when 5 => data_out_r <= "010" & "00101" & std_logic_vector(multi_tmg_trg_number);
+ -- --when 6 => data_out_r <= "010" & "00110" & std_logic_vector(spurious_trg_number);
+ -- --when 7 => data_out_r <= "010" & "00111" & std_logic_vector(wrong_readout_number);
+ -- --when 8 => data_out_r <= "010" & "01000" & std_logic_vector(spike_number);
+ -- when 4 => data_out_r <= "010" & "01001" & std_logic_vector(idle_time);
+ -- when 5 => data_out_r <= "010" & "01010" & std_logic_vector(wait_time);
+ -- when 6 => data_out_r <= "010" & "01011" & std_logic_vector(total_empty_channel);
+ -- stop_status <= '1';
+ -- when 7 => data_out_r <= "010" & "01100" & std_logic_vector(readout_time);
+ -- i := -1;
+ -- --when 13 => data_out_r <= "010" & "01101" & std_logic_vector(timeout_number);
+ -- --i := -1;
+ -- when others => null;
+ -- end case;
+ -- i := i+1;
+ -- --elsif wr_trailer = '1' then
+ -- -- data_out_r <= "011" & "0000000000000" & trailer_error_bits;
+ -- -- data_wr_r <= '1';
+ -- -- stop_status<= '0';
else
- data_out_r <= (others => '1');
- stop_status <= '0';
+ data_out_r <= (others => '1');
+ --stop_status <= '0';
end if;
end if;
end process Data_Out_MUX;
- wr_info <= wr_header or wr_status when rising_edge(CLK_100);
+ --wr_info <= wr_header or wr_status when rising_edge(CLK_100);
+ wr_info <= wr_header when rising_edge(CLK_100);
wr_time <= wr_ch_data_r and ch_data_4r(31) when rising_edge(CLK_100);
wr_epoch <= wr_ch_data_r and not data_out_r(31) and data_out_r(30) and data_out_r(29) and ch_data_4r(31);
READOUT_DEBUG(31 downto 17) <= (others => '0');
-- Error, warning bits set in the header
-
+
header_error_bits(0) <= or_all(CH_ALMOST_FULL_IN);
header_error_bits(1) <= missing_ref_time;
header_error_bits(15 downto 2) <= (others => '0');
CheckHitStatus : process (CLK_100) is
begin
- if rising_edge(CLK_100) then -- rising clock edge
+ if rising_edge(CLK_100) then -- rising clock edge
if LIGHT_MODE_IN = '0' or TRG_WIN_EN_IN = '1' then
isNoHit <= '0';
isNoHit_r <= '0';
-- Debug and statistics words
-------------------------------------------------------------------------------
- edge_to_pulse_1 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => VALID_TIMING_TRG_IN,
- pulse => valid_timing_trg_p);
-
- edge_to_pulse_2 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => VALID_NOTIMING_TRG_IN,
- pulse => valid_notiming_trg_p);
-
- edge_to_pulse_3 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => INVALID_TRG_IN,
- pulse => invalid_trg_p);
-
- edge_to_pulse_4 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => MULTI_TMG_TRG_IN,
- pulse => multi_tmg_trg_p);
-
- edge_to_pulse_5 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => SPURIOUS_TRG_IN,
- pulse => spurious_trg_p);
-
- edge_to_pulse_6 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => SPIKE_DETECTED_IN,
- pulse => spike_detected_p);
-
- edge_to_pulse_7 : edge_to_pulse
- port map (
- clock => CLK_100,
- en_clk => '1',
- signal_in => TMGTRG_TIMEOUT_IN,
- pulse => timeout_detected_p);
-
--- Internal trigger number counter (only valid triggers)
- Statistics_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- trg_number <= (others => '0');
- elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then
- trg_number <= trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Trigger_Number;
-
--- Internal release number counter
- Statistics_Release_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- release_number <= (others => '0');
- elsif trg_release = '1' then
- release_number <= release_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Release_Number;
-
--- Internal valid timing trigger number counter
- Statistics_Valid_Timing_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- valid_tmg_trg_number <= (others => '0');
- elsif valid_timing_trg_p = '1' then
- valid_tmg_trg_number <= valid_tmg_trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Valid_Timing_Trigger_Number;
-
--- Internal valid NOtiming trigger number counter
- Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- valid_NOtmg_trg_number <= (others => '0');
- elsif valid_notiming_trg_p = '1' then
- valid_NOtmg_trg_number <= valid_NOtmg_trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Valid_NoTiming_Trigger_Number;
-
--- Internal invalid trigger number counter
- Statistics_Invalid_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- invalid_trg_number <= (others => '0');
- elsif invalid_trg_p = '1' then
- invalid_trg_number <= invalid_trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Invalid_Trigger_Number;
-
--- Internal multi timing trigger number counter
- Statistics_Multi_Timing_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- multi_tmg_trg_number <= (others => '0');
- elsif multi_tmg_trg_p = '1' then
- multi_tmg_trg_number <= multi_tmg_trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Multi_Timing_Trigger_Number;
-
--- Internal spurious trigger number counter
- Statistics_Spurious_Trigger_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- spurious_trg_number <= (others => '0');
- elsif spurious_trg_p = '1' then
- spurious_trg_number <= spurious_trg_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Spurious_Trigger_Number;
-
- wrongReadoutUp : entity work.risingEdgeDetect
- port map (
- CLK => CLK_100,
- SIGNAL_IN => wrong_readout,
- PULSE_OUT => wrong_readout_up);
--- Number of wrong readout becasue of spurious trigger
- Statistics_Wrong_Readout_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- wrong_readout_number <= (others => '0');
- elsif wrong_readout_up = '1' then
- wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Wrong_Readout_Number;
-
--- Internal spike number counter
- Statistics_Spike_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- spike_number <= (others => '0');
- elsif spike_detected_p = '1' then
- spike_number <= spike_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Spike_Number;
-
--- Internal timeout number counter
- Statistics_Timeout_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- timeout_number <= (others => '0');
- elsif timeout_detected_p = '1' then
- timeout_number <= timeout_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Timeout_Number;
-
--- IDLE time of the TDC readout
- Statistics_Idle_Time : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- idle_time <= (others => '0');
- elsif idle_time_up = '1' then
- idle_time <= idle_time + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Idle_Time;
-
--- Readout and Wait time of the TDC readout
- Statistics_Readout_Wait_Time : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- readout_time <= (others => '0');
- wait_time <= (others => '0');
- elsif readout_time_up = '1' then
- readout_time <= readout_time + to_unsigned(1, 1);
- elsif wait_time_up = '1' then
- wait_time <= wait_time + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Readout_Wait_Time;
-
- -- Number of sent data finished
- Statistics_Finished_Number : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if RESET_COUNTERS = '1' then
- finished_number <= (others => '0');
- elsif data_finished = '1' then --finished = '1' then
- finished_number <= finished_number + to_unsigned(1, 1);
- end if;
- end if;
- end process Statistics_Finished_Number;
-
- HistoryReadDebug : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if rd_fsm_debug_r /= rd_fsm_debug then
- history_rd_fsm <= history_rd_fsm(27 downto 0) & rd_fsm_debug;
- end if;
- rd_fsm_debug_r <= rd_fsm_debug;
- end if;
- end process HistoryReadDebug;
-
- HistoryWriteDebug : process (CLK_100)
- begin
- if rising_edge(CLK_100) then
- if wr_fsm_debug_r /= wr_fsm_debug then
- history_wr_fsm <= history_wr_fsm(27 downto 0) & wr_fsm_debug;
- end if;
- wr_fsm_debug_r <= wr_fsm_debug;
- end if;
- end process HistoryWriteDebug;
+-- edge_to_pulse_1 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => VALID_TIMING_TRG_IN,
+-- pulse => valid_timing_trg_p);
+
+-- edge_to_pulse_2 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => VALID_NOTIMING_TRG_IN,
+-- pulse => valid_notiming_trg_p);
+
+-- edge_to_pulse_3 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => INVALID_TRG_IN,
+-- pulse => invalid_trg_p);
+
+-- edge_to_pulse_4 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => MULTI_TMG_TRG_IN,
+-- pulse => multi_tmg_trg_p);
+
+-- edge_to_pulse_5 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => SPURIOUS_TRG_IN,
+-- pulse => spurious_trg_p);
+
+-- edge_to_pulse_6 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => SPIKE_DETECTED_IN,
+-- pulse => spike_detected_p);
+
+-- edge_to_pulse_7 : edge_to_pulse
+-- port map (
+-- clock => CLK_100,
+-- en_clk => '1',
+-- signal_in => TMGTRG_TIMEOUT_IN,
+-- pulse => timeout_detected_p);
+
+-- -- Internal trigger number counter (only valid triggers)
+-- Statistics_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- trg_number <= (others => '0');
+-- elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then
+-- trg_number <= trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Trigger_Number;
+
+-- -- Internal release number counter
+-- Statistics_Release_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- release_number <= (others => '0');
+-- elsif trg_release = '1' then
+-- release_number <= release_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Release_Number;
+
+-- -- Internal valid timing trigger number counter
+-- Statistics_Valid_Timing_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- valid_tmg_trg_number <= (others => '0');
+-- elsif valid_timing_trg_p = '1' then
+-- valid_tmg_trg_number <= valid_tmg_trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Valid_Timing_Trigger_Number;
+
+-- -- Internal valid NOtiming trigger number counter
+-- Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- valid_NOtmg_trg_number <= (others => '0');
+-- elsif valid_notiming_trg_p = '1' then
+-- valid_NOtmg_trg_number <= valid_NOtmg_trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Valid_NoTiming_Trigger_Number;
+
+-- -- Internal invalid trigger number counter
+-- Statistics_Invalid_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- invalid_trg_number <= (others => '0');
+-- elsif invalid_trg_p = '1' then
+-- invalid_trg_number <= invalid_trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Invalid_Trigger_Number;
+
+-- -- Internal multi timing trigger number counter
+-- Statistics_Multi_Timing_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- multi_tmg_trg_number <= (others => '0');
+-- elsif multi_tmg_trg_p = '1' then
+-- multi_tmg_trg_number <= multi_tmg_trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Multi_Timing_Trigger_Number;
+
+-- -- Internal spurious trigger number counter
+-- Statistics_Spurious_Trigger_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- spurious_trg_number <= (others => '0');
+-- elsif spurious_trg_p = '1' then
+-- spurious_trg_number <= spurious_trg_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Spurious_Trigger_Number;
+
+-- wrongReadoutUp : entity work.risingEdgeDetect
+-- port map (
+-- CLK => CLK_100,
+-- SIGNAL_IN => wrong_readout,
+-- PULSE_OUT => wrong_readout_up);
+-- -- Number of wrong readout becasue of spurious trigger
+-- Statistics_Wrong_Readout_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- wrong_readout_number <= (others => '0');
+-- elsif wrong_readout_up = '1' then
+-- wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Wrong_Readout_Number;
+
+-- -- Internal spike number counter
+-- Statistics_Spike_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- spike_number <= (others => '0');
+-- elsif spike_detected_p = '1' then
+-- spike_number <= spike_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Spike_Number;
+
+-- -- Internal timeout number counter
+-- Statistics_Timeout_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- timeout_number <= (others => '0');
+-- elsif timeout_detected_p = '1' then
+-- timeout_number <= timeout_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Timeout_Number;
+
+-- -- IDLE time of the TDC readout
+-- Statistics_Idle_Time : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- idle_time <= (others => '0');
+-- elsif idle_time_up = '1' then
+-- idle_time <= idle_time + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Idle_Time;
+
+-- -- Readout and Wait time of the TDC readout
+-- Statistics_Readout_Wait_Time : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- readout_time <= (others => '0');
+-- wait_time <= (others => '0');
+-- elsif readout_time_up = '1' then
+-- readout_time <= readout_time + to_unsigned(1, 1);
+-- elsif wait_time_up = '1' then
+-- wait_time <= wait_time + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Readout_Wait_Time;
+
+-- -- Number of sent data finished
+-- Statistics_Finished_Number : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if RESET_COUNTERS = '1' then
+-- finished_number <= (others => '0');
+-- elsif data_finished = '1' then --finished = '1' then
+-- finished_number <= finished_number + to_unsigned(1, 1);
+-- end if;
+-- end if;
+-- end process Statistics_Finished_Number;
+
+-- HistoryReadDebug : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if rd_fsm_debug_r /= rd_fsm_debug then
+-- history_rd_fsm <= history_rd_fsm(27 downto 0) & rd_fsm_debug;
+-- end if;
+-- rd_fsm_debug_r <= rd_fsm_debug;
+-- end if;
+-- end process HistoryReadDebug;
+
+-- HistoryWriteDebug : process (CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if wr_fsm_debug_r /= wr_fsm_debug then
+-- history_wr_fsm <= history_wr_fsm(27 downto 0) & wr_fsm_debug;
+-- end if;
+-- wr_fsm_debug_r <= wr_fsm_debug;
+-- end if;
+-- end process HistoryWriteDebug;
-------------------------------------------------------------------------------
-- STATUS REGISTERS BUS
-------------------------------------------------------------------------------
-- statistics
- STATISTICS_OUT(0) <= std_logic_vector(trg_number);
- STATISTICS_OUT(1) <= std_logic_vector(valid_tmg_trg_number);
- STATISTICS_OUT(2) <= std_logic_vector(valid_NOtmg_trg_number);
- STATISTICS_OUT(3) <= std_logic_vector(invalid_trg_number);
- STATISTICS_OUT(4) <= std_logic_vector(multi_tmg_trg_number);
- STATISTICS_OUT(5) <= std_logic_vector(spurious_trg_number);
- STATISTICS_OUT(6) <= std_logic_vector(wrong_readout_number);
- STATISTICS_OUT(7) <= std_logic_vector(spike_number);
- STATISTICS_OUT(8) <= std_logic_vector(idle_time);
- STATISTICS_OUT(9) <= std_logic_vector(wait_time);
- STATISTICS_OUT(10) <= std_logic_vector(total_empty_channel);
- STATISTICS_OUT(11) <= std_logic_vector(release_number);
- STATISTICS_OUT(12) <= std_logic_vector(readout_time);
- STATISTICS_OUT(13) <= std_logic_vector(timeout_number);
- STATISTICS_OUT(14) <= std_logic_vector(finished_number);
- STATISTICS_OUT(15) <= (others => '0');
-
+ -- STATISTICS_OUT(0) <= std_logic_vector(trg_number);
+ -- STATISTICS_OUT(1) <= std_logic_vector(valid_tmg_trg_number);
+ -- STATISTICS_OUT(2) <= std_logic_vector(valid_NOtmg_trg_number);
+
+ -- STATISTICS_OUT(3) <= std_logic_vector(invalid_trg_number);
+ -- STATISTICS_OUT(4) <= std_logic_vector(multi_tmg_trg_number);
+ -- STATISTICS_OUT(5) <= std_logic_vector(spurious_trg_number);
+ -- STATISTICS_OUT(6) <= std_logic_vector(wrong_readout_number);
+ -- STATISTICS_OUT(7) <= std_logic_vector(spike_number);
+ -- STATISTICS_OUT(3) <= std_logic_vector(idle_time);
+ -- STATISTICS_OUT(4) <= std_logic_vector(wait_time);
+ -- STATISTICS_OUT(5) <= std_logic_vector(total_empty_channel);
+ -- STATISTICS_OUT(6) <= std_logic_vector(release_number);
+ -- STATISTICS_OUT(7) <= std_logic_vector(readout_time);
+ -- -- STATISTICS_OUT(13) <= std_logic_vector(timeout_number);
+ -- STATISTICS_OUT(8) <= std_logic_vector(finished_number);
+ -- STATISTICS_OUT(9) <= (others => '0');
+
-- readout debug history
--STATUS_REGISTERS_BUS_OUT(19) <= history_rd_fsm;
--STATUS_REGISTERS_BUS_OUT(20) <= history_wr_fsm;
jspc29 / tdc.git / commitdiff