Finish backport of ADC AddOn from TRB3sc to TRB3, fix bug in "samples after trigger...

diff --git a/ADC/compile_periph_frankfurt.pl b/ADC/compile_periph_frankfurt.pl
index 37970429e4ca77450c1c9a38c463daab4af27ac6..caf8a39875539ec094f7fcfb31a3f17523288c87 100755 (executable)
--- a/ADC/compile_periph_frankfurt.pl
+++ b/ADC/compile_periph_frankfurt.pl
@@ -11,7 +11,7 @@ use FileHandle;
 my $TOPNAME                      = "trb3_periph_adc";  #Name of top-level entity
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.1_x64';
 my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_synplify = "27020\@jspc29";
 my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
 ###################################################################################
 
@@ -55,7 +55,7 @@ system("rm $TOPNAME.ncd");
 
 #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|;
 #  $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 4 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
+$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 7 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|;
 execute($c);
 
 $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
@@ -113,4 +113,4 @@ sub checksrr {
       exit 129;
       }
     }
-  }
\ No newline at end of file
+  }

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 9835c0ab3060e9cf6bacd2aa6290134e336aa1c1..29b86370740286df2cffb4dcae55a750210f96ef 100644 (file)
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -9,7 +9,8 @@ use work.adc_package.all;
 
 entity adc_ad9219 is
   generic(
-    NUM_DEVICES    : integer := 5
+    NUM_DEVICES    : integer := 5;
+    IS_TRB3        : integer := 0
     );
   port(
     CLK        : in std_logic;
@@ -70,13 +71,18 @@ begin
 --       LOCK  => lock(0)
 --       );
 
+gen_240_to_200 : if IS_TRB3 = 0 generate
   THE_ADC_PLL_0 : entity work.pll_adc10bit
     port map(
       CLK   => CLK_ADCRAW,
       CLKOP => clk_adcfast_i,
       LOCK  => lock(1)
       );
+end generate;
 
+gen_no_pll : if IS_TRB3 = 1 generate
+  clk_adcfast_i <= CLK_ADCRAW;
+end generate;
  
   restart_i <= RESTART_IN when rising_edge(clk_data);
 

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index 2016c073b9b42ea7c2b3463a6048c1c9cbc275ae..6f64585a305f5aa5655af270d67c0b05c098c0b8 100644 (file)
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -8,6 +8,9 @@ use work.trb3_components.all;
 use work.adc_package.all;
 
 entity adc_handler is
+  generic(
+    IS_TRB3 : integer := 0
+    );
   port(
     CLK        : in std_logic;
     CLK_ADCRAW : in std_logic;
@@ -112,7 +115,8 @@ begin
 
 THE_ADC_LEFT : entity work.adc_ad9219
   generic map(
-    NUM_DEVICES        => DEVICES_1
+    NUM_DEVICES        => DEVICES_1,
+    IS_TRB3            => IS_TRB3
     )
   port map(
     CLK         => CLK,
@@ -151,7 +155,8 @@ THE_ADC_LEFT : entity work.adc_ad9219
 
 THE_ADC_RIGHT : entity work.adc_ad9219
   generic map(
-    NUM_DEVICES        => DEVICES_2
+    NUM_DEVICES        => DEVICES_2,
+    IS_TRB3            => IS_TRB3
     )
   port map(
     CLK         => CLK,

diff --git a/ADC/source/adc_processor.vhd b/ADC/source/adc_processor.vhd
index 5f408e55cfaf6776a838dbf1b448894c22dde52f..1f8297e0ba588d9ffed5a03d42a7944917e4006d 100644 (file)
--- a/ADC/source/adc_processor.vhd
+++ b/ADC/source/adc_processor.vhd
@@ -278,7 +278,7 @@ proc_buffer_enable : process begin
   elsif or_all(std_logic_vector(after_trg_cnt)) = '0' then
     stop_writing_rdo <= '1';
     after_trg_cnt    <= (others => '1');
-  elsif after_trg_cnt(11) = '0' then
+  elsif after_trg_cnt(11) = '0' and ram_write = '1' then
     after_trg_cnt <= after_trg_cnt - 1;
   end if;
   

diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd
index 203a174ab468830172b88d12d17d2a1706125058..eacb02cad3dbd2714ae6626aa803278f0ddac1cf 100644 (file)
--- a/ADC/trb3_periph_adc.vhd
+++ b/ADC/trb3_periph_adc.vhd
@@ -190,7 +190,13 @@ begin
       );
 
 
-  
+
+  THE_ADC_REF : entity work.pll_in200_out40
+    port map(
+      CLK   => CLK_PCLK_RIGHT,
+      CLKOP => P_CLOCK,
+      LOCK  => open
+      );  
   
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
@@ -288,6 +294,9 @@ begin
 ---------------------------------------------------------------------------
 gen_reallogic : if USE_DUMMY_READOUT = 0 generate
   THE_ADC : entity work.adc_handler
+    generic map(
+      IS_TRB3 => 1
+      )
     port map(
       CLK        => clk_100_i,
       CLK_ADCRAW => CLK_PCLK_RIGHT,

diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf
index 3aec3b1cc2a4c809b7660516ad3d7a663160a9cd..59c1171b2fd8b58392855ea26311a82dfcb37484 100644 (file)
--- a/ADC/trb3_periph_adc_constraints.lpf
+++ b/ADC/trb3_periph_adc_constraints.lpf
@@ -77,8 +77,8 @@ INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_12;
 # Clocks
 #################################################################  
 #USE PRIMARY NET "CLK_GPLL_RIGHT_c";
-#USE PRIMARY NET "CLK_PCLK_LEFT_c";
 
+USE PRIMARY NET "CLK_PCLK_LEFT_c";
 USE PRIMARY NET "CLK_PCLK_RIGHT_c";
 
 #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0";