unknown

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 745ecad573cb89f462b9e57d1e5e1ac6a9983f19..5e9612d6e5a04860759a74684d7371ca4321b00c 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -258,6 +258,8 @@ architecture trb3sc_arch of trb3sc_cts is
   signal rx_index_i                  : std_logic_vector(3 downto 0);
   signal phaser_data                 : std_logic_vector(31 downto 0);
   signal phaser_update               : std_logic;
+  signal coarse_counter              : unsigned(15 downto 0);
+  signal coarse_delay                : std_logic_vector(15 downto 0);
   
 --  attribute syn_keep : boolean;
 --  attribute syn_preserve : boolean;  
@@ -436,10 +438,26 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       RESET         => reset_i,
       SIGNAL_A_IN   => word_sync_i,
       SIGNAL_B_IN   => rx_index_i(3),
-      LOW_CNT_OUT   => phaser_data(15 downto 0),
+      LOW_CNT_OUT   => open,
       HI_CNT_OUT    => phaser_data(31 downto 16),
       UPDATE_OUT    => phaser_update
     ); 
+    
+  THE_COARSE_COUNTER_PROC: process( clk_full_osc )
+  begin
+    if( rising_edge(clk_full_osc) ) then
+      if( tx_dlm_i = '1' ) then
+        coarse_counter <= (others => '0');
+      else
+        coarse_counter <= coarse_counter + 1;
+      end if;
+      if( rx_dlm_i = '1' ) then
+        coarse_delay <= std_logic_vector(coarse_counter);
+      end if;
+    end if;
+  end process THE_COARSE_COUNTER_PROC;
+  
+  phaser_data(15 downto 0) <= coarse_delay;
   --------------------------------------------------------------------
   --------------------------------------------------------------------