keep current working status3

diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd
index b0a92aa879b93050db0c0b59cffbd43d43cfbd56..2fd8581a9c48b9fdb0e4029c65e0415e0bd1e03b 100644 (file)
--- a/nxyter/source/nx_timestamp_fifo_read.vhd
+++ b/nxyter/source/nx_timestamp_fifo_read.vhd
@@ -96,7 +96,8 @@ architecture Behavioral of nx_timestamp_fifo_read is
   signal slv_no_more_data_o       : std_logic;\r
   signal slv_unknown_addr_o       : std_logic;\r
   signal slv_ack_o                : std_logic;\r
-  signal register_fifo_status     : std_logic_vector(31 downto 0);\r
+\r
+  signal reset_ctr                : std_logic;\r
   signal frame_clock_ctr_inc_r    : std_logic;\r
 \r
 begin\r
@@ -353,7 +354,8 @@ begin
                                  fifo_out(8),\r
                                  fifo_new_frame,\r
                                  register_fifo_data,\r
-                                 frame_sync_wait_done\r
+                                 frame_sync_wait_done,\r
+                                 reset_ctr\r
                                  )\r
 \r
     variable fifo_tag_given : std_logic_vector(3 downto 0);\r
@@ -396,7 +398,10 @@ begin
       when S_SYNC_RESYNC =>\r
         rs_sync_reset_x         <= '1';\r
         frame_clock_ctr_inc_s_x <= '1';\r
-        nx_frame_resync_ctr_x   <= nx_frame_resync_ctr + 1;\r
+        if (reset_ctr = '0') then\r
+          nx_frame_resync_ctr_x   <= nx_frame_resync_ctr + 1;          \r
+        end if;\r
+\r
         frame_sync_wait_ctr_x   <= x"14";\r
         NEXT_STATE_SYNC         <= S_SYNC_WAIT;\r
 \r
@@ -408,21 +413,17 @@ begin
         end if;\r
         \r
     end case;\r
+\r
+    if (reset_ctr = '1') then\r
+      nx_frame_resync_ctr_x   <= (others => '0');       \r
+    end if;\r
+\r
   end process PROC_SYNC_TO_NX_FRAME;\r
 \r
   -----------------------------------------------------------------------------\r
   -- TRBNet Slave Bus\r
   -----------------------------------------------------------------------------\r
 \r
-  register_fifo_status(0)            <= fifo_full;\r
-  register_fifo_status(1)            <= fifo_empty;\r
-  register_fifo_status(2)            <= fifo_data_valid;\r
-  register_fifo_status(3)            <= fifo_new_frame;\r
-  register_fifo_status(15 downto 4)  <= (others => '0');\r
-  register_fifo_status(23 downto 16) <= nx_frame_resync_ctr;\r
-  register_fifo_status(30 downto 24) <= (others => '0');\r
-  register_fifo_status(31)           <= nx_frame_synced;\r
-\r
   -- Give status info to the TRB Slow Control Channel\r
   PROC_FIFO_REGISTERS: process(CLK_IN)\r
   begin\r
@@ -433,37 +434,53 @@ begin
         slv_unknown_addr_o     <= '0';\r
         slv_no_more_data_o     <= '0';\r
         frame_clock_ctr_inc_r  <= '0';\r
+        reset_ctr              <= '0';\r
       else\r
         slv_data_out_o         <= (others => '0');\r
-        slv_ack_o              <= '1';\r
+        slv_ack_o              <= '0';\r
         slv_unknown_addr_o     <= '0';\r
         slv_no_more_data_o     <= '0';\r
         frame_clock_ctr_inc_r  <= '0';\r
+        reset_ctr              <= '0';\r
 \r
         if (SLV_READ_IN  = '1') then\r
           case SLV_ADDR_IN is\r
             when x"0000" =>\r
-              slv_data_out_o     <= register_fifo_data;\r
+              slv_data_out_o               <= register_fifo_data;\r
+              slv_ack_o                    <= '1';\r
 \r
             when x"0001" =>\r
-              slv_data_out_o     <= register_fifo_status;\r
+              slv_data_out_o(0)            <= fifo_full;\r
+              slv_data_out_o(1)            <= fifo_empty;\r
+              slv_data_out_o(3 downto 2)   <= (others => '0');\r
+              slv_data_out_o(4)            <= fifo_data_valid;\r
+              slv_data_out_o(5)            <= fifo_new_frame;\r
+              slv_data_out_o(30 downto 6)  <= (others => '0');\r
+              slv_data_out_o(31)           <= nx_frame_synced;\r
+              slv_ack_o                    <= '1'; \r
+\r
+            when x"0002" =>\r
+              slv_data_out_o(7 downto 0)   <= nx_frame_resync_ctr;\r
+              slv_data_out_o(31 downto 8)  <= (others => '0');\r
+              slv_ack_o                    <= '1'; \r
 \r
             when others  =>\r
-              slv_unknown_addr_o <= '1';\r
-              slv_ack_o          <= '0';          \r
+              slv_unknown_addr_o           <= '1';\r
           end case;\r
           \r
         elsif (SLV_WRITE_IN  = '1') then\r
           case SLV_ADDR_IN is\r
             when x"0001" =>\r
               frame_clock_ctr_inc_r <= '1';\r
+              slv_ack_o             <= '1'; \r
+\r
+            when x"0002" => \r
+              reset_ctr             <= '1';\r
+              slv_ack_o             <= '1'; \r
 \r
             when others  =>\r
               slv_unknown_addr_o    <= '1';              \r
-              slv_ack_o             <= '0';\r
           end case;                \r
-        else\r
-          slv_ack_o <= '0';\r
         end if;\r
       end if;\r
     end if;\r

diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd
index d8e69b871dde713ca4992043e3d19705cbbc87f4..3ba2ca903dbb1e88131269050d4ffbee2e87dba7 100644 (file)
--- a/nxyter/source/nx_trigger_generator.vhd
+++ b/nxyter/source/nx_trigger_generator.vhd
@@ -12,6 +12,7 @@ entity nx_trigger_generator is
 \r
     TRIGGER_OUT          : out   std_logic;\r
     TS_RESET_OUT         : out   std_logic;\r
+    TESTPULSE_OUT        : out   std_logic;\r
     \r
     -- Slave bus         \r
     SLV_READ_IN          : in    std_logic;\r
@@ -40,12 +41,13 @@ architecture Behavioral of nx_trigger_generator is
   signal trigger_o_x         : std_logic;\r
   signal ts_reset_o          : std_logic;\r
   signal ts_reset_o_x        : std_logic;\r
+  signal testpulse_o_x       : std_logic;\r
+  signal testpulse_o         : std_logic;\r
   \r
   type STATES is (S_IDLE,\r
-                  S_WAIT_TS_RESET,\r
                   S_NEXT_CYCLE,\r
-                  S_SET_TRIGGER,\r
-                  S_WAIT_TRIGGER\r
+                  S_SET_TESTPULSE,\r
+                  S_WAIT_TRIGGER_END\r
                   );\r
   signal STATE, NEXT_STATE : STATES;\r
   \r
@@ -56,7 +58,7 @@ architecture Behavioral of nx_trigger_generator is
   signal slv_ack_o               : std_logic;\r
 \r
   signal reg_trigger_period      : unsigned(15 downto 0);\r
-  signal reg_trigger_length      : unsigned(15 downto 0);\r
+  signal reg_testpulse_length    : unsigned(15 downto 0);\r
   signal reg_trigger_num_cycles  : unsigned(7 downto 0);      \r
   signal reg_reset_on            : std_logic;\r
   \r
@@ -92,12 +94,14 @@ begin
     if( rising_edge(CLK_IN) ) then\r
       if (RESET_IN = '1') then\r
         trigger_o         <= '0';\r
+        testpulse_o       <= '0';\r
         ts_reset_o        <= '0';\r
         wait_timer_init   <= (others => '0');\r
         trigger_cycle_ctr <= (others => '0');\r
         STATE             <= S_IDLE;\r
       else\r
         trigger_o         <= trigger_o_x;\r
+        testpulse_o       <= testpulse_o_x;\r
         ts_reset_o        <= ts_reset_o_x;\r
         wait_timer_init   <= wait_timer_init_x;\r
         trigger_cycle_ctr <= trigger_cycle_ctr_x;\r
@@ -109,10 +113,14 @@ begin
   PROC_TRIGGER_OUT: process(STATE,\r
                             start_cycle,\r
                             reg_trigger_num_cycles,\r
+                            reg_trigger_period,\r
+                            reg_reset_on,\r
+                            reg_testpulse_length,\r
                             wait_timer_done\r
                             )\r
   begin\r
     trigger_o_x         <= '0';\r
+    testpulse_o_x       <= '0';\r
     ts_reset_o_x        <= '0';\r
     wait_timer_init_x   <= (others => '0');\r
     trigger_cycle_ctr_x <= trigger_cycle_ctr;\r
@@ -121,10 +129,10 @@ begin
       when  S_IDLE =>\r
         if (start_cycle = '1') then\r
           trigger_cycle_ctr_x   <= reg_trigger_num_cycles;\r
-          if reg_reset_on = '1' then\r
+          if (reg_reset_on = '1') then\r
             ts_reset_o_x        <= '1';\r
             wait_timer_init_x   <= reg_trigger_period;\r
-            NEXT_STATE          <= S_WAIT_TS_RESET;\r
+            NEXT_STATE          <= S_WAIT_TRIGGER_END;\r
           else\r
             NEXT_STATE          <= S_NEXT_CYCLE;\r
           end if;\r
@@ -132,34 +140,33 @@ begin
           NEXT_STATE            <= S_IDLE;\r
         end if;\r
 \r
-      when S_WAIT_TS_RESET =>\r
-        if (wait_timer_done = '0') then\r
-          NEXT_STATE        <= S_WAIT_TS_RESET;\r
-        else\r
-          NEXT_STATE        <= S_NEXT_CYCLE;\r
-        end if;\r
-        \r
       when S_NEXT_CYCLE =>\r
         if (trigger_cycle_ctr > 0) then\r
+          trigger_o_x           <= '1';\r
           trigger_cycle_ctr_x <= trigger_cycle_ctr - 1;\r
-          wait_timer_init_x   <= reg_trigger_length;\r
-          NEXT_STATE          <= S_SET_TRIGGER;\r
+          if (reg_testpulse_length > 0) then\r
+            wait_timer_init_x   <= reg_testpulse_length;\r
+            NEXT_STATE          <= S_SET_TESTPULSE;\r
+          else\r
+            wait_timer_init_x   <= reg_trigger_period;\r
+            NEXT_STATE          <= S_WAIT_TRIGGER_END;\r
+          end if;\r
         else\r
-          NEXT_STATE          <= S_IDLE;\r
+          NEXT_STATE            <= S_IDLE;\r
         end if;\r
 \r
-      when S_SET_TRIGGER =>\r
-        trigger_o_x <= '1';\r
+      when S_SET_TESTPULSE =>\r
+        testpulse_o_x         <= '1';\r
         if (wait_timer_done = '0') then\r
-          NEXT_STATE          <= S_SET_TRIGGER;\r
+          NEXT_STATE          <= S_SET_TESTPULSE;\r
         else\r
-          wait_timer_init_x   <= reg_trigger_period - reg_trigger_length;\r
-          NEXT_STATE          <= S_WAIT_TRIGGER;\r
+          wait_timer_init_x   <= reg_trigger_period - reg_testpulse_length;\r
+          NEXT_STATE          <= S_WAIT_TRIGGER_END;\r
         end if;\r
         \r
-      when S_WAIT_TRIGGER =>\r
+      when S_WAIT_TRIGGER_END =>\r
         if (wait_timer_done = '0') then\r
-          NEXT_STATE        <= S_WAIT_TRIGGER;\r
+          NEXT_STATE        <= S_WAIT_TRIGGER_END;\r
         else\r
           NEXT_STATE        <= S_NEXT_CYCLE;\r
         end if;\r
@@ -177,7 +184,7 @@ begin
       if( RESET_IN = '1' ) then\r
         reg_trigger_period     <= x"00ff";\r
         reg_trigger_num_cycles <= x"01";\r
-        reg_trigger_length     <= x"000a";\r
+        reg_testpulse_length   <= (others => '0');\r
         reg_reset_on           <= '0';\r
         slv_data_out_o         <= (others => '0');\r
         slv_no_more_data_o     <= '0';\r
@@ -203,7 +210,7 @@ begin
               reg_trigger_num_cycles   <= unsigned(SLV_DATA_IN(7 downto 0));\r
               slv_ack_o                <= '1';\r
             when x"0003" =>\r
-              reg_trigger_length       <= unsigned(SLV_DATA_IN(15 downto 0));\r
+              reg_testpulse_length     <= unsigned(SLV_DATA_IN(15 downto 0));\r
               slv_ack_o                <= '1';\r
             when x"0004" =>\r
               reg_reset_on             <=  SLV_DATA_IN(0);\r
@@ -225,7 +232,7 @@ begin
               slv_ack_o                   <= '1';\r
             when x"0003" =>\r
               slv_data_out_o(15 downto 0) <=\r
-                std_logic_vector(reg_trigger_length);\r
+                std_logic_vector(reg_testpulse_length);\r
               slv_ack_o                   <= '1';\r
             when x"0004" =>\r
               slv_data_out_o(0)           <= reg_reset_on;\r
@@ -249,6 +256,7 @@ begin
   -- Trigger Output\r
   TRIGGER_OUT          <= trigger_o;\r
   TS_RESET_OUT         <= ts_reset_o;\r
+  TESTPULSE_OUT        <= testpulse_o;\r
 \r
   -- Slave Bus\r
   SLV_DATA_OUT         <= slv_data_out_o;    \r

diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd
index 87715246302b798cb1bf5304c8fdf3a13f140383..8f04494c6163c24f4712605a16c2c02e02345aa0 100644 (file)
--- a/nxyter/source/nx_trigger_handler.vhd
+++ b/nxyter/source/nx_trigger_handler.vhd
@@ -37,10 +37,8 @@ end entity;
 architecture Behavioral of nx_trigger_handler is\r
 \r
   signal start_cycle         : std_logic;\r
-  signal trigger_cycle_ctr   : unsigned(7 downto 0);\r
-  signal trigger_cycle_ctr_x : unsigned(7 downto 0);\r
-  signal wait_timer_init     : unsigned(15 downto 0);\r
-  signal wait_timer_init_x   : unsigned(15 downto 0);\r
+  signal wait_timer_init     : unsigned(9 downto 0);\r
+  signal wait_timer_init_x   : unsigned(9 downto 0);\r
   signal wait_timer_done     : std_logic;\r
   signal trigger_o           : std_logic;\r
   signal trigger_o_x         : std_logic;\r
@@ -61,7 +59,7 @@ architecture Behavioral of nx_trigger_handler is
   signal slv_unknown_addr_o       : std_logic;\r
   signal slv_ack_o                : std_logic;\r
 \r
-  signal reg_timestamp_hold_delay : unsigned(15 downto 0);\r
+  signal reg_timestamp_hold_delay : unsigned(9 downto 0);\r
   \r
 begin\r
 \r
@@ -76,7 +74,7 @@ begin
   -- Timer\r
   nx_timer_1: nx_timer\r
     generic map (\r
-      CTR_WIDTH => 16\r
+      CTR_WIDTH => 10\r
       )\r
     port map (\r
       CLK_IN         => CLK_IN,\r
@@ -123,8 +121,12 @@ begin
       when  S_IDLE =>\r
         if (TRIGGER_IN = '1') then\r
           trigger_o_x         <= '1';\r
-          wait_timer_init_x   <= reg_timestamp_hold_delay;\r
-          NEXT_STATE          <= S_WAIT_HOLD;\r
+          if (reg_timestamp_hold_delay > 0) then\r
+            wait_timer_init_x   <= reg_timestamp_hold_delay;\r
+            NEXT_STATE          <= S_WAIT_HOLD;\r
+          else\r
+            NEXT_STATE          <= S_WAIT_TRIGGER_RELEASE;\r
+          end if;\r
         else\r
            trigger_busy_o_x   <= '0';\r
            NEXT_STATE         <= S_IDLE;\r
@@ -133,7 +135,7 @@ begin
       when S_WAIT_HOLD =>\r
         if (wait_timer_done = '1') then\r
           timestamp_hold_o_x  <= '1';\r
-          NEXT_STATE          <= S_IDLE;\r
+          NEXT_STATE          <= S_WAIT_TRIGGER_RELEASE;\r
         else\r
           NEXT_STATE          <= S_WAIT_HOLD ;\r
         end if;\r
@@ -161,37 +163,39 @@ begin
         slv_unknown_addr_o       <= '0';\r
         start_cycle              <= '0';\r
         slv_ack_o                <= '0';\r
-        reg_timestamp_hold_delay <= x"00ff";\r
+        reg_timestamp_hold_delay <= (others => '0');\r
       else\r
         slv_unknown_addr_o <= '0';\r
         slv_no_more_data_o <= '0';\r
         slv_data_out_o     <= (others => '0');\r
+        slv_ack_o          <= '0';\r
         start_cycle        <= '0';\r
-\r
+        \r
         if (SLV_WRITE_IN  = '1') then\r
           case SLV_ADDR_IN is\r
             when x"0000" =>\r
-              reg_timestamp_hold_delay <= SLV_DATA_IN(15 downto 0);\r
+              reg_timestamp_hold_delay <= SLV_DATA_IN(9 downto 0);\r
               slv_ack_o                <= '1';\r
+              \r
             when others =>\r
               slv_unknown_addr_o       <= '1';\r
-              slv_ack_o                <= '0';\r
+\r
           end case;\r
 \r
         elsif (SLV_READ_IN = '1') then\r
           case SLV_ADDR_IN is\r
+\r
             when x"0000" =>\r
-              slv_data_out_o(15 downto 0)  <=\r
+              slv_data_out_o(9 downto 0)   <=\r
                 std_logic_vector(reg_timestamp_hold_delay);\r
-              slv_data_out_o(31 downto 16) <= (others => '0');\r
+              slv_data_out_o(31 downto 10) <= (others => '0');\r
               slv_ack_o                    <= '1';\r
+\r
             when others =>\r
               slv_unknown_addr_o           <= '1';\r
-              slv_ack_o                    <= '0';\r
+\r
           end case;\r
 \r
-        else\r
-          slv_ack_o            <= '0';\r
         end if;\r
       end if;\r
     end if;           \r

diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd
index 34d5ddd5b986f8b4d16cd9420c2b6e93a911d576..e101e6ab7487af3b36de9838b7d94cb19cf160dc 100644 (file)
--- a/nxyter/source/nxyter.vhd
+++ b/nxyter/source/nxyter.vhd
@@ -116,7 +116,8 @@ architecture Behavioral of nXyter_FEE_board is
   signal timestamp_hold       : std_logic;
   signal trigger_busy         : std_logic;
   
-  -- Testpulse Generator
+  -- Trigger Generator
+  signal trigger              : std_logic;
   signal nx_testpulse_o       : std_logic;
   
 begin
@@ -133,8 +134,9 @@ begin
   DEBUG_LINE_OUT(6)            <= timestamp_hold;
   DEBUG_LINE_OUT(7)            <= nx_token_return;
   DEBUG_LINE_OUT(8)            <= nx_nomore_data;
-  DEBUG_LINE_OUT(9)            <= trigger_busy;
-  DEBUG_LINE_OUT(15 downto 10) <= (others => '0');
+  DEBUG_LINE_OUT(9)            <= trigger;
+  DEBUG_LINE_OUT(10)           <= trigger_busy;
+  DEBUG_LINE_OUT(15 downto 11) <= (others => '0');
 
 -------------------------------------------------------------------------------
 -- Port Maps
@@ -166,7 +168,7 @@ begin
 
       PORT_ADDR_MASK      => ( 0 => 3,          -- Control Register Handler
                                1 => 0,          -- I2C master
-                               2 => 1,          -- Timestamp Fifo
+                               2 => 2,          -- Timestamp Fifo
                                3 => 0,          -- Data Buffer
                                4 => 0,          -- SPI Master
                                5 => 3,          -- Trigger Generator
@@ -218,8 +220,8 @@ begin
       BUS_WRITE_ENABLE_OUT(2)             => slv_write(2),
       BUS_DATA_OUT(2*32+31 downto 2*32)   => slv_data_wr(2*32+31 downto 2*32),
       BUS_DATA_IN(2*32+31 downto 2*32)    => slv_data_rd(2*32+31 downto 2*32),
-      BUS_ADDR_OUT(2*16+0)                => slv_addr(2*16+0),
-      BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open,
+      BUS_ADDR_OUT(2*16+1 downto 2*16)    => slv_addr(2*16+1 downto 2*16),
+      BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open,
       BUS_TIMEOUT_OUT(2)                  => open,
       BUS_DATAREADY_IN(2)                 => slv_ack(2),
       BUS_WRITE_ACK_IN(2)                 => slv_ack(2),
@@ -399,8 +401,6 @@ begin
       DEBUG_OUT           => open
       );
 
---  DEBUG_LINE_OUT(15) <= nx_testpulse_o;
-  
 -------------------------------------------------------------------------------
 -- Data Buffer FIFO
 -------------------------------------------------------------------------------
@@ -484,7 +484,7 @@ begin
     port map (
       CLK_IN                => CLK_IN,
       RESET_IN              => RESET_IN,
-      TRIGGER_IN            => nx_testpulse_o,
+      TRIGGER_IN            => trigger,
       TRIGGER_RELEASE_IN    => trigger_release,
       TRIGGER_OUT           => trigger_ack,
       TIMESTAMP_HOLD_OUT    => timestamp_hold,
@@ -497,7 +497,7 @@ begin
       SLV_ACK_OUT           => slv_ack(7),
       SLV_NO_MORE_DATA_OUT  => slv_no_more_data(7),
       SLV_UNKNOWN_ADDR_OUT  => slv_unknown_addr(7),
-      -- DEBUG_OUT(14 downto 0) => DEBUG_LINE_OUT(14 downto 0)
+      -- DEBUG_OUT           => DEBUG_LINE_OUT
       DEBUG_OUT             => open
       );
   
@@ -509,8 +509,9 @@ begin
     port map (
       CLK_IN               => CLK_IN,
       RESET_IN             => RESET_IN,
-      TRIGGER_OUT          => nx_testpulse_o,
+      TRIGGER_OUT          => trigger,
       TS_RESET_OUT         => nx_ts_reset_2,
+      TESTPULSE_OUT        => nx_testpulse_o,
       SLV_READ_IN          => slv_read(5),
       SLV_WRITE_IN         => slv_write(5),
       SLV_DATA_OUT         => slv_data_rd(5*32+31 downto 5*32),
@@ -529,7 +530,7 @@ begin
 -------------------------------------------------------------------------------
   nx_ts_reset_o     <= nx_ts_reset_1 or nx_ts_reset_2; 
   NX_RESET_OUT      <= not nx_ts_reset_o;
-  NX_TESTPULSE_OUT  <= not nx_testpulse_o;
+  NX_TESTPULSE_OUT  <= nx_testpulse_o;
 
 -------------------------------------------------------------------------------
 -- I2C Signals

diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd
index 16adf197ab344417d0c9d1c1cc6ee83af3be8712..e3e87a400348c6b0226d0855870237a9dcd5e263 100644 (file)
--- a/nxyter/source/nxyter_components.vhd
+++ b/nxyter/source/nxyter_components.vhd
@@ -366,6 +366,7 @@ component nx_trigger_generator
     RESET_IN             : in  std_logic;
     TRIGGER_OUT          : out std_logic;
     TS_RESET_OUT         : out std_logic;
+    TESTPULSE_OUT        : out std_logic;
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);