constant INIT_ADDRESS : std_logic_vector := x"F60E";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"90";
- constant INCLUDE_UART : integer := c_NO; --300 slices
- constant INCLUDE_SPI : integer := c_NO; --300 slices
- constant INCLUDE_ADC : integer := c_YES; --300 slices
- constant INCLUDE_LCD : integer := c_NO; --800 slices
- constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_NO;
+ constant INCLUDE_ADC : integer := c_YES;
+ constant INCLUDE_I2C : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
--input monitor and trigger generation logic
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
- constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_STATISTICS : integer := c_NO;
constant TRIG_GEN_INPUT_NUM : integer := 32;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 32;
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
- t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_2.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan1_0/serdes_sync_2.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan1_0/serdes_sync_2.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes/dual_serdes.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes/serdes0/serdes0_softlogic.v"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes/serdes1/serdes1_softlogic.v"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
-add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes_1/dual_serdes_1.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0_softlogic.v"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1_softlogic.v"
+
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+#add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
end entity;
architecture arch of mdcoep is
- constant INTERFACE_NUM : integer := 3;
+ constant INTERFACE_NUM : integer := 4;
attribute syn_keep : boolean;
THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_2
generic map(
+ DUAL => 0,
IS_SYNC_SLAVE => (c_YES,c_NO)
)
port map(
---------------------------------------------------------------------------
-- Second TrbNet Downlink
---------------------------------------------------------------------------
- THE_DOWN_INTERFACE_2 : entity work.med_ecp5_sfp_sync
+ THE_DOWN_INTERFACE_2 : entity work.med_ecp5_sfp_sync_2
generic map(
- SERDES_NUM => 2,
- IS_SYNC_SLAVE => c_NO
+ DUAL => 1,
+ IS_SYNC_SLAVE => (c_NO,c_NO)
+
)
port map(
CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(2),
- MEDIA_INT2MED => int2med(2),
-
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
+ MEDIA_MED2INT => med2int(2 to 3),
+ MEDIA_INT2MED => int2med(2 to 3),
--SFP Connection
- SD_PRSNT_N_IN => GPIO(5),
- SD_LOS_IN => GPIO(5),
- SD_TXDIS_OUT => GPIO(4),
+ SD_PRSNT_N_IN(0) => GPIO(5),
+ SD_LOS_IN(0) => GPIO(5),
+ SD_TXDIS_OUT(0) => GPIO(4),
+ SD_PRSNT_N_IN(1) => GPIO(9),
+ SD_LOS_IN(1) => GPIO(9),
+ SD_TXDIS_OUT(1) => GPIO(8),
--Control Interface
BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
- -- Status and control port
- STAT_DEBUG => open, --med_stat_debug(63 downto 0),
- CTRL_DEBUG => open
+ BUS_TX => bussci2_tx
);
---------------------------------------------------------------------------
INIT_ADDRESS => INIT_ADDRESS,
MII_NUMBER => INTERFACE_NUM,
MII_IS_UPLINK => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- MII_IS_DOWNLINK => (0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0),
+ MII_IS_DOWNLINK => (0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0),
MII_IS_UPLINK_ONLY => (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
USE_ONEWIRE => c_I2C,
HARDWARE_VERSION => HARDWARE_INFO,
trigger_inputs_i <= (others => '0');
-TEST(1) <= ADC_CS;
-TEST(2) <= ADC_MOSI;
-TEST(3) <= ADC_MISO;
-TEST(4) <= ADC_SCK;
+-- TEST(1) <= ADC_CS;
+-- TEST(2) <= ADC_MOSI;
+-- TEST(3) <= ADC_MISO;
+-- TEST(4) <= ADC_SCK;
---------------------------------------------------------------------------
-- LED
LED(2) <= FLASH_SELECT and not led_off;
LED(3) <= (med2int(1).stat_op(10) or med2int(1).stat_op(11)) and not led_off;
- LED(4) <= med2int(1).stat_op(9) and not led_off;
+ LED(4) <= (med2int(2).stat_op(10) or med2int(2).stat_op(11)) and not led_off;
+ LED(5) <= (med2int(3).stat_op(10) or med2int(3).stat_op(11)) and not led_off;