added CLEAR for initial reset

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd
index a6bae19b9f2b1444aa73c5392eccc8388dd67ff3..7870338de767a57f85a87664c31d11c671c3776b 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_125M_RS.vhd
@@ -11,13 +11,13 @@ use work.med_sync_define_RS.all;
 
 entity med_ecp3_sfp_sync_all_125M_RS is
   generic(
-    IS_MODE            : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED);
-    IS_WAP_ZERO        : integer := 1
+    IS_MODE            : int_array_t(0 to 3) := (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED)
   );
   port(
     -- Clocks and reset
     CLK_REF_FULL       : in  std_logic; -- TRBnet reference clock
     SYSCLK             : in  std_logic; -- FPGA fabric clock
+    CLEAR              : in  std_logic;
     RESET              : in  std_logic; -- synchronous reset
     -- Media Interface TX/RX
     MEDIA_MED2INT      : out med2int_array_t(0 to 3);
@@ -386,7 +386,7 @@ begin
       fpga_txrefclk        => MASTER_CLK_IN, -- reference TX clock
       tx_serdes_rst_c      => '0',
       tx_pll_lol_qd_s      => TX_PLL_LOL_OUT,
-      rst_qd_c             => QUAD_RST_IN, 
+      rst_qd_c             => CLEAR, --QUAD_RST_IN, 
       serdes_rst_qd_c      => '0', -- was wrong
       tx_sync_qd_c         => SYNC_TX_PLL_IN
     );
@@ -401,7 +401,6 @@ gen_control : for i in 0 to 3 generate
   gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate
     THE_MED_CONTROL : entity work.med_sync_control_RS
       generic map(
-        IS_WAP_ZERO   => IS_WAP_ZERO,
         IS_MODE       => IS_MODE(i)
       )
       port map(
@@ -411,6 +410,7 @@ gen_control : for i in 0 to 3 generate
         CLK_RXHALF         => clk_rx_half(i),
         CLK_TXI            => clk_tx_full(i),
         CLK_REF            => CLK_REF_FULL,
+        CLEAR              => CLEAR,
         RESET              => RESET,
         -- Media Interface
         MEDIA_MED2INT      => MEDIA_MED2INT(i),
@@ -470,6 +470,11 @@ gen_control : for i in 0 to 3 generate
     MEDIA_MED2INT(i).dataready <= '0';
     MEDIA_MED2INT(i).tx_read   <= '1';
     MEDIA_MED2INT(i).stat_op   <= x"0007";
+    cv_cnt(i)                  <= (others => '0');
+    word_sync_i(i)             <= '0';
+    RX_DLM_WORD_OUT(i*8+7 downto i*8) <= (others => '0');
+    rx_rst_i(i)                       <= '0';
+    rx_rst_word_i(i*8+7 downto i*8)   <= (others => '0');
   end generate;
   
 end generate;
@@ -484,7 +489,7 @@ end generate;
   THE_SCI_READER : entity work.sci_reader_RS
     port map(
       CLK         => SYSCLK,
-      RESET       => RESET,
+      RESET       => CLEAR, --'0', -- need for link establishment
       --SCI
       SCI_WRDATA  => sci_data_in_i,
       SCI_RDDATA  => sci_data_out_i,
@@ -508,8 +513,7 @@ end generate;
       MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1),
       MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2),
       MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3),
-      MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'),
-      DEBUG_OUT   => open
+      MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0')
     );
 
   cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK);    
@@ -521,7 +525,7 @@ end generate;
   -- SerDes #3 is used for debugging
 --  DEBUG_OUT <= debug_i(0*32+31 downto 0*32);
   -- all SerDes debug
-  DEBUG_OUT(31 downto 24) <= debug_i(3*32+7 downto 3*32);
+  DEBUG_OUT(31 downto 24) <= stat_fsm_reset_i(3*32+7 downto 3*32);--debug_i(3*32+7 downto 3*32);
   DEBUG_OUT(23 downto 16) <= debug_i(2*32+7 downto 2*32);
   DEBUG_OUT(15 downto 8)  <= debug_i(1*32+7 downto 1*32);
   DEBUG_OUT(7 downto 0)   <= debug_i(0*32+7 downto 0*32);

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 2b1fae4b793ab64bde74e3dd5ac75d3b8b241226..21345e322aae4d71a3be33fab2d807652334c380 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -4,12 +4,10 @@ USE IEEE.numeric_std.all;
 
 library work;
 use work.trb_net_std.all;
---use work.trb_net_components.all;
 use work.med_sync_define_RS.all;
 
 entity med_sync_control_RS is
   generic(
-    IS_WAP_ZERO   : integer := 1; -- should be 1 for synchronous operation
     IS_MODE       : integer := c_IS_UNUSED
   );
   port(
@@ -19,6 +17,7 @@ entity med_sync_control_RS is
     CLK_RXHALF         : in  std_logic; -- used for media interface
     CLK_TXI            : in  std_logic; -- TX clock, from SerDes TX channel
     CLK_REF            : in  std_logic; -- SerDes reference clock
+    CLEAR              : in  std_logic;
     RESET              : in  std_logic;
     -- Media Interface
     MEDIA_MED2INT      : out MED2INT; -- Media Interface OUT
@@ -104,11 +103,6 @@ architecture med_sync_control_arch of med_sync_control_RS is
   signal link_rx_null_i           : std_logic;
   signal link_rx_null_qref        : std_logic;
   
---  attribute syn_keep : boolean;
---  attribute syn_preserve : boolean;  
---  attribute syn_keep of rx_lsm_state         : signal is true;
---  attribute syn_preserve of rx_lsm_state     : signal is true;
-
 begin
 
 -------------------------------------------------      
@@ -126,7 +120,7 @@ begin
 -------------------------------------------------
   THE_MAIN_RX_RST: main_rx_reset_RS 
     port map(
-      CLEAR             => '0',
+      CLEAR             => CLEAR, --'0', -- DO NOT USE
       CLK_REF           => CLK_REF,
       CDR_LOL_IN        => RX_CDR_LOL_IN,
       CV_IN             => RX_CV_IN,
@@ -165,7 +159,7 @@ begin
     port map(
       CLK_RXI                => CLK_RXI,
       CLK_SYS                => CLK_SYS,
-      RESET                  => '0', --reset_i,
+      RESET                  => CLEAR, --'0', -- DO NOT USE
       --
       RX_DATA_OUT            => media_med2int_i.data,
       RX_PACKET_NUMBER_OUT   => media_med2int_i.packet_num,
@@ -207,7 +201,7 @@ begin
     port map(
       CLK_TXI                  => CLK_TXI,
       CLK_SYS                  => CLK_SYS,
-      RESET                    => '0', --reset_i,
+      CLEAR                    => CLEAR, --'0', -- DO NOT USE
       -- Media Interface
       TX_DATA_IN               => MEDIA_INT2MED.data,
       TX_PACKET_NUMBER_IN      => MEDIA_INT2MED.packet_num,
@@ -249,7 +243,6 @@ begin
 -------------------------------------------------   
   led_ok  <= link_full_done_i when rising_edge(CLK_SYS); 
   led_rx  <= (media_med2int_i.dataready or led_rx)  and not timer(20) when rising_edge(CLK_SYS);
---  led_tx  <= (MEDIA_INT2MED.dataready or led_tx or sd_los_q)  and not timer(20) when rising_edge(CLK_SYS);
   led_tx  <= (MEDIA_INT2MED.dataready or led_tx or SFP_LOS_IN)  and not timer(20) when rising_edge(CLK_SYS);
 
   ROC_TIMER_PROC: process( CLK_SYS, RESET )
@@ -327,15 +320,6 @@ begin
   LINK_RX_NULL_OUT <= link_rx_null_qref;
   
 -- TEST_LINE signals
---  DEBUG_OUT(31 downto 12) <= (others => '0');
---  DEBUG_OUT(11)           <= link_full_done_qsys;
---  DEBUG_OUT(10)           <= link_half_done_qsys;
---  DEBUG_OUT(9)            <= '0';
---  DEBUG_OUT(8)            <= link_rx_ready_qsys;
---  DEBUG_OUT(7)            <= link_tx_ready_qsys;
---  DEBUG_OUT(6 downto 2)   <= (others => '0');
---  DEBUG_OUT(1 downto 0)   <= debug_rx_control_i(1 downto 0);
---  DEBUG_OUT        <= (others => '0');
   DEBUG_OUT(31 downto 8)  <= (others => '0');
   -- these signals will be used outside!
   DEBUG_OUT(7 downto 4)   <= (others => '0');

diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd
index 4ed1ccf609a385291e8b49cbb40d3c91570d0dbc..8aefe48f4427cc3948bd6310e1d0a4cbe6767e66 100644 (file)
--- a/media_interfaces/sync/med_sync_define_RS.vhd
+++ b/media_interfaces/sync/med_sync_define_RS.vhd
@@ -29,12 +29,10 @@ component main_rx_reset_RS is
   port (\r
     CLEAR             : in  std_logic;\r
     CLK_REF           : in  std_logic;\r
-    PLL_LOL_IN        : in  std_logic;\r
     CDR_LOL_IN        : in  std_logic;\r
     CV_IN             : in  std_logic;\r
     LSM_IN            : in  std_logic;\r
     LOS_IN            : in  std_logic;\r
-    SD_LOS_IN         : in  std_logic;\r
     WAP_ZERO_IN       : in  std_logic;\r
     -- outputs\r
     WAP_REQ_OUT       : out std_logic;\r
@@ -45,6 +43,22 @@ component main_rx_reset_RS is
   );\r
 end component;  \r
 \r
+component main_tx_reset_RS is\r
+  port(\r
+    CLEAR                : in  std_logic; -- async reset, active high\r
+    CLK_REF              : in  std_logic; -- usually RX_REFCLK, not TX_REFCLK!   \r
+    TX_PLL_LOL_QD_A_IN   : in  std_logic; -- QUAD A\r
+    TX_PLL_LOL_QD_B_IN   : in  std_logic; -- QUAD B\r
+    TX_PLL_LOL_QD_C_IN   : in  std_logic; -- QUAD C\r
+    TX_PLL_LOL_QD_D_IN   : in  std_logic; -- QUAD D\r
+    TX_CLOCK_AVAIL_IN    : in  std_logic; -- recovered RX clock available (if needed)\r
+    TX_PCS_RST_CH_C_OUT  : out std_logic; -- PCS reset\r
+    SYNC_TX_QUAD_OUT     : out std_logic; -- sync all QUADs to TX bit 0\r
+    LINK_TX_READY_OUT    : out std_logic; -- TX lane can use used now\r
+    STATE_OUT            : out std_logic_vector(3 downto 0)\r
+  );\r
+end component;\r
+\r
 component signal_sync is\r
   generic(\r
     WIDTH : integer := 1;     --\r
@@ -75,22 +89,6 @@ component lattice_ecp3_fifo_18x16_dualport_oreg
   );\r
 end component;\r
 \r
-component main_tx_reset_RS is\r
-  port(\r
-    CLEAR                : in  std_logic; -- async reset, active high\r
-    CLK_REF              : in  std_logic; -- usually RX_REFCLK, not TX_REFCLK!   \r
-    TX_PLL_LOL_QD_A_IN   : in  std_logic; -- QUAD A\r
-    TX_PLL_LOL_QD_B_IN   : in  std_logic; -- QUAD B\r
-    TX_PLL_LOL_QD_C_IN   : in  std_logic; -- QUAD C\r
-    TX_PLL_LOL_QD_D_IN   : in  std_logic; -- QUAD D\r
-    TX_CLOCK_AVAIL_IN    : in  std_logic; -- recovered RX clock available (if needed)\r
-    TX_PCS_RST_CH_C_OUT  : out std_logic; -- PCS reset\r
-    SYNC_TX_QUAD_OUT     : out std_logic; -- sync all QUADs to TX bit 0\r
-    LINK_TX_READY_OUT    : out std_logic; -- TX lane can use used now\r
-    STATE_OUT            : out std_logic_vector(3 downto 0)\r
-  );\r
-end component;\r
-\r
 component rx_control_RS is\r
   port(\r
     CLK_RXI                        : in  std_logic;\r
@@ -127,7 +125,7 @@ component tx_control_RS is
   port(\r
     CLK_TXI                        : in  std_logic;\r
     CLK_SYS                        : in  std_logic;\r
-    RESET                          : in  std_logic; -- async/sync reset\r
+    CLEAR                          : in  std_logic;\r
     -- Media Interface\r
     TX_DATA_IN                     : in  std_logic_vector(15 downto 0); -- media interface\r
     TX_PACKET_NUMBER_IN            : in  std_logic_vector(2 downto 0); -- media interface\r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 08e67ac434698362102afd3a0c7eea0f44b9dc42..f5fca7d36ca6bbd85208f6e4411052574cc964f9 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -27,8 +27,7 @@ entity sci_reader_RS is
     --Slowcontrol
     BUS_RX           : in  CTRLBUS_RX;
     BUS_TX           : out CTRLBUS_TX;    
-    MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0');
-    DEBUG_OUT        : out std_logic_vector(31 downto 0)
+    MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0')
   );
 end entity;
 
@@ -141,5 +140,6 @@ begin
   end process PROC_SCI_CTRL;
 
   WA_POS_OUT <= wa_position;
-
+  WA_ACK_OUT <= '0';
+  
 end architecture;

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index 61bfbb50edd727d488ab9ad518a7e53943dde08c..f553dfa0e299f2fa3d366d983a3c0a8e40aecb7a 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -16,7 +16,7 @@ entity tx_control_RS is
   port(\r
     CLK_TXI                        : in  std_logic;\r
     CLK_SYS                        : in  std_logic;\r
-    RESET                          : in  std_logic; -- async/sync reset\r
+    CLEAR                          : in  std_logic;\r
     -- Media Interface\r
     TX_DATA_IN                     : in  std_logic_vector(15 downto 0); -- media interface\r
     TX_PACKET_NUMBER_IN            : in  std_logic_vector(2 downto 0); -- media interface\r
@@ -173,12 +173,12 @@ begin
       AlmostFull        => ct_fifo_afull\r
       );\r
 \r
-  THE_RD_PROC : process(CLK_SYS)\r
-    begin\r
-      if rising_edge(CLK_SYS) then\r
-        buf_tx_read_out  <= link_active_qsys and not ct_fifo_afull ;\r
-      end if;\r
-    end process;\r
+  THE_RD_PROC: process( CLK_SYS )\r
+  begin\r
+    if rising_edge(CLK_SYS) then\r
+      buf_tx_read_out  <= link_active_qsys and not ct_fifo_afull ;\r
+    end if;\r
+  end process;\r
 \r
   ct_fifo_reset <= not link_active_qtx;\r
   TX_READ_OUT   <= buf_tx_read_out;\r
@@ -195,64 +195,64 @@ begin
 ----------------------------------------------------------------------\r
 -- RAM\r
 ----------------------------------------------------------------------\r
-  THE_RAM_WR_PROC : process(CLK_TXI)\r
-    begin\r
-      if( rising_edge(CLK_TXI) ) then\r
-        ram_write   <= last_ct_fifo_read and not last_ct_fifo_empty;\r
-      end if;\r
-    end process;\r
+  THE_RAM_WR_PROC: process( CLK_TXI )\r
+  begin\r
+    if( rising_edge(CLK_TXI) ) then\r
+      ram_write   <= last_ct_fifo_read and not last_ct_fifo_empty;\r
+    end if;\r
+  end process THE_RAM_WR_PROC;\r
 \r
 --RAM\r
-  THE_RAM_PROC : process(CLK_TXI)\r
-    begin\r
-      if( rising_edge(CLK_TXI) ) then\r
-        if( ram_write = '1' ) then\r
-          ram((to_integer(ram_write_addr))) <= tx_data_200;\r
-        end if;\r
-        next_ram_dout <= ram(to_integer(ram_read_addr));\r
-        ram_dout <= next_ram_dout;\r
+  THE_RAM_PROC: process( CLK_TXI )\r
+  begin\r
+    if( rising_edge(CLK_TXI) ) then\r
+      if( ram_write = '1' ) then\r
+        ram((to_integer(ram_write_addr))) <= tx_data_200;\r
       end if;\r
-    end process;\r
+      next_ram_dout <= ram(to_integer(ram_read_addr));\r
+      ram_dout <= next_ram_dout;\r
+    end if;\r
+  end process THE_RAM_PROC;\r
 \r
 --RAM read pointer\r
-  THE_READ_CNT : process(CLK_TXI)\r
-    begin\r
-      if( rising_edge(CLK_TXI) ) then\r
-        if( link_active_qtx = '0' ) then\r
-          ram_read_addr <= (others => '0');\r
-        elsif( ram_read = '1' ) then\r
-          ram_read_addr <= ram_read_addr + to_unsigned(1,1);\r
-        end if;\r
+  THE_READ_CNT: process( CLK_TXI )\r
+  begin\r
+    if( rising_edge(CLK_TXI) ) then\r
+      if( link_active_qtx = '0' ) then\r
+        ram_read_addr <= (others => '0');\r
+      elsif( ram_read = '1' ) then\r
+        ram_read_addr <= ram_read_addr + to_unsigned(1,1);\r
       end if;\r
-    end process;\r
+    end if;\r
+  end process THE_READ_CNT;\r
 \r
 --RAM write pointer\r
-  THE_WRITE_CNT : process(CLK_TXI)\r
-    begin\r
-      if( rising_edge(CLK_TXI) ) then\r
-        if( link_active_qtx = '0' ) then\r
-          ram_write_addr <= (others => '0');\r
-        elsif( ram_write = '1' ) then\r
-          ram_write_addr <= ram_write_addr + to_unsigned(1,1);\r
-        end if;\r
+  THE_WRITE_CNT: process( CLK_TXI )\r
+  begin\r
+    if( rising_edge(CLK_TXI) ) then\r
+      if( link_active_qtx = '0' ) then\r
+        ram_write_addr <= (others => '0');\r
+      elsif( ram_write = '1' ) then\r
+        ram_write_addr <= ram_write_addr + to_unsigned(1,1);\r
       end if;\r
-    end process;\r
+    end if;\r
+  end process THE_WRITE_CNT;\r
 \r
 --RAM fill level counter\r
-  THE_FILL_CNT : process(CLK_TXI)\r
-    begin\r
-      if( rising_edge(CLK_TXI) ) then\r
-        if( link_active_qtx = '0' ) then\r
-          ram_fill_level <= (others => '0');\r
-        else\r
-          ram_fill_level <= last_ram_write_addr - ram_read_addr;\r
-        end if;\r
+  THE_FILL_CNT: process( CLK_TXI )\r
+  begin\r
+    if( rising_edge(CLK_TXI) ) then\r
+      if( link_active_qtx = '0' ) then\r
+        ram_fill_level <= (others => '0');\r
+      else\r
+        ram_fill_level <= last_ram_write_addr - ram_read_addr;\r
       end if;\r
-    end process;\r
+    end if;\r
+  end process THE_FILL_CNT;\r
 \r
 --RAM empty\r
-  ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET = '1' else '0';\r
-  ram_afull <= '1' when ram_fill_level >= 4 else '0';\r
+  ram_empty <= '1' when ((last_ram_write_addr = ram_read_addr) or (CLEAR = '1')) else '0';\r
+  ram_afull <= '1' when (ram_fill_level >= 4) else '0';\r
 \r
   last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TXI);\r
 \r
@@ -260,141 +260,141 @@ begin
 -- TX control state machine\r
 ----------------------------------------------------------------------\r
 \r
-  THE_DATA_CONTROL_FSM : process(CLK_TXI, RESET)\r
-    begin\r
-      if( RESET = '1' ) then\r
-        current_state <= IDLE;\r
-        tx_k_i        <= '1';\r
-        tx_data_i     <= K_NULL;\r
-        word_sync_i   <= '0';\r
-      else \r
-        if( rising_edge(CLK_TXI) ) then\r
-          tx_k_i            <= '0';\r
-          word_sync_i       <= '0';\r
-          debug_sending_dlm <= '0';\r
-          debug_sending_rst <= '0';\r
+  THE_DATA_CONTROL_FSM: process( CLK_TXI, CLEAR, link_active_qtx )\r
+  begin\r
+    if( CLEAR = '1' ) then\r
+      current_state <= IDLE;\r
+      tx_k_i        <= '1';\r
+      tx_data_i     <= K_NULL;\r
+      word_sync_i   <= '0';\r
+    else \r
+      if( rising_edge(CLK_TXI) ) then\r
+        tx_k_i            <= '0';\r
+        word_sync_i       <= '0';\r
+        debug_sending_dlm <= '0';\r
+        debug_sending_rst <= '0';\r
           \r
-          case current_state is\r
-            when IDLE =>\r
-              tx_k_i      <= '1';\r
-              tx_data_i     <= K_NULL;\r
-              if( (link_tx_ready_qtx = '1') and (link_tx_null_qtx = '0') ) then\r
-                current_state <= SEND_IDLE_L;\r
-              else\r
-                current_state <= IDLE;\r
-              end if;\r
+        case current_state is\r
+          when IDLE =>\r
+            tx_k_i      <= '1';\r
+            tx_data_i     <= K_NULL;\r
+            if( (link_tx_ready_qtx = '1') and (link_tx_null_qtx = '0') ) then\r
+              current_state <= SEND_IDLE_L;\r
+            else\r
+              current_state <= IDLE;\r
+            end if;\r
         \r
-            when SEND_IDLE_L =>\r
-              tx_data_i   <= K_IDLE;\r
-              tx_k_i      <= '1';\r
-              if( WORD_SYNC_IN = '1' )then\r
-                current_state <= SEND_IDLE_H;\r
-              else\r
-                current_state <= SEND_IDLE_L;\r
-              end if;\r
-\r
-            when SEND_IDLE_H =>\r
-              word_sync_i <= '1';\r
-              if( send_steady_idle_int = '1' ) then\r
-                tx_data_i   <= D_IDLE1;\r
-              else\r
-                tx_data_i   <= D_IDLE0;\r
-              end if;\r
-\r
-            when SEND_DATA_L =>\r
-              tx_data_i     <= ram_dout(7 downto 0);\r
-              load_sop      <= ram_dout(16);\r
-              load_eop      <= ram_dout(17);\r
-              current_state <= SEND_DATA_H;\r
-\r
-            when SEND_DATA_H =>\r
-              word_sync_i <= '1';\r
-              tx_data_i   <= ram_dout(15 downto 8);\r
-\r
-            when SEND_DLM_L =>\r
-              tx_data_i         <= K_DLM;\r
-              tx_k_i            <= '1';\r
-              current_state     <= SEND_DLM_H;\r
-              debug_sending_dlm <= '1';\r
-\r
-            when SEND_DLM_H =>\r
-              word_sync_i <= '1';\r
-              tx_data_i   <= send_dlm_word_i;\r
-\r
-            when SEND_RST_L =>\r
-              tx_data_i         <= K_RST;\r
-              tx_k_i            <= '1';\r
-              current_state     <= SEND_RST_H;\r
-              debug_sending_rst <= '1';\r
-\r
-            when SEND_RST_H =>\r
-              word_sync_i <= '1';\r
-              tx_data_i   <= send_rst_word_i;\r
-\r
-            when others =>\r
+          when SEND_IDLE_L =>\r
+            tx_data_i   <= K_IDLE;\r
+            tx_k_i      <= '1';\r
+            if( WORD_SYNC_IN = '1' )then\r
+              current_state <= SEND_IDLE_H;\r
+            else\r
               current_state <= SEND_IDLE_L;\r
-          end case;\r
-\r
-          if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or\r
-                        (current_state = SEND_DLM_H)  or (current_state = SEND_RST_H) ) then\r
-            if   ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then\r
-              current_state     <= IDLE;\r
-            elsif( send_dlm_i = '1' ) then\r
-              current_state     <= SEND_DLM_L;\r
-            elsif( send_rst_i = '1' ) then\r
-              current_state     <= SEND_RST_L;\r
-            elsif( ram_empty = '0' ) then\r
-              current_state     <= SEND_DATA_L;\r
+            end if;\r
+\r
+          when SEND_IDLE_H =>\r
+            word_sync_i <= '1';\r
+            if( send_steady_idle_int = '1' ) then\r
+              tx_data_i   <= D_IDLE1;\r
             else\r
-              current_state     <= SEND_IDLE_L;\r
+              tx_data_i   <= D_IDLE0;\r
             end if;\r
 \r
+          when SEND_DATA_L =>\r
+            tx_data_i     <= ram_dout(7 downto 0);\r
+            load_sop      <= ram_dout(16);\r
+            load_eop      <= ram_dout(17);\r
+            current_state <= SEND_DATA_H;\r
+\r
+          when SEND_DATA_H =>\r
+            word_sync_i <= '1';\r
+            tx_data_i   <= ram_dout(15 downto 8);\r
+\r
+          when SEND_DLM_L =>\r
+            tx_data_i         <= K_DLM;\r
+            tx_k_i            <= '1';\r
+            current_state     <= SEND_DLM_H;\r
+            debug_sending_dlm <= '1';\r
+\r
+          when SEND_DLM_H =>\r
+            word_sync_i <= '1';\r
+            tx_data_i   <= send_dlm_word_i;\r
+\r
+          when SEND_RST_L =>\r
+            tx_data_i         <= K_RST;\r
+            tx_k_i            <= '1';\r
+            current_state     <= SEND_RST_H;\r
+            debug_sending_rst <= '1';\r
+\r
+           when SEND_RST_H =>\r
+            word_sync_i <= '1';\r
+            tx_data_i   <= send_rst_word_i;\r
+\r
+          when others =>\r
+            current_state <= SEND_IDLE_L;\r
+\r
+        end case;\r
+\r
+        if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or\r
+                      (current_state = SEND_DLM_H)  or (current_state = SEND_RST_H) ) then\r
+          if   ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then\r
+            current_state     <= IDLE;\r
+          elsif( send_dlm_i = '1' ) then\r
+            current_state     <= SEND_DLM_L;\r
+          elsif( send_rst_i = '1' ) then\r
+            current_state     <= SEND_RST_L;\r
+          elsif( ram_empty = '0' ) then\r
+            current_state     <= SEND_DATA_L;\r
+          else\r
+            current_state     <= SEND_IDLE_L;\r
           end if;\r
-        end if;\r
-      end if;\r
 \r
-            --async because of oreg.\r
-      if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H)) \r
-           and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') then\r
-        ram_read <= '1';\r
-      else \r
-        ram_read <= '0';\r
-      end if;\r
-      if RESET = '1' then\r
-        ram_read <= '0';\r
+        end if;\r
       end if;\r
+    end if;\r
 \r
-    end process;\r
+    --async because of oreg.\r
+    if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H)) \r
+         and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') then\r
+      ram_read <= '1';\r
+    else \r
+      ram_read <= '0';\r
+    end if;\r
+    if (CLEAR = '1') then\r
+      ram_read <= '0';\r
+    end if;\r
 \r
+  end process THE_DATA_CONTROL_FSM;\r
 \r
 ----------------------------------------------------------------------\r
 --\r
 ----------------------------------------------------------------------\r
 \r
-send_dlm_i      <= SEND_DLM_IN      when rising_edge(CLK_TXI);\r
-send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI);\r
+  send_dlm_i      <= SEND_DLM_IN      when rising_edge(CLK_TXI);\r
+  send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI);\r
 \r
 -- Send RST message\r
 -- UNTESTED\r
-  THE_STORE_RST_PROC: process( CLK_TXI, RESET )\r
-    begin\r
-      if( RESET = '1' ) then\r
+  THE_STORE_RST_PROC: process( CLK_TXI, CLEAR )\r
+  begin\r
+    if( CLEAR = '1' ) then\r
+      send_rst_i <= '0';\r
+      send_rst_word_i <= (others => '0');\r
+    elsif( rising_edge(CLK_TXI) ) then\r
+      if   ( link_active_qtx = '0' ) then\r
         send_rst_i <= '0';\r
         send_rst_word_i <= (others => '0');\r
-      elsif( rising_edge(CLK_TXI) ) then\r
-        if   ( link_active_qtx = '0' ) then\r
-          send_rst_i <= '0';\r
-          send_rst_word_i <= (others => '0');\r
-        elsif( SEND_RST_IN = '1' ) then\r
-          send_rst_i <= '1';\r
-          send_rst_word_i <= SEND_RST_WORD_IN;\r
-        elsif( current_state = SEND_RST_L ) then\r
-          send_rst_i <= '0';\r
-        elsif( current_state = SEND_RST_H ) then\r
-          send_rst_word_i <= (others => '0');\r
-        end if;\r
+      elsif( SEND_RST_IN = '1' ) then\r
+        send_rst_i <= '1';\r
+        send_rst_word_i <= SEND_RST_WORD_IN;\r
+      elsif( current_state = SEND_RST_L ) then\r
+        send_rst_i <= '0';\r
+      elsif( current_state = SEND_RST_H ) then\r
+        send_rst_word_i <= (others => '0');\r
       end if;\r
-    end process THE_STORE_RST_PROC;\r
+    end if;\r
+  end process THE_STORE_RST_PROC;\r
 \r
 ----------------------------------------------------------------------\r
 -- Debug\r
@@ -407,27 +407,27 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI);
   DEBUG_OUT(4)           <= '0'; --toggle_idle when rising_edge(CLK_TXI);\r
   DEBUG_OUT(3 downto 0)  <= state_bits when rising_edge(CLK_TXI);\r
   \r
-  process(CLK_SYS)\r
-    begin\r
-      if rising_edge(CLK_SYS) then\r
---        STAT_REG_OUT <= (others => '0');\r
-        STAT_REG_OUT(3 downto 0)   <= state_bits;\r
-        STAT_REG_OUT(7 downto 4)   <= (others => '0');\r
-        STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);\r
-        STAT_REG_OUT(17)           <= ram_empty;\r
-        STAT_REG_OUT(18)           <= link_active_qsys;\r
-        STAT_REG_OUT(19)           <= '0';\r
-        STAT_REG_OUT(21 downto 20) <= (others => '0');\r
-        STAT_REG_OUT(22)           <= load_eop;\r
-        STAT_REG_OUT(23)           <= send_dlm_i;\r
-        STAT_REG_OUT(26 downto 24) <= (others => '0');\r
-        STAT_REG_OUT(27)           <= ct_fifo_afull;\r
-        STAT_REG_OUT(28)           <= ct_fifo_read;\r
-        STAT_REG_OUT(29)           <= ct_fifo_write;\r
-        STAT_REG_OUT(30)           <= RESET;\r
-        STAT_REG_OUT(31)           <= '0';\r
-      end if;\r
-    end process;\r
+  THE_STAT_PROC: process( CLK_SYS )\r
+  begin\r
+    if rising_edge(CLK_SYS) then\r
+--      STAT_REG_OUT <= (others => '0');\r
+      STAT_REG_OUT(3 downto 0)   <= state_bits;\r
+      STAT_REG_OUT(7 downto 4)   <= (others => '0');\r
+      STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);\r
+      STAT_REG_OUT(17)           <= ram_empty;\r
+      STAT_REG_OUT(18)           <= link_active_qsys;\r
+      STAT_REG_OUT(19)           <= '0';\r
+      STAT_REG_OUT(21 downto 20) <= (others => '0');\r
+      STAT_REG_OUT(22)           <= load_eop;\r
+      STAT_REG_OUT(23)           <= send_dlm_i;\r
+      STAT_REG_OUT(26 downto 24) <= (others => '0');\r
+      STAT_REG_OUT(27)           <= ct_fifo_afull;\r
+      STAT_REG_OUT(28)           <= ct_fifo_read;\r
+      STAT_REG_OUT(29)           <= ct_fifo_write;\r
+      STAT_REG_OUT(30)           <= CLEAR;\r
+      STAT_REG_OUT(31)           <= '0';\r
+    end if;\r
+  end process THE_STAT_PROC;\r
 \r
   state_bits <= x"0" when current_state = IDLE else\r
                 x"1" when current_state = SEND_IDLE_L else\r