*** empty log message ***

diff --git a/compile_munich.pl b/compile_munich.pl
index 7243ef6afc6c5f8254502e52ffce457ead12a9fb..649829255c3e868bec8dc6b263f92716ae7f3880 100755 (executable)
--- a/compile_munich.pl
+++ b/compile_munich.pl
@@ -35,6 +35,23 @@ my $CTIME_String = localtime(time);
 print "Script started: $CTIME_String\n";
 system("echo $CTIME_String > workdir/benchmark.txt");
 
+# cleanup in workdir
+system("rm workdir/$TOPNAME.alt");
+system("rm workdir/$TOPNAME.bgn");
+system("rm workdir/$TOPNAME.bit");
+system("rm workdir/$TOPNAME.edf");
+system("rm workdir/$TOPNAME.fse");
+system("rm workdir/$TOPNAME.mrp");
+system("rm workdir/$TOPNAME.ncd");
+system("rm workdir/$TOPNAME.ngd");
+system("rm workdir/$TOPNAME.ngo");
+system("rm workdir/$TOPNAME.ngy");
+system("rm workdir/$TOPNAME.pad");
+system("rm workdir/$TOPNAME.par");
+system("rm workdir/$TOPNAME.sr?");
+system("rm workdir/$TOPNAME.tlg");
+system("rm workdir/$TOPNAME.twr*");
+
 # Create full lpf file
 system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
 system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");

diff --git a/cts_fpga1.prj b/cts_fpga1.prj
index 73cb5a8ca2849ae0d98dc6b04a2fc2684530de40..6782cd53ce1d7e70d0fe52add7ed08f52793577e 100644 (file)
--- a/cts_fpga1.prj
+++ b/cts_fpga1.prj
@@ -66,7 +66,10 @@ add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd"
 add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_var_oreg.vhd"
-add file -vhdl -lib work "../trbnet/lattice/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd"
 #############################
 
 add_file -vhdl -lib work "cts_fpga1.vhd"

diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd
index 10305353e26f9bda34d725464242fd348d08f3fe..f9feb660b3a30ed82edf6d9bf14d8284dbe31c28 100644 (file)
--- a/cts_fpga1.vhd
+++ b/cts_fpga1.vhd
@@ -18,8 +18,14 @@ entity cts_fpga1 is
   port(
     --Clocks
     CLK_200_IN          : in  std_logic;
-    ADO_CLKOUT          : out std_logic;
-    --Resets
+--    ADO_CLKOUT          : out std_logic;
+    FAKE_SERDES_RXD_P_IN    : in  std_logic;
+    FAKE_SERDES_RXD_N_IN    : in  std_logic;
+    FAKE_SERDES_TXD_P_OUT   : out std_logic;
+    FAKE_SERDES_TXD_N_OUT   : out std_logic;
+    FAKE_SERDES_REFCLK_P_IN : in  std_logic;
+    FAKE_SERDES_REFCLK_N_IN : in  std_logic;
+     --Resets
     RESET_FPGA_1        : in  std_logic;
     ADDON_RESET         : in  std_logic;
     --To TRB
@@ -208,6 +214,43 @@ architecture cts_fpga1_arch of cts_fpga1 is
 
 begin
 
+---------------------------------------------------------------------------
+-- Fakes
+---------------------------------------------------------------------------
+trg_release             <= '0';
+trg_error_pattern       <= (others => '0');
+fee_trg_release         <= '0';
+fee_trg_statusbits      <= (others => '0');
+fee_data                <= (others => '0');
+fee_data_local          <= (others => '0');
+fee_data_write          <= '0';
+fee_data_finished       <= '0';
+timing_trigger_feedback <= '0';
+med_stat_debug          <= (others => '0');
+my_address              <= (others => '0');
+regio_common_stat_reg   <= (others => '0');
+regio_stat_registers    <= (others => '0');
+
+-- RICH trigger connection
+RICH_TRIGGER_OUT        <= '0';
+RICH_TIMING_OUT         <= '0';
+RICH_RESERVED_OUT       <= '0';
+RICH_CLK_OUT            <= '0';
+
+-- LEDs
+LED_YELLOW              <= '0';
+LED_RED                 <= '0';
+LED_ORANGE              <= '0';
+LED_GREEN               <= '0';
+
+-- SFP status LEDs
+TRB3_TX_LED             <= '0';
+TRB3_RX_LED             <= '0';
+TRB3_OK_LED             <= '0';
+TRB2_TX_LED             <= '0';
+TRB2_RX_LED             <= '0';
+TRB2_OK_LED             <= '0';
+
 ---------------------------------------------------------------------------
 -- Clock & Reset state machine
 ---------------------------------------------------------------------------
@@ -222,7 +265,6 @@ begin
       LOCK     => pll_locked
       );
 
-
   THE_RESET_HANDLER : trb_net_reset_handler
     generic map(
       RESET_DELAY     => x"0EEE"
@@ -244,13 +286,13 @@ begin
 --  Media Interface
 ---------------------------------------------------------------------------
 
-THE_MEDIA_INTERFACE_0: trb_net16_med_scm_sfp_gbe
-generic map(
+  THE_MEDIA_INTERFACE_0: trb_net16_med_scm_sfp_gbe
+  generic map(
        SERDES_NUM    => 0,
        EXT_CLOCK     => c_NO,
        USE_200_MHZ   => c_YES
-)
-port map(
+  )
+  port map(
     CLK                => CLK_200_IN, -- raw 200MHz clock
     SYSCLK             => clk_100,    -- 100MHz from PLL
     RESET              => reset_i_100,
@@ -281,23 +323,7 @@ port map(
     CTRL_OP            => med_ctrl_op,
     STAT_DEBUG         => open,
     CTRL_DEBUG         => open
-   );
-
---      --SFP Connection
---      SD_RXD_P_IN              => F3_RXP,
---      SD_RXD_N_IN              => F3_RXN,
---      SD_TXD_P_OUT             => F3_TXP,
---      SD_TXD_N_OUT             => F3_TXN,
---      SD_REFCLK_P_IN           => open,
---      SD_REFCLK_N_IN           => open,
---      SD_PRSNT_N_IN            => '0',
---      SD_LOS_IN                => '0',
---      -- Status and control port
---      STAT_OP                  => med_stat_op,
---      CTRL_OP                  => med_ctrl_op,
---      STAT_DEBUG               => med_stat_debug,
---      CTRL_DEBUG               => (others => '0')
---    );
+  );
 
 ---------------------------------------------------------------------------
 -- TrbNet Endpoint
@@ -504,7 +530,7 @@ port map(
 ---------------------------------------------------------------------------
 -- Reboot FPGA
 ---------------------------------------------------------------------------
-  PROC_REBOOT : process (clk_100)
+  PROC_REBOOT: process (clk_100, reset_i_100)
     begin
       if reset_i_100 = '1' then
         PROGRAMN_OUT             <= '1';