--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58)
+-- Module Version: 4.4
+--/opt/lattice/isplever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 18 -depth 512 -no_enable -pe 10 -pf 508 -e
+
+-- Thu Mar 19 16:21:17 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity ecp2m_link_fifo is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end ecp2m_link_fifo;
+
+architecture Structure of ecp2m_link_fifo is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal full_i: std_logic;
+ signal rRst: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4: std_logic;
+ signal wcount_9: std_logic;
+ signal co3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_ci: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_8: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal iae_setcount_0: std_logic;
+ signal iae_setcount_1: std_logic;
+ signal ae_set_ctr_ci: std_logic;
+ signal iae_setcount_2: std_logic;
+ signal iae_setcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal iae_setcount_4: std_logic;
+ signal iae_setcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal iae_setcount_6: std_logic;
+ signal iae_setcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal iae_setcount_8: std_logic;
+ signal iae_setcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal ae_setcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal wcount_r0: std_logic;
+ signal wcount_r1: std_logic;
+ signal ae_setcount_0: std_logic;
+ signal ae_setcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal ae_setcount_2: std_logic;
+ signal ae_setcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal ae_setcount_4: std_logic;
+ signal ae_setcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r7: std_logic;
+ signal ae_setcount_6: std_logic;
+ signal ae_setcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal wcount_r8: std_logic;
+ signal ae_set_cmp_clr: std_logic;
+ signal ae_setcount_8: std_logic;
+ signal ae_set_cmp_set: std_logic;
+ signal ae_set_d: std_logic;
+ signal ae_set_d_c: std_logic;
+ signal scuba_vhi: std_logic;
+ signal iaf_setcount_0: std_logic;
+ signal iaf_setcount_1: std_logic;
+ signal af_set_ctr_ci: std_logic;
+ signal iaf_setcount_2: std_logic;
+ signal iaf_setcount_3: std_logic;
+ signal co0_6: std_logic;
+ signal iaf_setcount_4: std_logic;
+ signal iaf_setcount_5: std_logic;
+ signal co1_6: std_logic;
+ signal iaf_setcount_6: std_logic;
+ signal iaf_setcount_7: std_logic;
+ signal co2_6: std_logic;
+ signal iaf_setcount_8: std_logic;
+ signal iaf_setcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal af_setcount_9: std_logic;
+ signal co3_6: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_3: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal af_setcount_0: std_logic;
+ signal af_setcount_1: std_logic;
+ signal co0_7: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal af_setcount_2: std_logic;
+ signal af_setcount_3: std_logic;
+ signal co1_7: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal af_setcount_4: std_logic;
+ signal af_setcount_5: std_logic;
+ signal co2_7: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w7: std_logic;
+ signal af_setcount_6: std_logic;
+ signal af_setcount_7: std_logic;
+ signal co3_7: std_logic;
+ signal rcount_w8: std_logic;
+ signal af_set_cmp_clr: std_logic;
+ signal af_setcount_8: std_logic;
+ signal af_set_cmp_set: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x0410";
+ attribute initval of LUT4_6 : label is "0x1004";
+ attribute initval of LUT4_5 : label is "0x0140";
+ attribute initval of LUT4_4 : label is "0x4001";
+ attribute initval of LUT4_3 : label is "0x13c8";
+ attribute initval of LUT4_2 : label is "0x2004";
+ attribute initval of LUT4_1 : label is "0x4c32";
+ attribute initval of LUT4_0 : label is "0x8001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "ecp2m_link_fifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "ENABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t20: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t19: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t18: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>w_gcount_r29,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r8);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x13c8")
+ -- synopsys translate_on
+ port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29,
+ AD0=>rptr_9, DO0=>ae_set_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x2004")
+ -- synopsys translate_on
+ port map (AD3=>ae_setcount_9, AD2=>rcount_9, AD1=>w_gcount_r29,
+ AD0=>rptr_9, DO0=>ae_set_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4c32")
+ -- synopsys translate_on
+ port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29,
+ AD0=>wptr_9, DO0=>af_set_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8001")
+ -- synopsys translate_on
+ port map (AD3=>af_setcount_9, AD2=>wcount_9, AD1=>r_gcount_w29,
+ AD0=>wptr_9, DO0=>af_set_cmp_clr);
+
+ pdp_ram_0_0_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "ENABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
+ ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
+ ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
+ ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
+ ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ FF_123: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_93: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_63: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_62: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_60: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_59: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_58: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_23: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ FF_21: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>ae_setcount_0);
+
+ FF_20: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_1, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>ae_setcount_1);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_2);
+
+ FF_18: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_3, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>ae_setcount_3);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_4);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_5);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_6);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_7);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_8);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iae_setcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>ae_setcount_9);
+
+ FF_11: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ae_set_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
+
+ FF_10: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_0);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_1);
+
+ FF_8: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>af_setcount_2);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_3);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_4);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_5);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_6);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_7);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_8);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>af_setcount_9);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
+ B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
+ B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ ae_set_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>ae_set_ctr_ci, S0=>open,
+ S1=>open);
+
+ ae_set_ctr_0: CU2
+ port map (CI=>ae_set_ctr_ci, PC0=>ae_setcount_0,
+ PC1=>ae_setcount_1, CO=>co0_4, NC0=>iae_setcount_0,
+ NC1=>iae_setcount_1);
+
+ ae_set_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>ae_setcount_2, PC1=>ae_setcount_3,
+ CO=>co1_4, NC0=>iae_setcount_2, NC1=>iae_setcount_3);
+
+ ae_set_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>ae_setcount_4, PC1=>ae_setcount_5,
+ CO=>co2_4, NC0=>iae_setcount_4, NC1=>iae_setcount_5);
+
+ ae_set_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>ae_setcount_6, PC1=>ae_setcount_7,
+ CO=>co3_4, NC0=>iae_setcount_6, NC1=>iae_setcount_7);
+
+ ae_set_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>ae_setcount_8, PC1=>ae_setcount_9,
+ CO=>co4_2, NC0=>iae_setcount_8, NC1=>iae_setcount_9);
+
+ ae_set_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+ ae_set_cmp_0: AGEB2
+ port map (A0=>ae_setcount_0, A1=>ae_setcount_1, B0=>wcount_r0,
+ B1=>wcount_r1, CI=>cmp_ci_2, GE=>co0_5);
+
+ ae_set_cmp_1: AGEB2
+ port map (A0=>ae_setcount_2, A1=>ae_setcount_3, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>co0_5, GE=>co1_5);
+
+ ae_set_cmp_2: AGEB2
+ port map (A0=>ae_setcount_4, A1=>ae_setcount_5, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co1_5, GE=>co2_5);
+
+ ae_set_cmp_3: AGEB2
+ port map (A0=>ae_setcount_6, A1=>ae_setcount_7,
+ B0=>w_g2b_xor_cluster_0, B1=>wcount_r7, CI=>co2_5, GE=>co3_5);
+
+ ae_set_cmp_4: AGEB2
+ port map (A0=>ae_setcount_8, A1=>ae_set_cmp_set, B0=>wcount_r8,
+ B1=>ae_set_cmp_clr, CI=>co3_5, GE=>ae_set_d_c);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
+ S1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_set_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open,
+ S1=>open);
+
+ af_set_ctr_0: CU2
+ port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0,
+ PC1=>af_setcount_1, CO=>co0_6, NC0=>iaf_setcount_0,
+ NC1=>iaf_setcount_1);
+
+ af_set_ctr_1: CU2
+ port map (CI=>co0_6, PC0=>af_setcount_2, PC1=>af_setcount_3,
+ CO=>co1_6, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3);
+
+ af_set_ctr_2: CU2
+ port map (CI=>co1_6, PC0=>af_setcount_4, PC1=>af_setcount_5,
+ CO=>co2_6, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5);
+
+ af_set_ctr_3: CU2
+ port map (CI=>co2_6, PC0=>af_setcount_6, PC1=>af_setcount_7,
+ CO=>co3_6, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7);
+
+ af_set_ctr_4: CU2
+ port map (CI=>co3_6, PC0=>af_setcount_8, PC1=>af_setcount_9,
+ CO=>co4_3, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9);
+
+ af_set_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
+
+ af_set_cmp_0: AGEB2
+ port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_7);
+
+ af_set_cmp_1: AGEB2
+ port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co0_7, GE=>co1_7);
+
+ af_set_cmp_2: AGEB2
+ port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co1_7, GE=>co2_7);
+
+ af_set_cmp_3: AGEB2
+ port map (A0=>af_setcount_6, A1=>af_setcount_7,
+ B0=>r_g2b_xor_cluster_0, B1=>rcount_w7, CI=>co2_7, GE=>co3_7);
+
+ af_set_cmp_4: AGEB2
+ port map (A0=>af_setcount_8, A1=>af_set_cmp_set, B0=>rcount_w8,
+ B1=>af_set_cmp_clr, CI=>co3_7, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a3: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of ecp2m_link_fifo is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+
+entity etrax_interfacev2 is
+ generic (
+ RW_SYSTEM : integer range 1 to 2:=1
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_BUS : in std_logic_vector(31 downto 0);
+ ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0);
+ ETRAX_DATA_BUS_B_17 : in std_logic;--_vector(16 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
+ DATA_VALID : in std_logic;
+ ETRAX_BUS_BUSY : in std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
+ TDC_TCK : out std_logic;
+ TDC_TDI : out std_logic;
+ TDC_TMS : out std_logic;
+ TDC_TRST : out std_logic;
+ TDC_TDO : in std_logic;
+ TDC_RESET : out std_logic;
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(15 downto 0);
+ FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
+ LVL2_VALID : in std_logic
+ -- DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0)
+ );
+end etrax_interfacev2;
+
+architecture etrax_interfacev2 of etrax_interfacev2 is
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ signal etrax_trigger_pulse : std_logic;
+ signal rw_operation_finished_pulse : std_logic;
+ signal saved_rw_mode : std_logic_vector(15 downto 0);
+ signal saved_address : std_logic_vector (31 downto 0);
+ signal saved_data : std_logic_vector(31 downto 0);
+ signal saved_data_fpga : std_logic_vector(31 downto 0);
+
+ signal fpga_register_00_i : std_logic_vector(31 downto 0);
+ signal fpga_register_01_i : std_logic_vector(31 downto 0);
+ signal fpga_register_02_i : std_logic_vector(31 downto 0);
+ signal fpga_register_03_i : std_logic_vector(31 downto 0);
+ signal fpga_register_04_i : std_logic_vector(31 downto 0);
+ signal fpga_register_05_i : std_logic_vector(31 downto 0);
+ signal fpga_register_06_i : std_logic_vector(31 downto 0);
+ signal fpga_register_07_i : std_logic_vector(31 downto 0);
+ signal fpga_register_08_i : std_logic_vector(31 downto 0);
+ signal fpga_register_09_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0A_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0B_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0C_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0D_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0E_i : std_logic_vector(31 downto 0);
+ signal saved_external_data : std_logic_vector(31 downto 0);
+ signal etrax_is_ready_to_read_i : std_logic;
+ signal lvl2_not_valid_pulse : std_logic;
+ signal counter_for_pulses : std_logic_vector(2 downto 0);
+ signal internal_reset_i : std_logic := '0';
+
+ signal data_from_etrax : std_logic_vector(80 downto 0);
+ signal etrax_std_data_counter : std_logic_vector(7 downto 0):=x"00";
+ signal enable_transmition : std_logic :='1';
+ signal etrax_strobe : std_logic;
+ signal data_to_etrax : std_logic_vector(31 downto 0);
+ signal reset_counter : std_logic_vector(15 downto 0) := x"0000";
+ signal external_reset_counter : std_logic_vector(31 downto 0);
+ signal en_trigg_to_etrax : std_logic;
+ signal busy_dma_counter : std_logic_vector(3 downto 0);
+ signal busy_dma : std_logic;
+ signal etrax_busy_end_pulse : std_logic;
+ signal not_etrax_busy : std_logic;
+ signal data_valid_synch : std_logic;
+ signal send_data : std_logic;
+ signal data_bus_reg : std_logic_vector(31 downto 0);
+ constant INTERFACE_FOR_TRANSFER : integer := 2; --1 DMA, 2 no DMA
+ signal readout_lvl2_fifo_to_long :std_logic;
+ signal readout_lvl2_fifo_to_long_synch :std_logic;
+ signal readout_lvl2_fifo :std_logic;
+ signal etrax_busy_start : std_logic;
+ signal data_valid_start_pulse : std_logic;
+ signal data_valid_end_pulse : std_logic;
+ signal data_valid_not : std_logic;
+ signal etrax_busy_end : std_logic;
+ signal write_to_dma : std_logic;
+ signal write_to_dma_synch : std_logic;
+ signal word16_counter : std_logic_vector(7 downto 0);
+ signal write_to_dma_synch_synch : std_logic;
+begin
+
+
+-------------------------------------------------------------------------------
+-- transmition for reading, writing fpga registers, dsp, sdram , addon . . .
+-------------------------------------------------------------------------------
+
+ TRB_SYSTEM : if RW_SYSTEM = 1 generate
+ ETRAX_DATA_BUS_C(17) <= 'Z';
+ STROBE_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_C(17),
+ pulse => etrax_strobe);
+
+ SAVE_ETRAX_DATA : process (CLK, RESET)
+ variable etrax_data_counter : integer := 0;
+ begin
+ if rising_edge(CLK)then
+ if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
+ etrax_data_counter := 0;
+ data_from_etrax <= (others => '0');
+ ETRAX_DATA_BUS_C(16) <= 'Z';
+ enable_transmition <= '1';
+ etrax_std_data_counter <= x"00";
+ elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
+ data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_C(16);
+ etrax_data_counter := etrax_data_counter + 1;
+ ETRAX_DATA_BUS_C(16) <= 'Z';
+ enable_transmition <= '0';
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_C(16) <= data_to_etrax(0);
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_C(16) <= data_to_etrax((etrax_data_counter-81) mod 32);
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ end if;
+ end if;
+ end process SAVE_ETRAX_DATA;
+ end generate TRB_SYSTEM;
+ -- we should add one state to wait for the data from external device (valid
+ -- pulse- > one long puls on the data bus !)
+ ADDON_SYSTEM : if RW_SYSTEM = 2 generate
+ ETRAX_DATA_BUS_E(8) <= 'Z';
+ STROBE_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_E(9),--
+ pulse => etrax_strobe);
+
+ SAVE_ETRAX_DATA : process (CLK, RESET)
+ variable etrax_data_counter : integer := 0;
+ begin
+ if rising_edge(CLK)then
+ if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
+ etrax_data_counter := 0;
+ data_from_etrax <= (others => '0');
+ ETRAX_DATA_BUS_E(8) <= 'Z';
+ enable_transmition <= '1';
+ etrax_std_data_counter <= x"00";
+ elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
+ data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_E(8);
+ etrax_data_counter := etrax_data_counter + 1;
+ ETRAX_DATA_BUS_E(8) <= 'Z';
+ enable_transmition <= '0';
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_E(8) <= data_to_etrax(0);
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_E(8) <= data_to_etrax( (etrax_data_counter-81) mod 32);
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ end if;
+ end if;
+ end process SAVE_ETRAX_DATA;
+ end generate ADDON_SYSTEM;
+
+ data_to_etrax <= saved_data_fpga when saved_rw_mode(7 downto 0) = x"00" else saved_external_data;
+ RW_FINISHED_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => EXTERNAL_VALID,
+ pulse => rw_operation_finished_pulse);
+ --for reading only 1us for responce for any external device !!! - ask RADEK
+ --abut timing
+ REGISTER_ETRAX_BUS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if rw_operation_finished_pulse = '1' then
+ saved_external_data <= EXTERNAL_DATA_IN;
+ else
+ saved_external_data <= saved_external_data;
+ end if;
+ end if;
+ end process REGISTER_ETRAX_BUS;
+ EXTERNAL_ADDRESS <= saved_address;
+ EXTERNAL_MODE <= saved_rw_mode(15 downto 0);
+ EXTERNAL_DATA_OUT <= saved_data;
+ EXTERNAL_ACK <= '1' when etrax_std_data_counter = 80 else '0';
+
+ CLOCK_SAVED_DATA: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_rw_mode <= (others => '0');
+ saved_address <= (others => '0');
+ saved_data <= (others => '0');
+ else
+ saved_rw_mode <= data_from_etrax(15 downto 0);
+ saved_address <= data_from_etrax(47 downto 16);
+ saved_data <= data_from_etrax(79 downto 48);
+ end if;
+ end if;
+ end process CLOCK_SAVED_DATA;
+
+ REGISTERS: process (CLK)
+ begin
+ if rising_edge(CLK) then
+-- if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+ fpga_register_01_i <= FPGA_REGISTER_01;
+ fpga_register_02_i <= FPGA_REGISTER_02;
+ fpga_register_03_i <= FPGA_REGISTER_03;
+ fpga_register_04_i <= FPGA_REGISTER_04;
+ fpga_register_05_i <= FPGA_REGISTER_05;
+ FPGA_REGISTER_06 <= fpga_register_06_i; --this used for TDCjtag enable(0)
+ FPGA_REGISTER_07 <= fpga_register_07_i;
+ fpga_register_08_i <= FPGA_REGISTER_08;
+ fpga_register_09_i <= FPGA_REGISTER_09;
+ fpga_register_0A_i <= FPGA_REGISTER_0A;
+ fpga_register_0B_i <= FPGA_REGISTER_0B;
+ fpga_register_0c_i <= FPGA_REGISTER_0C;
+ fpga_register_0d_i <= FPGA_REGISTER_0D;
+ FPGA_REGISTER_0E <= fpga_register_0e_i;
+ end if;
+ end process REGISTERS;
+
+ DATA_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then--(ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
+ fpga_register_06_i <= x"00000000";
+ fpga_register_07_i <= x"00000000";
+ fpga_register_0e_i <= x"00000000";
+ else
+ case saved_rw_mode(7 downto 0) is
+ when "00000000" =>
+ if saved_rw_mode(15) = '1' then
+ case saved_address(31 downto 0) is
+ when x"00000000" => saved_data_fpga <= fpga_register_00_i;
+ when x"00000001" => saved_data_fpga <= fpga_register_01_i;
+ when x"00000002" => saved_data_fpga <= fpga_register_02_i;
+ when x"00000003" => saved_data_fpga <= fpga_register_03_i;
+ when x"00000004" => saved_data_fpga <= fpga_register_04_i;
+ when x"00000005" => saved_data_fpga <= fpga_register_05_i;
+ when x"00000006" => saved_data_fpga <= fpga_register_06_i;
+ when x"00000007" => saved_data_fpga <= fpga_register_07_i;
+ when x"00000008" => saved_data_fpga <= fpga_register_08_i;
+ when x"00000009" => saved_data_fpga <= fpga_register_09_i;
+ when x"0000000A" => saved_data_fpga <= fpga_register_0A_i;
+ when x"0000000B" => saved_data_fpga <= fpga_register_0B_i;
+ when x"0000000C" => saved_data_fpga <= fpga_register_0C_i;
+ when x"0000000D" => saved_data_fpga <= fpga_register_0D_i;
+ when x"0000000E" => saved_data_fpga <= fpga_register_0E_i;
+ when others => saved_data_fpga <= x"deadface";
+ end case;
+ elsif saved_rw_mode(15) = '0' and etrax_std_data_counter = 80 then
+ case saved_address(31 downto 0) is
+ when x"00000006" => fpga_register_06_i <= saved_data;
+ when x"00000007" => fpga_register_07_i <= saved_data;
+ when x"0000000e" => fpga_register_0e_i <= saved_data;
+ when others => null;
+ end case;
+ end if;
+ when "00000001" => --DSP write read
+ saved_data_fpga <= saved_external_data;
+ when x"02" => --sdram
+ saved_data_fpga <= saved_external_data;
+ when x"03" => --ADDON board write read
+ saved_data_fpga <= saved_external_data;
+ when others =>
+ saved_data_fpga <= x"deadface";
+ end case;
+ end if;
+ end if;
+ end process DATA_SOURCE_SELECT;
+
+-------------------------------------------------------------------------------
+-- data transmitio fpga -> etrax
+-------------------------------------------------------------------------------
+--DMA
+ DMA_INTERFACE: if INTERFACE_FOR_TRANSFER=1 generate
+
+ REG_DATA_TO_ETRAXa:process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ data_bus_reg <= (others => '0');
+ write_to_dma_synch <= '0';
+ write_to_dma_synch_synch <= '0';
+ else
+ data_bus_reg <= DATA_BUS;
+ write_to_dma_synch <= readout_lvl2_fifo;--write_to_dma;
+ write_to_dma_synch_synch <= write_to_dma_synch;
+ end if;
+ end if;
+ end process REG_DATA_TO_ETRAXa;
+ ETRAX_DATA_BUS_B(7 downto 0) <= data_bus_reg(31 downto 24);
+-- ETRAX_DATA_BUS_B(6 downto 0) <= data_bus_reg(30 downto 24); --!!!test
+ ETRAX_DATA_BUS_B(15 downto 8) <= data_bus_reg(23 downto 16);
+ ETRAX_DATA_BUS_C(15 downto 8) <= data_bus_reg(15 downto 8);
+ ETRAX_DATA_BUS_C(7 downto 4) <= data_bus_reg(7 downto 4);
+
+
+-- ETRAX_DATA_BUS_B(7) <= ETRAX_DATA_BUS_B_17; --for test
+
+ TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1';
+ TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1';
+ TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1';
+ ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else data_bus_reg(0);
+ ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(1);
+ ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(2);
+ ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else data_bus_reg(3);
+
+ START_READOUT : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => DATA_VALID,
+ pulse => data_valid_start_pulse);
+ data_valid_not <= not DATA_VALID;
+
+ END_READOUT : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => data_valid_not,
+ pulse => data_valid_end_pulse);
+
+ ETRAX_BUSY_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_B_17,
+ pulse => etrax_busy_start);
+
+ not_etrax_busy <= not ETRAX_DATA_BUS_B_17;
+
+ ETRAX_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_etrax_busy,
+ pulse => etrax_busy_end);
+
+ COUNTER_FOR_READOUT: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ word16_counter <= x"FF";
+ elsif (data_valid_start_pulse = '1') or (etrax_busy_end = '1' and DATA_VALID = '1') then
+ word16_counter <= x"00";
+ elsif word16_counter < x"1e" then
+ word16_counter <= word16_counter + 1;
+ else
+ word16_counter <= word16_counter;
+ end if;
+ end if;
+ end process COUNTER_FOR_READOUT;
+
+ READOUT_LVL2_FIFO_PROC: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or data_valid_end_pulse = '1' or word16_counter = x"1e" then
+ readout_lvl2_fifo <= '0';
+ elsif word16_counter < x"1e" then
+ readout_lvl2_fifo <= word16_counter(0);
+ end if;
+ end if;
+ end process READOUT_LVL2_FIFO_PROC;
+
+ WRITE_TO_ETRAX_DMA: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or word16_counter = x"1e" then
+ write_to_dma <= '0';
+ elsif word16_counter = x"00" then
+ write_to_dma <= '1';
+ end if;
+ end if;
+ end process WRITE_TO_ETRAX_DMA;
+
+ etrax_is_ready_to_read_i <= (data_valid_start_pulse or readout_lvl2_fifo) and DATA_VALID;
+ ETRAX_IS_READY_TO_READ <= readout_lvl2_fifo;
+ ETRAX_DATA_BUS_B(16) <= write_to_dma_synch_synch;--(not CLK) and (write_to_dma_synch_synch);
+
+ end generate DMA_INTERFACE;
+
+
+-- NO DMA
+ WITHOUT_DMA_ETRAX_INTERFACE: if INTERFACE_FOR_TRANSFER = 2 generate
+
+ ETRAX_READY_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_B_17,
+ pulse => etrax_is_ready_to_read_i);
+
+ MAKE_PULSES: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_for_pulses <= "000";
+ else
+ counter_for_pulses <= counter_for_pulses + 1;
+ end if;
+ end if;
+ end process make_pulses;
+
+ LVL2_NOT_VALID_READY_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => counter_for_pulses(2),
+ pulse => lvl2_not_valid_pulse);
+
+ ETRAX_IS_READY_TO_READ <= DATA_VALID and ((etrax_is_ready_to_read_i and (not LVL2_VALID)) or (lvl2_not_valid_pulse and LVL2_VALID));
+
+ TDC_TMS <= ETRAX_DATA_BUS_C(1) when fpga_register_06_i(0) = '1' else '1';
+ TDC_TCK <= ETRAX_DATA_BUS_C(2) when fpga_register_06_i(0) = '1' else '1';
+ TDC_TDI <= ETRAX_DATA_BUS_C(3) when fpga_register_06_i(0) = '1' else '1';
+ ETRAX_DATA_BUS_C(0) <= TDC_TDO when fpga_register_06_i(0) = '1' else DATA_BUS(16);
+ ETRAX_DATA_BUS_C(1) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(17);
+ ETRAX_DATA_BUS_C(2) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(18);
+ ETRAX_DATA_BUS_C(3) <= 'Z' when fpga_register_06_i(0) = '1' else DATA_BUS(19);
+ ETRAX_DATA_BUS_C(15 downto 4) <= DATA_BUS(31 downto 20);
+ ETRAX_DATA_BUS_B(15 downto 0) <= DATA_BUS(15 downto 0);
+ ETRAX_DATA_BUS_B(16) <= DATA_VALID and (not LVL2_VALID);
+
+
+ REG_DATA_TO_ETRAX: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ data_bus_reg <= (others => '0');
+ else
+ data_bus_reg <= DATA_BUS;
+ end if;
+ end if;
+ end process REG_DATA_TO_ETRAX;
+end generate WITHOUT_DMA_ETRAX_INTERFACE;
+
+end etrax_interfacev2;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_arith.all;
+use IEEE.STD_LOGIC_unsigned.all;
+
+
+entity f_divider is
+
+ generic(
+ cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. --
+ );
+
+ port (
+ clk : in std_logic;
+ ena_cnt : in std_logic;
+ f_div : out std_logic
+ );
+
+end f_divider;
+
+
+
+architecture arch_f_divider of f_divider is
+
+ function How_many_Bits (int : integer) return integer is
+ variable i, tmp : integer;
+ begin
+ tmp := int;
+ i := 0;
+ while tmp > 0 loop
+ tmp := tmp / 2;
+ i := i + 1;
+ end loop;
+ return i;
+ end How_many_bits;
+
+
+ --+
+ --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? |
+ --+
+ constant c_counter_width : integer := How_many_Bits(cnt - 2);
+
+ --+ ---------------------------------------------------------------------------------------------+
+ --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" |
+ --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne |
+ --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. |
+ --+ ---------------------------------------------------------------------------------------------+
+ signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1);
+
+ --+ ---------------------------------------------------------------------------------------------+
+ --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem |
+ --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. |
+ --+ ---------------------------------------------------------------------------------------------+
+ constant c_ld_value : integer := cnt - 2;
+
+begin
+ p_f_divider : process (clk)
+ begin
+ if clk'event and clk = '1' then
+ if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen --
+ s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length);
+ elsif ena_cnt = '1' then
+ if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter --
+ s_counter <= s_counter - 1; -- subtrahieren. --
+ end if;
+ end if;
+ end if;
+ end process p_f_divider;
+
+ f_div <= s_counter(s_counter'high);
+
+end arch_f_divider;
+
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+--library synplify;
+--use synplify.attributes.all;
+
+
+entity edge_to_pulse is
+
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+
+end edge_to_pulse;
+
+architecture arch_edge_to_pulse of edge_to_pulse is
+ signal signal_sync : std_logic;
+ signal old_sync : std_logic;
+ type state is (idle, high, wait_for_low); -- state
+ signal current_state, next_state : state;
+
+begin -- arch_edge_to_pulse
+
+ fsm : process (clock)
+ begin -- process fsm
+ if rising_edge(clock) then -- rising clock edge
+ if en_clk = '1' then
+ current_state <= next_state;
+ signal_sync <= signal_in;
+ end if;
+ end if;
+ end process fsm;
+
+
+ fsm_comb : process (current_state, signal_sync)
+ begin -- process fsm_comb
+ case current_state is
+ when idle =>
+ pulse <= '0';
+ if signal_sync = '1' then
+ next_state <= high;
+ else
+ next_state <= idle;
+ end if;
+ when high =>
+ pulse <= '1';
+ next_state <= wait_for_low;
+-- when wait_for_low_1 =>
+-- pulse <= '1';
+-- next_state <= wait_for_low;
+ when wait_for_low =>
+ pulse <= '0';
+ if signal_sync = '0' then
+ next_state <= idle;
+ else
+ next_state <= wait_for_low;
+ end if;
+ when others =>
+ pulse <= '0';
+ next_state <= idle;
+ end case;
+ end process fsm_comb;
+
+
+end arch_edge_to_pulse;
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package support is
+
+ component f_divider
+ generic (
+ cnt : integer);
+ port (
+ clk : in std_logic;
+ ena_cnt : in std_logic;
+ f_div : out std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+
+end support;
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+entity flexi_PCS_channel_synch is
+
+ port (
+ SYSTEM_CLK : in std_logic;
+ TX_CLK : in std_logic;
+ RX_CLK : in std_logic;
+ RESET : in std_logic;
+ RXD : in std_logic_vector(15 downto 0);
+ RXD_SYNCH : out std_logic_vector(15 downto 0);
+ RX_K : in std_logic_vector(1 downto 0);
+ RX_RST : out std_logic;
+ CV : in std_logic_vector(1 downto 0);
+ TXD : in std_logic_vector(15 downto 0);
+ TXD_SYNCH : out std_logic_vector(15 downto 0);
+ TX_K : out std_logic_vector(1 downto 0);
+ DATA_VALID_IN : in std_logic;
+ DATA_VALID_OUT : out std_logic;
+ FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(2 downto 0);
+ MED_READ_IN : in std_logic
+ );
+
+end flexi_PCS_channel_synch;
+architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is
+ component flexi_PCS_fifo_EBR
+ port (
+ Data : in std_logic_vector(17 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component ecp2m_link_fifo
+ port (
+ Data : in std_logic_vector(17 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component simpleupcounter_32bit
+ port (
+ QOUT : out std_logic_vector(31 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component simpleupcounter_16bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component simpleupcounter_8bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component edge_to_pulse
+ port (
+ CLOCK : in std_logic;
+ EN_CLK : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE : out std_logic);
+ end component;
+ type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, NORMAL_OPERATION_1, NORMAL_OPERATION_2);
+ signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE;
+ signal fsm_debug_register : std_logic_vector(2 downto 0);
+ signal resync_counter_up :std_logic;
+ signal resync_counter_clr :std_logic;
+ signal resync_counter : std_logic_vector(31 downto 0);
+ signal cv_i : std_logic_vector(1 downto 0);
+ signal cv_or : std_logic;
+ signal cv_counter : std_logic_vector(15 downto 0);
+ signal rx_rst_i : std_logic;
+ signal rxd_synch_i : std_logic_vector(15 downto 0);
+ signal rxd_synch_synch_i : std_logic_vector(15 downto 0);
+ signal rx_k_synch_i : std_logic_vector(1 downto 0);
+ signal rx_k_synch_synch_i : std_logic_vector(1 downto 0);
+ signal fifo_data_in : std_logic_vector(17 downto 0);
+ signal fifo_data_out : std_logic_vector(17 downto 0);
+ signal fifo_wr_en : std_logic;
+ signal fifo_rd_en : std_logic;
+ signal fifo_rst : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_almost_full : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_almost_empty : std_logic;
+ signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal start_counter_1 : std_logic_vector(31 downto 0);
+ signal start_counter_2 : std_logic_vector(31 downto 0);
+ signal fifo_rd_pulse : std_logic;
+ signal fifo_rd_cnt : std_logic_vector(15 downto 0);
+ signal fifo_wr_cnt : std_logic_vector(15 downto 0);
+ signal not_fifo_empty : std_logic;
+ signal fifo_rd_en_dv : std_logic;
+ -----------------------------------------------------------------------------
+ -- fifo to optical link
+ -----------------------------------------------------------------------------
+ signal data_valid_out_i : std_logic;
+ signal fifo_opt_not_empty : std_logic;
+ signal fifo_opt_empty : std_logic;
+ signal fifo_opt_empty_synch : std_logic;
+ signal data_opt_in : std_logic_vector(17 downto 0);
+ signal txd_fifo_out : std_logic_vector(17 downto 0);
+ signal fifo_opt_full : std_logic;
+ signal fifo_opt_almost_empty : std_logic;
+ signal fifo_opt_almost_full : std_logic;
+ signal not_clk : std_logic;
+ signal txd_synch_i : std_logic_vector(15 downto 0);
+ signal tx_k_i : std_logic;
+ signal fifo_opt_empty_synch_synch : std_logic;
+ signal fifo_rd_en_hub : std_logic;
+ constant SYSTEM : Integer := 2;
+begin
+ SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT)
+ begin
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ MED_ERROR_OUT <= ERROR_NC;
+ elsif SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2 then
+ MED_ERROR_OUT <= ERROR_OK;
+ elsif SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2 then
+ MED_ERROR_OUT <= ERROR_WAIT;
+ else
+ MED_ERROR_OUT <= ERROR_NC;
+ end if;
+ end if;
+ end process SEND_ERROR;
+ PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en)
+ begin
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ packet_number <= "011";
+ elsif fifo_rd_en = '1' then
+ if packet_number = c_max_word_number then
+ packet_number <= "000";
+ else
+ packet_number <= packet_number + 1;
+ end if;
+ end if;
+ end if;
+ end process PACKET_NUM;
+ MED_PACKET_NUM_OUT <= packet_number;
+ LINK_STATUS : process (SYSTEM_CLK,RESET)
+ begin
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ RX_RST <= '0';
+ FLEXI_PCS_STATUS(15 downto 0) <= (others => '0');
+ else
+ RX_RST <= rx_rst_i;
+ FLEXI_PCS_STATUS(2 downto 0) <= fsm_debug_register;
+ FLEXI_PCS_STATUS(7 downto 3) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full & DATA_VALID_IN;--fifo_almost_full &
+ --'0';
+ FLEXI_PCS_STATUS(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
+-- FLEXI_PCS_STATUS(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0);
+ end if;
+ end if;
+ end process LINK_STATUS;
+ -----------------------------------------------------------------------------
+ -- data from hub to link
+ -----------------------------------------------------------------------------
+ data_opt_in <= "00" & TXD;
+ SYSTEM_SCM_MEMa: if SYSTEM=1 generate
+ CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR
+ port map (
+ Data => data_opt_in,
+ WrClock => SYSTEM_CLK,
+ RdClock => TX_CLK,
+ WrEn => DATA_VALID_IN,
+ RdEn => fifo_opt_not_empty,
+ Reset => fifo_rst,
+ RPReset => fifo_rst,
+ Q => txd_fifo_out,
+ Empty => fifo_opt_empty,
+ Full => fifo_opt_full,
+ AlmostEmpty => fifo_opt_almost_empty,
+ AlmostFull => fifo_opt_almost_full
+ );
+ end generate SYSTEM_SCM_MEMa;
+
+ SYSTEM_ECP2_MEMa: if SYSTEM=2 generate
+ CHANNEL_FIFO_TO_OPT: ecp2m_link_fifo
+ port map (
+ Data => data_opt_in,
+ WrClock => SYSTEM_CLK,
+ RdClock => TX_CLK,
+ WrEn => DATA_VALID_IN,
+ RdEn => fifo_opt_not_empty,
+ Reset => fifo_rst,
+ RPReset => fifo_rst,
+ Q => txd_fifo_out,
+ Empty => fifo_opt_empty,
+ Full => fifo_opt_full,
+ AlmostEmpty => fifo_opt_almost_empty,
+ AlmostFull => fifo_opt_almost_full
+ );
+ end generate SYSTEM_ECP2_MEMa;
+
+
+ DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
+ begin
+ if rising_edge(TX_CLK) then --falling ???
+ if RESET = '1' then
+ tx_k_i <= '0';
+ txd_synch_i <= (others => '0');
+ fifo_opt_empty_synch <= fifo_opt_empty;
+ fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
+ fifo_opt_not_empty <= not fifo_opt_empty;
+ elsif fifo_opt_empty_synch = '0' and fifo_opt_empty_synch_synch ='0' then
+ tx_k_i <= '0';
+ txd_synch_i <= txd_fifo_out(15 downto 0);
+ fifo_opt_empty_synch <= fifo_opt_empty;
+ fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
+ fifo_opt_not_empty <= not fifo_opt_empty;
+ else
+ tx_k_i <= '1';
+ txd_synch_i <= x"c5bc";
+ fifo_opt_empty_synch <= fifo_opt_empty;
+ fifo_opt_empty_synch_synch <= fifo_opt_empty_synch;
+ fifo_opt_not_empty <= not fifo_opt_empty;
+ end if;
+ end if;
+ end process DATA_SEND_TO_LINK;
+ SYNCH_DATA: process (TX_CLK)
+ begin
+ if rising_edge(TX_CLK) then
+ TXD_SYNCH <= txd_synch_i;
+ TX_K(0) <= tx_k_i;
+ TX_K(1) <= '0';
+ end if;
+ end process SYNCH_DATA;
+-- TX_FORCE_DISP(1) <= '0';
+ -----------------------------------------------------------------------------
+ -- from link to hub
+ -----------------------------------------------------------------------------
+ SYSTEM_SCM_MEMb: if SYSTEM=1 generate
+ CHANNEL_FIFO_TO_FPGA: flexi_PCS_fifo_EBR
+ port map (
+ Data => fifo_data_in,
+ WrClock => RX_CLK,
+ RdClock => SYSTEM_CLK,
+ WrEn => fifo_wr_en,
+ RdEn => fifo_rd_en,
+ Reset => fifo_rst,
+ RPReset => fifo_rst,
+ Q => fifo_data_out,
+ Empty => fifo_empty,
+ Full => fifo_full,
+ AlmostEmpty => fifo_almost_empty,
+ AlmostFull => fifo_almost_full
+ );
+ end generate SYSTEM_SCM_MEMb;
+
+ SYSTEM_ECP2_MEMb: if SYSTEM=2 generate
+ CHANNEL_FIFO_TO_FPGA: ecp2m_link_fifo
+ port map (
+ Data => fifo_data_in,
+ WrClock => RX_CLK,
+ RdClock => SYSTEM_CLK,
+ WrEn => fifo_wr_en,
+ RdEn => fifo_rd_en,
+ Reset => fifo_rst,
+ RPReset => fifo_rst,
+ Q => fifo_data_out,
+ Empty => fifo_empty,
+ Full => fifo_full,
+ AlmostEmpty => fifo_almost_empty,
+ AlmostFull => fifo_almost_full
+ );
+ end generate SYSTEM_ECP2_MEMb;
+
+ not_fifo_empty <= not fifo_empty;
+ RD_FIFO_PULSE: edge_to_pulse
+ port map (
+ clock => SYSTEM_CLK,
+ en_clk => '1',
+ signal_in => not_fifo_empty,
+ pulse => fifo_rd_pulse);
+ READING_THE_FIFO: process (SYSTEM_CLK, RESET, fifo_rd_pulse,MED_READ_IN,fifo_empty,data_valid_out_i)
+ begin
+ if rising_edge(SYSTEM_CLK) then
+ if RESET = '1' then
+ data_valid_out_i <= '0';
+ fifo_rd_en_hub <= '0';
+ elsif fifo_rd_pulse = '1' then
+ data_valid_out_i <= '1';
+ fifo_rd_en_hub <= MED_READ_IN;
+ elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then
+ data_valid_out_i <= '0';
+ fifo_rd_en_hub <= '0';
+ elsif data_valid_out_i = '1' and fifo_empty = '0' then
+ data_valid_out_i <= '1';
+ fifo_rd_en_hub <= MED_READ_IN;
+ end if;
+ end if;
+ end process READING_THE_FIFO;
+ DATA_VALID_OUT <= data_valid_out_i;
+ fifo_rd_en <= (fifo_rd_en_hub and (not fifo_empty)) or fifo_rd_pulse;
+ RXD_SYNCH <= fifo_data_out(15 downto 0);
+-- DATA_VALID_OUT <= fifo_data_out(16) and (not fifo_empty);
+ VALID_DATA_SEND_TO_API: process (RX_CLK, RESET)
+ begin
+ if rising_edge(RX_CLK) then
+ if RESET = '1' then
+ rxd_synch_i <= (others => '0');
+ rxd_synch_synch_i <= rxd_synch_i;
+ rx_k_synch_i <= "00";
+ rx_k_synch_synch_i <= rx_k_synch_i;
+ else-- RX_K(0) = '1' then
+ rxd_synch_i <= RXD;
+ rxd_synch_synch_i <= rxd_synch_i;
+ rx_k_synch_i <= RX_K;
+ rx_k_synch_synch_i <= rx_k_synch_i;
+ end if;
+ end if;
+ end process VALID_DATA_SEND_TO_API;
+ SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET, SYNCH_CURRENT)
+ begin
+ if rising_edge(RX_CLK) then
+ if RESET = '1' then
+ fifo_data_in <= (others => '0');
+ elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then
+ fifo_data_in <= '0' & (not RX_K(0)) & RXD;
+ elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then
+ fifo_data_in <= '0' & (not RX_K(1)) & rxd_synch_i(7 downto 0) & RXD(15 downto 8);
+ else
+ fifo_data_in <= (others => '0');
+ end if;
+ end if;
+ end process SHIFT_OR_NOT_DATA_IN;
+
+-- SYNCH_CLOCK : process (RX_CLK, RESET)
+ SYNCH_CLOCK : process (SYSTEM_CLK, RESET)
+ begin
+ if rising_edge (SYSTEM_CLK) then
+ if RESET = '1' then
+ SYNCH_CURRENT <= IDLE; --no_sim--
+--sim-- SYNCH_CURRENT <= NORMAL_OPERATION_2;
+ cv_i <= (others => '0');
+ else
+ SYNCH_CURRENT <= SYNCH_NEXT;
+ cv_i <= CV;
+ end if;
+ end if;
+ end process SYNCH_CLOCK;
+ SYNCH_FSM : process( SYNCH_CURRENT, rxd_synch_i, resync_counter, cv_i,RX_K, MED_READ_IN ,fifo_rd_pulse, fifo_rd_en_hub,rx_k_synch_i)
+ begin
+ case (SYNCH_CURRENT) is
+ when IDLE =>
+ fifo_rst <= '1';
+ fifo_wr_en <= '0';
+ fsm_debug_register(2 downto 0) <= "001";
+ rx_rst_i <= '0';
+ resync_counter_up <= '0';
+ resync_counter_clr <= '1';
+-- if rxd_synch_i = x"bc50" then
+-- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;--WAIT_1;
+ --els
+ if rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc" then
+ SYNCH_NEXT <= WAIT_2;--NORMAL_OPERATION_2; --WAIT_2;
+ else
+ SYNCH_NEXT <= RESYNC1;
+ end if;
+ when RESYNC1 =>
+ fifo_rst <= '0';
+ fifo_wr_en <= '0';
+ fsm_debug_register(2 downto 0) <= "010";
+ rx_rst_i <= '1';
+ resync_counter_up <= '1';
+ resync_counter_clr <= '0';
+ if resync_counter(8) = '1' then
+ SYNCH_NEXT <= RESYNC2;
+ else
+ SYNCH_NEXT <= RESYNC1;
+ end if;
+ when RESYNC2 =>
+ fifo_rst <= '0';
+ fifo_wr_en <= '0';
+ fsm_debug_register(2 downto 0) <= "010";
+ rx_rst_i <= '0';
+ resync_counter_up <= '1';
+ resync_counter_clr <= '0';
+ if resync_counter(16) = '1' then --at least 400us
+ SYNCH_NEXT <= RESYNC3;
+ else
+ SYNCH_NEXT <= RESYNC2;
+ end if;
+
+ when RESYNC3 =>
+ fifo_rst <= '0';
+ fifo_wr_en <= '0';
+ fsm_debug_register(2 downto 0) <= "010";
+ rx_rst_i <= '0';
+ resync_counter_up <= '0';
+ resync_counter_clr <= '1';
+-- if rxd_synch_i = x"bc50" and rx_k_synch_i(1) = '1' then
+-- SYNCH_NEXT <= WAIT_1;--NORMAL_OPERATION_1;
+ --els
+ if (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then
+ SYNCH_NEXT <= WAIT_2;--no_sim--
+--sim-- SYNCH_NEXT <= NORMAL_OPERATION_2;
+ else
+ SYNCH_NEXT <= IDLE;
+ end if;
+ when WAIT_1 =>
+ fifo_rst <= '0';
+ rx_rst_i <= '0';
+ fifo_wr_en <= '0';
+ fsm_debug_register(2 downto 0) <= "011";
+ resync_counter_up <= '1';
+ resync_counter_clr <= '0';
+ if resync_counter(27) = '1' and (rxd_synch_i = x"bc50" or rxd_synch_i = x"bcc5") and rx_k_synch_i(1) = '1' then
+ SYNCH_NEXT <= NORMAL_OPERATION_1;
+ elsif resync_counter(26) = '1' and (rxd_synch_i /= x"bc50" or rx_k_synch_i(1) = '0') then
+ SYNCH_NEXT <= RESYNC1;
+ else
+ SYNCH_NEXT <= WAIT_1;
+ end if;
+ when WAIT_2 =>
+ fifo_rst <= '0';
+ fifo_wr_en <= '0';
+ rx_rst_i <= '0';
+ fsm_debug_register(2 downto 0) <= "011";
+ resync_counter_up <= '1';
+ resync_counter_clr <= '0';
+ if resync_counter(27) = '1' and (rxd_synch_i = x"50bc" or rxd_synch_i = x"c5bc") and rx_k_synch_i(0) = '1' then
+ SYNCH_NEXT <= NORMAL_OPERATION_2;
+ elsif resync_counter(26) = '1' and (rxd_synch_i(7 downto 0) /= x"bc" or rx_k_synch_i(0) = '0') then
+ SYNCH_NEXT <= RESYNC1;
+ else
+ SYNCH_NEXT <= WAIT_2;
+ end if;
+ when NORMAL_OPERATION_1 =>
+ fifo_rst <= '0';
+ fifo_wr_en <= not rx_k_synch_i(1);
+ fsm_debug_register(2 downto 0) <= "110";
+ rx_rst_i <= '0';
+ resync_counter_up <= '0';
+ resync_counter_clr <= '0';
+ if cv_i(0) = '1' or cv_i(1) = '1' then
+ SYNCH_NEXT <= IDLE;
+ else
+ SYNCH_NEXT <= NORMAL_OPERATION_1;
+ end if;
+ when NORMAL_OPERATION_2 =>
+ fifo_rst <='0';--no_sim--
+--sim-- fifo_rst <=RESET;
+ fifo_wr_en <= not rx_k_synch_i(0);
+ fsm_debug_register(2 downto 0) <= "111";
+ rx_rst_i <= '0';
+ resync_counter_up <= '0';
+ resync_counter_clr <= '0';
+ if cv_i(0) = '1' or cv_i(1) = '1' then
+ SYNCH_NEXT <= IDLE;
+ else
+ SYNCH_NEXT <= NORMAL_OPERATION_2;
+ end if;
+ when others =>
+ fifo_rst <= '0';
+ fifo_wr_en <= '0';
+ resync_counter_up <= '0';
+ resync_counter_clr <= '0';
+ fsm_debug_register(2 downto 0) <= "000";
+ rx_rst_i <= '0';
+ SYNCH_NEXT <= IDLE;
+ end case;
+ end process SYNCH_FSM;
+
+ RESYNC_COUNTER_INST : simpleupcounter_32bit
+ port map (
+ QOUT => resync_counter,
+ UP => resync_counter_up,
+ CLK => SYSTEM_CLK,
+ CLR => resync_counter_clr);
+ cv_or <= cv_i(0) or cv_i(1);
+ CV_COUNTER_INST: simpleupcounter_16bit
+ port map (
+ QOUT => cv_counter,
+ UP => cv_or,
+ CLK => RX_CLK,
+ CLR => RESET);
+ WR_COUNTER_INST: simpleupcounter_16bit
+ port map (
+ QOUT => fifo_wr_cnt,
+ UP => fifo_wr_en,
+ CLK => SYSTEM_CLK,
+ CLR => RESET);
+ fifo_rd_en_dv <= fifo_rd_en and fifo_data_out(16) and fifo_empty;
+ RD_COUNTER_INST: simpleupcounter_16bit
+ port map (
+ QOUT => fifo_rd_cnt,
+ UP => DATA_VALID_IN,--fifo_rd_en_dv,--fifo_rd_en,
+ CLK => SYSTEM_CLK,
+ CLR => RESET);
+end flexi_PCS_channel_synch;
+--reciving idle for 1ms and start e11o until recive e11o and idle
+--write to fifo when rx_k is 1 ?
+-- wait for reset
+-- wait for pll locked
+-- send idles
+-- wait 650ms (counter(27) = 1)
+-- enable rx
+-- wait 650ms (counter(27) = 1)
+-- enable tx
+-- ready
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module Version: 4.2
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n flexi_PCS_fifo_EBR -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e
+
+-- Tue Nov 27 10:58:36 2007
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity flexi_PCS_fifo_EBR is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(17 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end flexi_PCS_fifo_EBR;
+
+architecture Structure of flexi_PCS_fifo_EBR is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111000001";
+ attribute FULLPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111111100001";
+ attribute AFPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101000001";
+ attribute AFPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b011111101100001";
+ attribute AEPOINTER1 of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of flexi_PCS_fifo_EBR_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of flexi_PCS_fifo_EBR_0_0 : label is "ASYNC";
+ attribute REGMODE of flexi_PCS_fifo_EBR_0_0 : label is "NOREG";
+ attribute CSDECODE_R of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
+ attribute CSDECODE_W of flexi_PCS_fifo_EBR_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of flexi_PCS_fifo_EBR_0_0 : label is "36";
+ attribute DATA_WIDTH_W of flexi_PCS_fifo_EBR_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ flexi_PCS_fifo_EBR_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
+ AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi,
+ WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17), EF=>Empty_int,
+ AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of flexi_PCS_fifo_EBR is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+use work.trb_net_std.all;
+
+entity flexi_PCS_synch is
+ generic (
+ HOW_MANY_CHANNELS : positive);
+ port (
+ SYSTEM_CLK : in std_logic;
+ CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
+ RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ RESET : in std_logic;
+ RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
+ MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
+ );
+end flexi_PCS_synch;
+architecture flexi_PCS_synch of flexi_PCS_synch is
+ component flexi_PCS_channel_synch
+ port (
+ SYSTEM_CLK : in std_logic;
+ TX_CLK : in std_logic;
+ RX_CLK : in std_logic;
+ RESET : in std_logic;
+ RXD : in std_logic_vector(15 downto 0);
+ RXD_SYNCH : out std_logic_vector(15 downto 0);
+ RX_K : in std_logic_vector(1 downto 0);
+ RX_RST : out std_logic;
+ CV : in std_logic_vector(1 downto 0);
+ TXD : in std_logic_vector(15 downto 0);
+ TXD_SYNCH : out std_logic_vector(15 downto 0);
+ TX_K : out std_logic_vector(1 downto 0);
+ DATA_VALID_IN : in std_logic;
+ DATA_VALID_OUT : out std_logic;
+ FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(2 downto 0);
+ MED_READ_IN : in std_logic
+ );
+ end component;
+begin
+ CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate
+ begin
+ MED_READ_OUT <= (others => '1');
+
+ SYNCH :flexi_PCS_channel_synch
+ port map (
+ SYSTEM_CLK => SYSTEM_CLK,
+ TX_CLK => CLK(bit_index/4), --4 different channles clk
+ RX_CLK => RX_CLK(bit_index),
+ RESET => RESET,
+ RXD => RXD((bit_index*16+15) downto bit_index*16),
+ RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16),
+ RX_K => RX_K(bit_index*2+1 downto bit_index*2),
+ RX_RST => RX_RST(bit_index),
+ CV => CV((bit_index*2+1) downto bit_index*2),
+ TXD => MED_DATA_IN((bit_index*16+15) downto bit_index*16),
+ TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16),
+ TX_K => TX_K(bit_index*2+1 downto bit_index*2),
+ DATA_VALID_IN => MED_DATAREADY_IN(bit_index),
+ DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index),
+ FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16),
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(((bit_index+1)*c_NUM_WIDTH-1) downto bit_index*c_NUM_WIDTH),
+ MED_ERROR_OUT => MED_ERROR_OUT((bit_index*3+2) downto bit_index*3),
+ MED_READ_IN => MED_READ_IN(bit_index)
+ );
+ end generate;
+end flexi_PCS_synch;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+use work.version.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+-- library sc;
+-- use sc.components.all;
+entity hub is
+ generic (
+ HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 16
+ );
+ port (
+ LVDS_CLK_200P : in std_logic;
+-- LVDS_CLK_200N : in std_logic;
+-- SERDES_200N : in std_logic;
+-- SERDES_200P : in std_logic;
+-- ADO_LV : in std_logic_vector(61 downto 0);
+ --addon connector
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ --diode
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ LOK : out std_logic_vector(16 downto 1);
+ RT : out std_logic_vector(16 downto 1);
+ TX_DIS : out std_logic_vector(16 downto 1);
+ IPLL : out std_logic;
+ OPLL : out std_logic;
+ --data to/from optical tranceivers
+ SFP_INP_N : in std_logic_vector(15 downto 0);
+ SFP_INP_P : in std_logic_vector(15 downto 0);
+ SFP_OUT_N : out std_logic_vector(15 downto 0);
+ SFP_OUT_P : out std_logic_vector(15 downto 0);
+ --tempsens
+ FS_PE_11 : inout std_logic;
+ --etrax_interface
+ FS_PE : inout std_logic_vector(9 downto 8)--sim-- ;
+--sim-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+--sim-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+--sim-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+--sim-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
+ );
+end hub;
+architecture hub of hub is
+ component trb_hub_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ STROBE : in std_logic;
+ INTERNAL_DATA_IN : in std_logic_vector(7 downto 0);
+ INTERNAL_DATA_OUT : out std_logic_vector(7 downto 0);
+ INTERNAL_ADDRESS : in std_logic_vector(15 downto 0);
+ INTERNAL_MODE : in std_logic;
+ VALID_DATA_SENT : out std_logic;
+ hub_register_00 : in std_logic_vector(7 downto 0);
+ hub_register_01 : in std_logic_vector(7 downto 0);
+ hub_register_02 : in std_logic_vector(7 downto 0);
+ hub_register_03 : in std_logic_vector(7 downto 0);
+ hub_register_04 : in std_logic_vector(7 downto 0);
+ hub_register_05 : in std_logic_vector(7 downto 0);
+ hub_register_06 : in std_logic_vector(7 downto 0);
+ hub_register_07 : in std_logic_vector(7 downto 0);
+ hub_register_08 : in std_logic_vector(7 downto 0);
+ hub_register_09 : in std_logic_vector(7 downto 0);
+ hub_register_0a : out std_logic_vector(7 downto 0);
+ hub_register_0b : out std_logic_vector(7 downto 0);
+ hub_register_0c : out std_logic_vector(7 downto 0);
+ hub_register_0d : out std_logic_vector(7 downto 0);
+ hub_register_0e : out std_logic_vector(7 downto 0);
+ hub_register_0f : out std_logic_vector(7 downto 0);
+ hub_register_10 : in std_logic_vector(7 downto 0);
+ hub_register_11 : in std_logic_vector(7 downto 0);
+ hub_register_12 : in std_logic_vector(7 downto 0);
+ hub_register_13 : in std_logic_vector(7 downto 0);
+ hub_register_14 : in std_logic_vector(7 downto 0);
+ hub_register_15 : in std_logic_vector(7 downto 0);
+ hub_register_16 : in std_logic_vector(7 downto 0)
+ );
+ end component;
+ component serdes_fpga_ref_clk--serdes, flexi PCS
+ port(
+-- refclkp : in std_logic;
+-- refclkn : in std_logic;
+ rxrefclk : in std_logic;
+ refclk : in std_logic;
+ hdinp_0 : in std_logic;
+ hdinn_0 : in std_logic;
+ tclk_0 : in std_logic;
+ rclk_0 : in std_logic;
+ tx_rst_0 : in std_logic;
+ rx_rst_0 : in std_logic;
+ txd_0 : in std_logic_vector(15 downto 0);
+ tx_k_0 : in std_logic_vector(1 downto 0);
+ tx_force_disp_0 : in std_logic_vector(1 downto 0);
+ tx_disp_sel_0 : in std_logic_vector(1 downto 0);
+ tx_crc_init_0 : in std_logic_vector(1 downto 0);
+ word_align_en_0 : in std_logic;
+ mca_align_en_0 : in std_logic;
+ felb_0 : in std_logic;
+ lsm_en_0 : in std_logic;
+ hdinp_1 : in std_logic;
+ hdinn_1 : in std_logic;
+ tclk_1 : in std_logic;
+ rclk_1 : in std_logic;
+ tx_rst_1 : in std_logic;
+ rx_rst_1 : in std_logic;
+ txd_1 : in std_logic_vector(15 downto 0);
+ tx_k_1 : in std_logic_vector(1 downto 0);
+ tx_force_disp_1 : in std_logic_vector(1 downto 0);
+ tx_disp_sel_1 : in std_logic_vector(1 downto 0);
+ tx_crc_init_1 : in std_logic_vector(1 downto 0);
+ word_align_en_1 : in std_logic;
+ mca_align_en_1 : in std_logic;
+ felb_1 : in std_logic;
+ lsm_en_1 : in std_logic;
+ hdinp_2 : in std_logic;
+ hdinn_2 : in std_logic;
+ tclk_2 : in std_logic;
+ rclk_2 : in std_logic;
+ tx_rst_2 : in std_logic;
+ rx_rst_2 : in std_logic;
+ txd_2 : in std_logic_vector(15 downto 0);
+ tx_k_2 : in std_logic_vector(1 downto 0);
+ tx_force_disp_2 : in std_logic_vector(1 downto 0);
+ tx_disp_sel_2 : in std_logic_vector(1 downto 0);
+ tx_crc_init_2 : in std_logic_vector(1 downto 0);
+ word_align_en_2 : in std_logic;
+ mca_align_en_2 : in std_logic;
+ felb_2 : in std_logic;
+ lsm_en_2 : in std_logic;
+ hdinp_3 : in std_logic;
+ hdinn_3 : in std_logic;
+ tclk_3 : in std_logic;
+ rclk_3 : in std_logic;
+ tx_rst_3 : in std_logic;
+ rx_rst_3 : in std_logic;
+ txd_3 : in std_logic_vector(15 downto 0);
+ tx_k_3 : in std_logic_vector(1 downto 0);
+ tx_force_disp_3 : in std_logic_vector(1 downto 0);
+ tx_disp_sel_3 : in std_logic_vector(1 downto 0);
+ tx_crc_init_3 : in std_logic_vector(1 downto 0);
+ word_align_en_3 : in std_logic;
+ mca_align_en_3 : in std_logic;
+ felb_3 : in std_logic;
+ lsm_en_3 : in std_logic;
+ mca_resync_01 : in std_logic;
+ mca_resync_23 : in std_logic;
+ quad_rst : in std_logic;
+ serdes_rst : in std_logic;
+ rxa_pclk : out std_logic;
+ rxb_pclk : out std_logic;
+ hdoutp_0 : out std_logic;
+ hdoutn_0 : out std_logic;
+ ref_0_sclk : out std_logic;
+ rx_0_sclk : out std_logic;
+ rxd_0 : out std_logic_vector(15 downto 0);
+ rx_k_0 : out std_logic_vector(1 downto 0);
+ rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
+ rx_cv_detect_0 : out std_logic_vector(1 downto 0);
+ rx_crc_eop_0 : out std_logic_vector(1 downto 0);
+ lsm_status_0 : out std_logic;
+ hdoutp_1 : out std_logic;
+ hdoutn_1 : out std_logic;
+ ref_1_sclk : out std_logic;
+ rx_1_sclk : out std_logic;
+ rxd_1 : out std_logic_vector(15 downto 0);
+ rx_k_1 : out std_logic_vector(1 downto 0);
+ rx_disp_err_detect_1 : out std_logic_vector(1 downto 0);
+ rx_cv_detect_1 : out std_logic_vector(1 downto 0);
+ rx_crc_eop_1 : out std_logic_vector(1 downto 0);
+ lsm_status_1 : out std_logic;
+ hdoutp_2 : out std_logic;
+ hdoutn_2 : out std_logic;
+ ref_2_sclk : out std_logic;
+ rx_2_sclk : OUT std_logic;
+ rxd_2 : OUT std_logic_vector(15 downto 0);
+ rx_k_2 : OUT std_logic_vector(1 downto 0);
+ rx_disp_err_detect_2 : OUT std_logic_vector(1 downto 0);
+ rx_cv_detect_2 : OUT std_logic_vector(1 downto 0);
+ rx_crc_eop_2 : OUT std_logic_vector(1 downto 0);
+ lsm_status_2 : OUT std_logic;
+ hdoutp_3 : OUT std_logic;
+ hdoutn_3 : OUT std_logic;
+ ref_3_sclk : OUT std_logic;
+ rx_3_sclk : OUT std_logic;
+ rxd_3 : OUT std_logic_vector(15 downto 0);
+ rx_k_3 : OUT std_logic_vector(1 downto 0);
+ rx_disp_err_detect_3 : out std_logic_vector(1 downto 0);
+ rx_cv_detect_3 : out std_logic_vector(1 downto 0);
+ rx_crc_eop_3 : out std_logic_vector(1 downto 0);
+ lsm_status_3 : out std_logic;
+ mca_aligned_01 : out std_logic;
+ mca_inskew_01 : out std_logic;
+ mca_outskew_01 : out std_logic;
+ mca_aligned_23 : out std_logic;
+ mca_inskew_23 : out std_logic;
+ mca_outskew_23 : out std_logic;
+ ref_pclk : out std_logic
+ );
+ end component;
+ component flexi_PCS_synch
+ generic (
+ HOW_MANY_CHANNELS : positive);
+ port (
+ SYSTEM_CLK : in std_logic;
+ CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
+ RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ RESET : in std_logic;
+ RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
+ MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
+ );
+ end component;
+ component pll_ref
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+-- component trb_net16_hub_base
+-- generic (
+-- --general settings
+-- MUX_SECURE_MODE : integer range 0 to 1 := c_NO;
+-- --hub control
+-- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL;
+-- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
+-- HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
+-- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+-- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+-- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F00A";
+-- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+-- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+-- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+-- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+-- --media interfaces
+-- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := HOW_MANY_CHANNELS;
+-- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+-- -- settings for apis
+-- API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
+-- API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
+-- API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0);
+-- API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
+-- API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
+-- --trigger reading interfaces
+-- TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0;
+-- TRG_SECURE_MODE : integer range 0 to 1 := c_NO;
+-- TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0)
+-- );
+-- port (
+-- CLK : in std_logic;
+-- RESET : in std_logic;
+-- CLK_EN : in std_logic;
+-- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+-- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+-- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+-- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+-- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+-- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+-- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+-- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+-- MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
+-- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+-- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+-- APL_DATA_IN : in std_logic_vector (API_NUMBER*c_DATA_WIDTH downto 0);
+-- APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
+-- APL_DATAREADY_IN : in std_logic_vector (API_NUMBER downto 0);
+-- APL_READ_OUT : out std_logic_vector (API_NUMBER downto 0);
+-- APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0);
+-- APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0);
+-- APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0);
+-- APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0);
+-- APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
+-- APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0);
+-- APL_PACKET_NUM_OUT : out std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
+-- APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0);
+-- APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0);
+-- APL_READ_IN : in std_logic_vector (API_NUMBER downto 0);
+-- APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0);
+-- APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
+-- APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0);
+-- TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0);
+-- TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);
+-- TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0);
+-- TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0);
+-- TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0);
+-- TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0);
+-- ONEWIRE : inout std_logic;
+-- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+-- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+-- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+-- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+-- ETRAX_CTRL : in std_logic_vector (15 downto 0)
+-- );
+-- end component;
+ component simpleupcounter_16bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component simpleupcounter_32bit
+ port (
+ QOUT : out std_logic_vector(31 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component trb_net_onewire
+ generic (
+ USE_TEMPERATURE_READOUT : integer range 0 to 1;
+ CLK_PERIOD : integer);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ONEWIRE : inout std_logic;
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(2 downto 0);
+ WRITE_OUT : out std_logic;
+ TEMP_OUT : out std_logic_vector(11 downto 0);
+ STAT : out std_logic_vector(31 downto 0));
+ end component;
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component DCS
+-- synthesis translate_off
+ --sim
+ generic (
+ DCSMODE : string := "LOW_LOW");
+-- synthesis translate_on
+ port (
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ SEL : in std_logic;
+ DCSOUT : out std_logic);
+ end component;
+ component etrax_interfacev2
+ generic (
+ RW_SYSTEM : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_BUS : in std_logic_vector(31 downto 0);
+ ETRAX_DATA_BUS_B : inout std_logic_vector(16 downto 0);
+ ETRAX_DATA_BUS_B_17 : in std_logic;
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_E : inout std_logic_vector(10 downto 9);
+ DATA_VALID : in std_logic;
+ ETRAX_BUS_BUSY : in std_logic;
+ ETRAX_IS_READY_TO_READ : out std_logic;
+ TDC_TCK : out std_logic;
+ TDC_TDI : out std_logic;
+ TDC_TMS : out std_logic;
+ TDC_TRST : out std_logic;
+ TDC_TDO : in std_logic;
+ TDC_RESET : out std_logic;
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(15 downto 0);
+ FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
+-- EXTERNAL_RESET : out std_logic;
+ LVL2_VALID : in std_logic);
+ end component;
+
+ component hub_etrax_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS : inout std_logic_vector(17 downto 5);
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(7 downto 0);
+ FPGA_REGISTER_00 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
+ EXTERNAL_RESET : out std_logic);
+ end component;
+
+ component simple_hub
+ generic (
+ HOW_MANY_CHANNELS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ DATA_IN_VALID : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ SEND_DATA : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ ENABLE_CHANNELS : in std_logic_vector(15 downto 0);
+ READ_DATA : out std_logic_vector(HOW_MANY_CHANNELS -1 downto 0);
+ HUB_DEBUG : out std_logic_vector(31 downto 0)
+ );
+ end component;
+-- constant HOW_MANY_CHANNELS : integer := 16;
+ -----------------------------------------------------------------------------
+ -- FLEXI_PCS
+ -----------------------------------------------------------------------------
+ signal ref_pclk : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
+ signal rxd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ signal rxd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ signal rx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal rx_rst_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ signal cv_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal txd_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ signal txd_synch_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ signal tx_k_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal rxb_pclk_a : std_logic_vector((HOW_MANY_CHANNELS+3)/4 -1 downto 0);
+ signal rx_clk_i : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ signal flexi_pcs_synch_status_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ signal word_align_en : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ -----------------------------------------------------------------------------
+ -- hub trb interface
+ -----------------------------------------------------------------------------
+ signal hub_register_00_i : std_logic_vector(31 downto 0);
+ signal hub_register_01_i : std_logic_vector(31 downto 0);
+ signal hub_register_02_i : std_logic_vector(31 downto 0);
+ signal hub_register_03_i : std_logic_vector(31 downto 0);
+ signal hub_register_04_i : std_logic_vector(31 downto 0);
+ signal hub_register_05_i : std_logic_vector(31 downto 0);
+ signal hub_register_06_i : std_logic_vector(31 downto 0);
+ signal hub_register_07_i : std_logic_vector(31 downto 0);
+ signal hub_register_08_i : std_logic_vector(31 downto 0);
+ signal hub_register_09_i : std_logic_vector(31 downto 0);
+ signal hub_register_0a_i : std_logic_vector(31 downto 0);
+ signal hub_register_0b_i : std_logic_vector(31 downto 0);
+ signal hub_register_0c_i : std_logic_vector(31 downto 0);
+ signal hub_register_0d_i : std_logic_vector(31 downto 0);
+ signal hub_register_0e_i : std_logic_vector(31 downto 0);
+ signal hub_register_0f_i : std_logic_vector(31 downto 0);
+ signal hub_register_10_i : std_logic_vector(31 downto 0);
+ signal hub_register_11_i : std_logic_vector(31 downto 0);
+ signal hub_register_12_i : std_logic_vector(31 downto 0);
+ signal hub_register_13_i : std_logic_vector(31 downto 0);
+ signal hub_register_14_i : std_logic_vector(31 downto 0);
+ signal hub_register_15_i : std_logic_vector(31 downto 0);
+ signal hub_register_16_i : std_logic_vector(31 downto 0);
+ signal ADO_TTL_12 : std_logic;
+ -----------------------------------------------------------------------------
+ -- flexi_PCS to hub interface
+ -----------------------------------------------------------------------------
+ signal med_dataready_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ --test
+ signal data_valid_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal med_dataready_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal med_read_in_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal med_read_out_i : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal med_data_out_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ signal med_data_in_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ signal med_packet_num_out_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ signal med_packet_num_in_i : std_logic_vector(HOW_MANY_CHANNELS*c_NUM_WIDTH-1 downto 0);
+ signal med_error_out_i : std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
+ signal med_stat_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ signal hub_stat_gen_i : std_logic_vector(31 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- other
+ -----------------------------------------------------------------------------
+ signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006";
+ signal cv_counter : std_logic_vector(31 downto 0);
+ signal cv_countera : std_logic_vector(31 downto 0);
+ signal serdes_ref_clk : std_logic;
+ signal serdes_ref_lock : std_logic;
+ signal serdes_ref_clks : std_logic;
+ signal med_packet_num_in_s : std_logic_vector(HOW_MANY_CHANNELS*2 -1 downto 0);
+ signal mplex_ctrl_i : std_logic_vector (HOW_MANY_CHANNELS*32-1 downto 0);
+ signal word_counter_for_api_00 : std_logic_vector(1 downto 0);
+ signal word_counter_for_api_01 : std_logic_vector(1 downto 0);
+ signal global_reset_i : std_logic;
+ signal global_reset_cnt : std_logic_vector(3 downto 0):=x"0";
+ signal registered_signals : std_logic_vector(7 downto 0);
+ signal hub_register_0a_i_synch : std_logic_vector(7 downto 0);
+ signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
+ signal test_signal : std_logic_vector(1 downto 0);
+ signal pulse_test : std_logic;
+ signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
+ signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
+ signal all_lvl1_ready : std_logic;
+ signal all_lvl2_ready : std_logic;
+ signal flexi_pcs_ref_clk : std_logic;
+ signal lok_i : std_logic_vector(16 downto 1);
+ signal not_used_lok : std_logic_vector(15 downto 0);
+ signal used_channels_locked : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal channels_locked : std_logic_vector(16 downto 1);
+ signal switch_rx_clk : std_logic;
+ signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal all_lvl1_ready_delay1 : std_logic;
+ signal all_lvl1_ready_delay2 : std_logic;
+ signal all_lvl2_ready_delay1 : std_logic;
+ signal all_lvl2_ready_delay2 : std_logic;
+ -- etrax interface
+-- signal external_address_i : std_logic_vector(31 downto 0);
+-- signal external_data_out_i : std_logic_vector(31 downto 0);
+-- signal external_data_in_i : std_logic_vector(31 downto 0);
+-- signal external_ack_i : std_logic;
+-- signal external_valid_i : std_logic;
+-- signal external_mode_i : std_logic_vector(7 downto 0);
+-- signal data_valid_i : std_logic;
+ signal debug_register_00_i : std_logic_vector(7 downto 0);
+ signal test2 : std_logic_vector(1 downto 0);
+ signal med_read_counter : std_logic_vector(3 downto 0);
+ -- simulation
+ signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
+ constant trb_net_enable : integer := 0;
+ --etrax interface
+ signal external_address_i : std_logic_vector(31 downto 0);
+ signal external_data_out_i : std_logic_vector(31 downto 0);
+ signal external_data_in_i : std_logic_vector(31 downto 0);
+ signal external_ack_i : std_logic;
+ signal external_valid_i : std_logic;
+ signal external_mode_i : std_logic_vector(15 downto 0);
+ signal fpga_register_00_i : std_logic_vector(31 downto 0);
+ signal fpga_register_01_i : std_logic_vector(31 downto 0);
+ signal fpga_register_02_i : std_logic_vector(31 downto 0);
+ signal fpga_register_03_i : std_logic_vector(31 downto 0);
+ signal fpga_register_04_i : std_logic_vector(31 downto 0);
+ signal fpga_register_05_i : std_logic_vector(31 downto 0);
+ signal fpga_register_06_i : std_logic_vector(31 downto 0):=x"00000003";
+ signal fpga_register_07_i : std_logic_vector(31 downto 0);
+ signal fpga_register_08_i : std_logic_vector(31 downto 0);
+ signal fpga_register_09_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0a_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0b_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0c_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0d_i : std_logic_vector(31 downto 0);
+ signal fpga_register_0e_i : std_logic_vector(31 downto 0);
+ --simple hub
+ signal hub_debug_i : std_logic_vector(31 downto 0);
+ --test
+ constant OPT_TEST_MODE : integer := 1;
+
+begin
+ GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
+ begin
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_cnt < x"e" then
+ global_reset_cnt <= global_reset_cnt + 1;
+ global_reset_i <= '1';
+ elsif global_reset_cnt = x"e" then
+ global_reset_i <= '0';
+ global_reset_cnt <= x"e";
+ else
+ global_reset_i <= '0';
+ global_reset_cnt <= global_reset_cnt;
+ end if;
+ end if;
+ end process GLOBAL_RESET;
+ REF_PLL: pll_ref
+ port map (
+ clk => LVDS_CLK_200P,
+ clkop => serdes_ref_clk,
+ clkos => serdes_ref_clks,
+ lock => serdes_ref_lock);
+ TEST: edge_to_pulse
+ port map (
+ clock => ref_pclk(0),
+ en_clk => '1',
+ signal_in => hub_register_0a_i(0),
+ pulse => pulse_test);
+ test_signal(1) <= pulse_test;
+ test_signal(0) <= pulse_test;
+ REF_CLK_SELECT: DCS
+ -- synthesis translate_off
+
+ generic map (--no_sim--
+ DCSMODE => DCSMODE)--no_sim--
+ -- synthesis translate_on
+ port map (
+ CLK0 => LVDS_CLK_200P,
+ CLK1 => '0',
+ SEL => switch_rx_clk,--hub_register_0a_i(0),--'0',--switch_rx_clk,
+ DCSOUT => flexi_pcs_ref_clk);
+ SWITCH_CLOCK: process (LVDS_CLK_200P, global_reset_i)
+ begin -- process SWITCH_CLOCK
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' or lock_pattern /= used_channels_locked then -- asynchronous reset (active low)
+ switch_rx_clk <= '0';
+ lock_pattern <= (others => '1');
+ elsif lock_pattern = used_channels_locked then
+ switch_rx_clk <= '1';
+ lock_pattern <= (others => '1');
+ end if;
+ end if;
+ end process SWITCH_CLOCK;
+-- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+-- begin
+-- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+-- end generate LOK_STATUS_DIOD_EN;
+
+ --lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1);
+ QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
+ begin
+ QUAD : serdes_fpga_ref_clk
+ port map (
+-- refclkp => SERDES_200P,
+-- refclkn => SERDES_200N,
+ rxrefclk => flexi_pcs_ref_clk,--LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
+ refclk => LVDS_CLK_200P,--serdes_ref_clk,--LVDS_CLK_200P,
+ hdinp_0 => SFP_INP_P(bit_index*4+0),
+ hdinn_0 => SFP_INP_N(bit_index*4+0),
+ tclk_0 => ref_pclk(bit_index),
+ rclk_0 => rx_clk_i(0+bit_index*4),
+ tx_rst_0 => '0',
+ rx_rst_0 => rx_rst_i(0+bit_index*4),--hub_register_0a_i(0),
+ txd_0 => txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--txd_synch_i(15+bit_index*64 downto 0+bit_index*64),--hub_register_0e_and_0d_synch,--
+ tx_k_0 => tx_k_i(1+bit_index*8 downto 0+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
+ tx_force_disp_0 => "00",--hub_register_0a_i(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--hub_register_0a_i_synch(3 downto 2),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),
+ tx_disp_sel_0 => "00",--hub_register_0a_i(5 downto 4), --"00",--hub_register_0a_i_synch(5 downto 4),--"00",
+ tx_crc_init_0 => "00",
+ word_align_en_0 => '1',--word_align_en(0+bit_index*4),--'1',
+ mca_align_en_0 => '0',
+ felb_0 => '0',
+ lsm_en_0 => '0',
+ hdinp_1 => SFP_INP_P(bit_index*4+1),
+ hdinn_1 => SFP_INP_N(bit_index*4+1),
+ tclk_1 => ref_pclk(bit_index),
+ rclk_1 => rx_clk_i(1+bit_index*4),
+ tx_rst_1 => '0',
+ rx_rst_1 => rx_rst_i(1+bit_index*4),
+ txd_1 => txd_synch_i(31+bit_index*64 downto 16+bit_index*64),
+ tx_k_1 => tx_k_i(3+bit_index*8 downto 2+bit_index*8),--tx_force_disp_i(bit_index*8+1 downto 0+bit_index*8),--"10",--"10",--hub_register_0a_i_synch(1 downto 0),--"10",
+ tx_force_disp_1 => "00",--tx_k_i(3+bit_index*8 downto 2+bit_index*8),
+ tx_disp_sel_1 => "00",
+ tx_crc_init_1 => "00",
+ word_align_en_1 => '1',--word_align_en(1+bit_index*4),--'1',--
+ mca_align_en_1 => '0',
+ felb_1 => '0',
+ lsm_en_1 => '0',
+ hdinp_2 => SFP_INP_P(bit_index*4+2),
+ hdinn_2 => SFP_INP_N(bit_index*4+2),
+ tclk_2 => ref_pclk(bit_index),
+ rclk_2 => rx_clk_i(2+bit_index*4),
+ tx_rst_2 => '0',
+ rx_rst_2 => rx_rst_i(2+bit_index*4),
+ txd_2 => txd_synch_i(47+bit_index*64 downto 32+bit_index*64),
+ tx_k_2 => tx_k_i(5+bit_index*8 downto 4+bit_index*8),--"10",
+ tx_force_disp_2 => "00",--
+ tx_disp_sel_2 => "00",
+ tx_crc_init_2 => "00",
+ word_align_en_2 => '1',--word_align_en(2+bit_index*4),--'1',
+ mca_align_en_2 => '0',
+ felb_2 => '0',
+ lsm_en_2 => '0',
+ hdinp_3 => SFP_INP_P(bit_index*4+3),
+ hdinn_3 => SFP_INP_N(bit_index*4+3),
+ tclk_3 => ref_pclk(bit_index),
+ rclk_3 => rx_clk_i(3+bit_index*4),
+ tx_rst_3 => '0',
+ rx_rst_3 => rx_rst_i(3+bit_index*4),
+ txd_3 => txd_synch_i(63+bit_index*64 downto 48+bit_index*64),
+ tx_k_3 => tx_k_i(7+bit_index*8 downto 6+bit_index*8),--"10",
+ tx_force_disp_3 => "00",
+ tx_disp_sel_3 => "00",
+ tx_crc_init_3 => "00",
+ word_align_en_3 => '1',--word_align_en(3+bit_index*4),--'1',
+ mca_align_en_3 => '0',
+ felb_3 => '0',
+ lsm_en_3 => '0',
+ mca_resync_01 => '0',
+ mca_resync_23 => '0',
+ quad_rst => '0',
+ serdes_rst => '0',
+ rxa_pclk => rx_clk_i(0+bit_index*4),
+ rxb_pclk => rxb_pclk_a(bit_index),
+ hdoutp_0 => SFP_OUT_P(bit_index*4+0),
+ hdoutn_0 => SFP_OUT_N(bit_index*4+0),
+ ref_0_sclk => open,
+ rx_0_sclk => open,
+ rxd_0 => rxd_i(15+bit_index*64 downto 0+bit_index*64),
+ rx_k_0 => rx_k_i(1+bit_index*8 downto 0+bit_index*8),
+ rx_disp_err_detect_0 => open, --rx_disp_err_detect_0_a,
+ rx_cv_detect_0 => cv_i(1+bit_index*8 downto 0+bit_index*8),
+ rx_crc_eop_0 => open,
+ lsm_status_0 => open,
+ hdoutp_1 => SFP_OUT_P(bit_index*4+1),
+ hdoutn_1 => SFP_OUT_N(bit_index*4+1),
+ ref_1_sclk => open,
+ rx_1_sclk => rx_clk_i(1+bit_index*4),
+ rxd_1 => rxd_i(31+bit_index*64 downto 16+bit_index*64),
+ rx_k_1 => rx_k_i(3+bit_index*8 downto 2+bit_index*8),
+ rx_disp_err_detect_1 => open, --rx_disp_err_detect_1_a,
+ rx_cv_detect_1 => cv_i(3+bit_index*8 downto 2+bit_index*8),
+ rx_crc_eop_1 => open,
+ lsm_status_1 => open,
+ hdoutp_2 => SFP_OUT_P(bit_index*4+2),
+ hdoutn_2 => SFP_OUT_N(bit_index*4+2),
+ ref_2_sclk => open,
+ rx_2_sclk => rx_clk_i(2+bit_index*4),
+ rxd_2 => rxd_i(47+bit_index*64 downto 32+bit_index*64),
+ rx_k_2 => rx_k_i(5+bit_index*8 downto 4+bit_index*8),
+ rx_disp_err_detect_2 => open, --rx_disp_err_detect_2_a,
+ rx_cv_detect_2 => cv_i(5+bit_index*8 downto 4+bit_index*8),
+ rx_crc_eop_2 => open,
+ lsm_status_2 => open,
+ hdoutp_3 => SFP_OUT_P(bit_index*4+3),
+ hdoutn_3 => SFP_OUT_N(bit_index*4+3),
+ ref_3_sclk => open,
+ rx_3_sclk => rx_clk_i(3+bit_index*4),
+ rxd_3 => rxd_i(63+bit_index*64 downto 48+bit_index*64),
+ rx_k_3 => rx_k_i(7+bit_index*8 downto 6+bit_index*8),
+ rx_disp_err_detect_3 => open, --rx_disp_err_detect_3_a,
+ rx_cv_detect_3 => cv_i(7+bit_index*8 downto 6+bit_index*8),
+ rx_crc_eop_3 => open,
+ lsm_status_3 => open,
+ mca_aligned_01 => open, --mca_aligned_01_i,
+ mca_inskew_01 => open, --mca_inskew_01_i,
+ mca_outskew_01 => open, --mca_outskew_01_i,
+ mca_aligned_23 => open, --mca_aligned_23_i,
+ mca_inskew_23 => open, --mca_inskew_23_i,
+ mca_outskew_23 => open, --mca_outskew_23_i,
+ ref_pclk => ref_pclk(bit_index)
+ );
+ end generate QUAD_GENERATE;
+ -- word_align_en <= not rx_rst_i;
+--sim-- SIMULATION_CONNECTION: for i in 0 to HOW_MANY_CHANNELS-1 generate
+--sim-- rx_k_sim(i*2) <= not OPT_DATA_VALID_IN(i);
+--sim-- rx_k_sim(i*2+1) <= '0';
+--sim-- OPT_DATA_VALID_OUT(i) <= not tx_k_sim(i*2);
+--sim-- rx_clk_sim <= (others => LVDS_CLK_200P);
+--sim-- ref_pclk_sim <= (others => LVDS_CLK_200P);
+--sim-- cv_sim <= (others => '0');
+--sim-- end generate SIMULATION_CONNECTION;
+ FLEXI_PCS_INT : flexi_PCS_synch
+ generic map (
+ HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
+ port map (
+ SYSTEM_CLK => LVDS_CLK_200P,
+ CLK => ref_pclk,--no_sim--
+--sim-- CLK => ref_pclk_sim,
+ RX_CLK => rx_clk_i,--no_sim--
+--sim-- RX_CLK => rx_clk_sim,
+ RESET => global_reset_i,
+ RXD => rxd_i,--no_sim--
+--sim-- RXD => OPT_DATA_IN,
+ MED_DATA_OUT => med_data_out_i,
+ RX_K => rx_k_i,--no_sim--
+--sim-- RX_K => rx_k_sim,
+ RX_RST => rx_rst_i,
+ CV => cv_i,--no_sim--
+--sim-- CV => cv_sim,
+ MED_DATA_IN => med_data_in_i,
+ TXD_SYNCH => txd_synch_i, --no_sim--
+--sim-- TXD_SYNCH => OPT_DATA_OUT,
+ TX_K => tx_k_i, --no_sim--
+--sim-- TX_K => tx_k_sim,
+ FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i,
+ MED_DATAREADY_IN => med_dataready_in_i,
+ MED_DATAREADY_OUT => med_dataready_out_i,
+ MED_PACKET_NUM_IN => med_packet_num_in_i,
+ MED_PACKET_NUM_OUT => med_packet_num_out_i,
+ MED_READ_IN => med_read_in_i,
+ MED_READ_OUT => med_read_out_i,
+ MED_ERROR_OUT => med_error_out_i,
+ MED_STAT_OP => med_stat_op_i,
+ MED_CTRL_OP => med_ctrl_op_i
+ );
+-- SIMPLE_HUB_GEN: if trb_net_enable = 0 and OPT_TEST_MODE = 0 generate
+-- SIMPLE_HUB_INST: simple_hub
+-- generic map (
+-- HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
+-- port map (
+-- CLK => LVDS_CLK_200P,
+-- RESET => global_reset_i,
+-- DATA_IN => med_data_out_i,
+-- DATA_OUT => med_data_in_i,
+-- DATA_IN_VALID => med_dataready_out_i,
+-- SEND_DATA => med_dataready_in_i,
+-- ENABLE_CHANNELS => fpga_register_06_i(15 downto 0),
+-- READ_DATA => med_read_in_i,
+-- HUB_DEBUG => hub_debug_i
+-- );
+
+-- end generate SIMPLE_HUB_GEN;
+
+-- ENABLE_OPT_TEST: if OPT_TEST_MODE = 1 generate
+ med_read_in_i <= (others => '1');
+ med_data_in_i <= med_data_out_i;
+ med_dataready_in_i <= med_dataready_out_i;
+-- end generate ENABLE_OPT_TEST;
+-- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
+-- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0);
+-- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
+-- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0);
+-- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
+-- med_read_in_i <= (others => '1'); --test
+
+-- ENABLE_TRB_NET: if trb_net_enable = 1 generate
+-- HUB_API: trb_net16_hub_base
+-- port map (
+-- CLK => LVDS_CLK_200P,
+-- RESET => global_reset_i,
+-- CLK_EN => '1',
+-- MED_DATAREADY_OUT => med_dataready_in_i,
+-- MED_DATA_OUT => med_data_in_i,
+-- MED_PACKET_NUM_OUT => med_packet_num_in_i,
+-- MED_READ_IN => med_read_out_i,
+-- MED_DATAREADY_IN => med_dataready_out_i,
+-- MED_DATA_IN => med_data_out_i,
+-- MED_PACKET_NUM_IN => med_packet_num_out_i,
+-- MED_READ_OUT => med_read_in_i,
+-- MED_ERROR_IN => med_error_out_i,
+-- MED_STAT_OP => med_stat_op_i,
+-- MED_CTRL_OP => med_ctrl_op_i,
+-- APL_DATA_IN => (others => '0'),
+-- APL_PACKET_NUM_IN => (others => '0'),
+-- APL_DATAREADY_IN => (others => '0'),
+-- APL_READ_OUT => open,
+-- APL_SHORT_TRANSFER_IN => (others => '0'),
+-- APL_DTYPE_IN => (others => '0'),
+-- APL_ERROR_PATTERN_IN => (others => '0'),
+-- APL_SEND_IN => (others => '0'),
+-- APL_TARGET_ADDRESS_IN => (others => '0'),
+-- APL_DATA_OUT => open,
+-- APL_PACKET_NUM_OUT => open,
+-- APL_TYP_OUT => open,
+-- APL_DATAREADY_OUT => open,
+-- APL_READ_IN => (others => '0'),
+-- APL_RUN_OUT => open,
+-- APL_MY_ADDRESS_IN => (others => '0'),
+-- APL_SEQNR_OUT => open,
+-- TRG_GOT_TRIGGER_OUT => open,
+-- TRG_ERROR_PATTERN_OUT => open,
+-- TRG_DTYPE_OUT => open,
+-- TRG_SEQNR_OUT => open,
+-- TRG_ERROR_PATTERN_IN => (others => '0'),
+-- TRG_RELEASE_IN => (others => '0'),
+-- ONEWIRE => FS_PE_11,
+-- HUB_STAT_CHANNEL => hub_stat_channel_i,
+-- HUB_STAT_GEN => hub_stat_gen_i,
+-- MPLEX_CTRL => mplex_ctrl_i,
+-- MPLEX_STAT => open,
+-- ETRAX_CTRL => hub_register_0e_and_0d
+-- );
+-- end generate ENABLE_TRB_NET;
+ ETRAX_RW_DATA_INTERFACE: etrax_interfacev2
+ generic map (
+ RW_SYSTEM => 2)
+ port map (
+ CLK => LVDS_CLK_200P,
+ RESET => global_reset_i,
+ DATA_BUS => (others => '0'),
+ ETRAX_DATA_BUS_B => open,--(others => '0'),
+ ETRAX_DATA_BUS_B_17 => '0',
+ ETRAX_DATA_BUS_C => open,--(others => '0'),
+ ETRAX_DATA_BUS_E => FS_PE(9 downto 8),
+ DATA_VALID => '0',
+ ETRAX_BUS_BUSY => '0',
+ ETRAX_IS_READY_TO_READ => open,
+ TDC_TCK => open,
+ TDC_TDI => open,
+ TDC_TMS => open,
+ TDC_TRST => open,
+ TDC_TDO => '0',
+ TDC_RESET => open,
+ EXTERNAL_ADDRESS => external_address_i,
+ EXTERNAL_DATA_OUT => external_data_out_i,
+ EXTERNAL_DATA_IN => x"ddbbccaa",--external_data_in_i,
+ EXTERNAL_ACK => external_ack_i,
+ EXTERNAL_VALID => external_ack_i,--external_valid_i,
+ EXTERNAL_MODE => external_mode_i,
+ FPGA_REGISTER_00 => fpga_register_00_i,
+ FPGA_REGISTER_01 => fpga_register_01_i,
+ FPGA_REGISTER_02 => fpga_register_02_i,
+ FPGA_REGISTER_03 => fpga_register_03_i,
+ FPGA_REGISTER_04 => fpga_register_04_i,
+ FPGA_REGISTER_05 => fpga_register_05_i,
+ FPGA_REGISTER_06 => fpga_register_06_i,
+ FPGA_REGISTER_07 => fpga_register_07_i,
+ FPGA_REGISTER_08 => fpga_register_08_i,
+ FPGA_REGISTER_09 => fpga_register_09_i,
+ FPGA_REGISTER_0A => fpga_register_0A_i,
+ FPGA_REGISTER_0B => fpga_register_0B_i,
+ FPGA_REGISTER_0C => fpga_register_0C_i,
+ FPGA_REGISTER_0D => fpga_register_0D_i,
+ FPGA_REGISTER_0E => fpga_register_0E_i,
+ -- EXTERNAL_RESET => open,
+ LVL2_VALID => '0');
+ fpga_register_00_i <= x"0000"& lok_i;
+ fpga_register_01_i <= hub_debug_i;
+ fpga_register_02_i <= flexi_pcs_synch_status_i(31 downto 0);
+ fpga_register_03_i <= flexi_pcs_synch_status_i(63 downto 32);
+ fpga_register_04_i <= flexi_pcs_synch_status_i(95 downto 64);
+
+ COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i )
+ begin
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' then
+ fpga_register_05_i <= (others => '0');
+ elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then
+ fpga_register_05_i <= fpga_register_05_i + 1;
+ end if;
+ end if;
+ end process COUNT_LVL1_START;
+
+ COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i )
+ begin
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' then
+ fpga_register_08_i <= (others => '0');
+ elsif med_dataready_in_i(1) = '1' and med_data_in_i(31 downto 28) = x"1" then
+ fpga_register_08_i <= fpga_register_08_i + 1;
+ end if;
+ end if;
+ end process COUNT_LVL1_SEND;
+
+ COUNT_LVL1_SEND: process (LVDS_CLK_200P, global_reset_i )
+ begin
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' then
+ fpga_register_09_i <= (others => '0');
+ elsif med_dataready_in_i(1) = '1' then
+ fpga_register_09_i <= fpga_register_08_i + 1;
+ end if;
+ end if;
+ end process COUNT_LVL1_SEND;
+
+ COUNT_LVL1_END: process (LVDS_CLK_200P, global_reset_i )
+ begin
+ if rising_edge(LVDS_CLK_200P) then
+ if global_reset_i = '1' then
+ fpga_register_07_i <= (others => '0');
+ elsif med_dataready_out_i(1) = '1' and med_data_out_i(31 downto 28) = x"1" then
+ fpga_register_07_i <= fpga_register_07_i + 1;
+ end if;
+ end if;
+ end process COUNT_LVL1_END;
+
+ TX_DIS_g : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+ begin
+ TX_DIS(synch_fsm_state+1) <= '0';
+ end generate;
+
+ TX_DIS_g1 : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
+ begin
+ WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
+ TX_DIS(16-not_connected) <= '1';
+ end generate WHEN_NOT_ALL_EN;
+ end generate;
+
+---------------------------------------------------------------------------
+-- setting LED
+---------------------------------------------------------------------------
+
+ --correct this for channels 11-8 - mirrored due to schematics -- also
+ --adressing of sfps !!!
+ LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+ begin
+ lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+ end generate LOK_STATUS_DIOD_EN;
+
+ LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate
+ begin
+ hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+ end generate LOK_STATUS_REGISTER_0;
+
+ LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate
+ begin
+ hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16);
+ end generate LOK_STATUS_REGISTER_1;
+
+ LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
+ begin
+ WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
+ lok_i(16-not_connected) <= '1';
+ end generate WHEN_NOT_ALL_EN;
+ end generate LOK_STATUS_DIOD_DIS;
+ LOK <= lok_i;
+ IPLL <= '0';
+ OPLL <= '0';
+ DBAD <= ADO_TTL(11);
+ DGOOD <= '1';
+ DINT <= '0';
+ DWAIT <= global_reset_i;
+
+ CV_COUNTERaaa: process (LVDS_CLK_200P, global_reset_i)
+ begin
+ if rising_edge(LVDS_CLK_200P) then -- rising clock edge
+ if global_reset_i = '1' then -- asynchronous reset (active low)
+ cv_counter <= (others => '0');
+ else
+ cv_counter <= cv_counter + 1;
+ end if;
+ end if;
+ end process CV_COUNTERaaa;
+ CV_COUNTERaab: process (ref_pclk(0), global_reset_i)
+ begin
+ if rising_edge(ref_pclk(0)) then -- rising clock edge
+ if global_reset_i = '1' then -- asynchronous reset (active low)
+ cv_countera <= (others => '0');
+ else
+ cv_countera <= cv_countera + 1;
+ end if;
+ end if;
+ end process CV_COUNTERaab;
+ RT(8) <= cv_counter(23);
+ RT(9) <= med_read_in_i(0);
+ RT(16 downto 10) <= flexi_pcs_synch_status_i(7 downto 1);
+ RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
+ RT(1) <= not switch_rx_clk;--ref_pclk(0);
+
+ RT(3) <= LVDS_CLK_200P;
+
+ RT(4) <= rx_k_i(0);
+
+ RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
+ RT(6) <= med_data_out_i(0);--serdes_ref_clks;
+ RT(7) <= med_data_out_i(1);--serdes_ref_lock;
+
+end hub;
+
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+entity link_test is
+
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ VALID_IN : in std_logic;
+ VALID_OUT : out std_logic;
+ LINK_DEBUG : out std_logic_vector(31 downto 0);
+ LINK_INFO : in std_logic_vector(15 downto 0)
+ );
+
+end link_test;
+
+architecture link_test of link_test is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component mdc_dc_lvl1_dpram_rand
+ port (
+ DataInA : in std_logic_vector(7 downto 0);
+ DataInB : in std_logic_vector(7 downto 0);
+ AddressA : in std_logic_vector(8 downto 0);
+ AddressB : in std_logic_vector(8 downto 0);
+ ClockA : in std_logic;
+ ClockB : in std_logic;
+ ClockEnA : in std_logic;
+ ClockEnB : in std_logic;
+ WrA : in std_logic;
+ WrB : in std_logic;
+ ResetA : in std_logic;
+ ResetB : in std_logic;
+ QA : out std_logic_vector(7 downto 0);
+ QB : out std_logic_vector(7 downto 0));
+ end component;
+
+ component mdc_dc_lvl1_dpram_zero
+ port (
+ DataInA : in std_logic_vector(7 downto 0);
+ DataInB : in std_logic_vector(7 downto 0);
+ AddressA : in std_logic_vector(8 downto 0);
+ AddressB : in std_logic_vector(8 downto 0);
+ ClockA : in std_logic;
+ ClockB : in std_logic;
+ ClockEnA : in std_logic;
+ ClockEnB : in std_logic;
+ WrA : in std_logic;
+ WrB : in std_logic;
+ ResetA : in std_logic;
+ ResetB : in std_logic;
+ QA : out std_logic_vector(7 downto 0);
+ QB : out std_logic_vector(7 downto 0));
+ end component;
+ type TEST_LINK_FSM is (IDLE, TEST1, TEST2, TEST3, TEST4, TRANSMITION_ERROR) ;
+ signal TEST_LINK_FSM_current, TEST_LINK_FSM_next : TEST_LINK_FSM;
+ signal wait_for_second_board_counter : std_logic_vector(31 downto 0);
+ signal enable_sec_board_counter : std_logic;
+ signal mem_diff : std_logic;
+ signal mem_check_ok : std_logic;
+
+ signal random_memory_address : std_logic_vector(8 downto 0);
+ signal random_memory_send : std_logic;
+
+ signal zero_memory_read_address : std_logic_vector(8 downto 0);
+ signal zero_memory_write_address : std_logic_vector(8 downto 0);
+ signal zero_memory_read : std_logic;
+
+ signal zero_memory_data_out : std_logic_vector(7 downto 0);
+ signal rand_memory_data_out : std_logic_vector(7 downto 0);
+
+ signal counter_for_send_en : std_logic_vector(10 downto 0);
+
+ signal rand_memory_data_out_synch : std_logic_vector(7 downto 0);
+ signal rand_memory_data_out_synch_synch : std_logic_vector(7 downto 0);
+ signal rand_memory_data_out_synch_synch_synch : std_logic_vector(7 downto 0);
+
+ signal wait_for_data_counter : std_logic_vector(27 downto 0);
+ signal wait_for_data_en : std_logic;
+
+ signal link_debug_i : std_logic_vector(1 downto 0);
+ signal wait_for_data_reset : std_logic;
+
+ signal zero_memory_read_synch : std_logic;
+ signal wait_for_second_board_reset : std_logic;
+
+
+begin
+ TEST_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ TEST_LINK_FSM_current <= IDLE;
+ else
+ TEST_LINK_FSM_current <= TEST_LINK_FSM_next;
+ end if;
+ end if;
+ end process TEST_CLOCK;
+ FSM_TO_TEST_LINK : process (CLK)
+ begin
+ case TEST_LINK_FSM_current is
+ when IDLE =>
+ link_debug_i <= "01";
+ enable_sec_board_counter <= '0';
+ mem_check_ok <= '0';
+ random_memory_send <= '0';
+ wait_for_data_reset <= '1';
+ VALID_OUT <= '0';
+ wait_for_second_board_reset <= '1';
+ if LINK_INFO(0)='1' then
+ TEST_LINK_FSM_next <= TEST1;
+ else
+ TEST_LINK_FSM_next <= IDLE;
+ end if;
+ when TEST1 =>
+ link_debug_i <= "10";
+ enable_sec_board_counter <= '1';
+ mem_check_ok <= '0';
+ random_memory_send <= '0';
+ VALID_OUT <= '0';
+ wait_for_data_reset <= '1';
+ wait_for_second_board_reset <= '0';
+ if wait_for_second_board_counter(27)='1' then
+ TEST_LINK_FSM_next <= TEST2;
+ else
+ TEST_LINK_FSM_next <= TEST1;
+ end if;
+ when TEST2 =>
+ link_debug_i <= "11";
+ enable_sec_board_counter <= '0';
+ mem_check_ok <= '1';
+ random_memory_send <= '1';
+ VALID_OUT <= counter_for_send_en(10);
+ wait_for_data_reset <= '0';
+ wait_for_second_board_reset <= '0';
+ if (LINK_INFO(1)= '1' or LINK_INFO(2)='1' or mem_diff = '1') and wait_for_data_en = '0' then
+ TEST_LINK_FSM_next <= IDLE;
+ else
+ TEST_LINK_FSM_next <= TEST2;
+ end if;
+ when TRANSMITION_ERROR =>
+ link_debug_i <= "00";
+ enable_sec_board_counter <= '0';
+ mem_check_ok <= '0';
+ random_memory_send <= '0';
+ wait_for_data_reset <= '1';
+ wait_for_second_board_reset <= '0';
+ when others =>
+ link_debug_i <= "00";
+ enable_sec_board_counter <= '0';
+ mem_check_ok <= '0';
+ random_memory_send <= '0';
+ wait_for_data_reset <= '1';
+ wait_for_second_board_reset <= '0';
+ TEST_LINK_FSM_next <= IDLE;
+ end case;
+ end process FSM_TO_TEST_LINK;
+
+
+ WAIT_FOR_SECOND_BOARD: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_second_board_reset,
+ COUNT_OUT => wait_for_second_board_counter,
+ UP_IN => enable_sec_board_counter,
+ DOWN_IN => '0');
+ wait_for_data_en <= random_memory_send and (not wait_for_data_counter(27));
+
+ WAIT_FOR_DATA: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 28)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_data_reset,
+ COUNT_OUT => wait_for_data_counter,
+ UP_IN => wait_for_data_en,
+ DOWN_IN => '0');
+
+
+ WRITE_ZERO_MEM_ADDRESS: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 9)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_second_board_reset,--RESET,
+ COUNT_OUT => zero_memory_write_address,
+ UP_IN => VALID_IN,
+ DOWN_IN => '0');
+
+ READ_ZERO_MEM_ADDRESS: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 9)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_second_board_reset,--RESET,
+ COUNT_OUT => zero_memory_read_address,
+ UP_IN => zero_memory_read,
+ DOWN_IN => '0');
+
+ READ_RAND_MEM_ADDRESS: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 9)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_second_board_reset,--RESET,
+ COUNT_OUT => random_memory_address,
+ UP_IN => random_memory_send,
+ DOWN_IN => '0');
+
+ SEND_RAND_MEM_EN: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 11)
+ port map (
+ CLK => CLK,
+ RESET => wait_for_second_board_reset,--RESET,
+ COUNT_OUT => counter_for_send_en,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ MEM_RANDOM: mdc_dc_lvl1_dpram_rand
+ port map (
+ DataInA => (others => '0'),
+ DataInB => (others => '0'),
+ AddressA => random_memory_address,
+ AddressB => (others => '0'),
+ ClockA => CLK,
+ ClockB => CLK,
+ ClockEnA => '1',
+ ClockEnB => '0',
+ WrA => '0',
+ WrB => '0',
+ ResetA => '0',
+ ResetB => '0',
+ QA => rand_memory_data_out,
+ QB => open);
+
+ MEM_ZERO: mdc_dc_lvl1_dpram_zero
+ port map (
+ DataInA => DATA_IN(7 downto 0),
+ DataInB => (others => '0'),
+ AddressA => zero_memory_write_address,
+ AddressB => zero_memory_read_address,
+ ClockA => CLK,
+ ClockB => CLK,
+ ClockEnA => '1',
+ ClockEnB => '1',
+ WrA => VALID_IN,
+ WrB => '0',
+ ResetA => '0',
+ ResetB => '0',
+ QA => open,
+ QB => zero_memory_data_out);
+ START_COMPARISON: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1'or TEST_LINK_FSM_current = IDLE then
+ zero_memory_read <= '0';
+ elsif rand_memory_data_out = zero_memory_data_out then
+ zero_memory_read <= '1';
+ else
+-- zero_memory_read <= '0';
+ zero_memory_read <= zero_memory_read;
+ end if;
+ end if;
+ end process START_COMPARISON;
+ MAKE_COMPARISON: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1'or wait_for_second_board_reset = '1' then
+ mem_diff <= '1';
+ elsif rand_memory_data_out_synch_synch = zero_memory_data_out then
+ mem_diff <= '0';
+ elsif zero_memory_read_synch = '1' and rand_memory_data_out_synch_synch_synch /= zero_memory_data_out then
+ mem_diff <= '1';
+-- mem_diff <= '0';
+ end if;
+ end if;
+ end process MAKE_COMPARISON;
+
+ SYNCH_DATA: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or wait_for_second_board_reset = '1' then
+ rand_memory_data_out_synch_synch_synch <= (others => '0');
+ rand_memory_data_out_synch_synch <= (others => '0');
+ rand_memory_data_out_synch <= (others => '0');
+ zero_memory_read_synch <= '0';
+ else
+ rand_memory_data_out_synch_synch_synch<= rand_memory_data_out_synch_synch;
+ rand_memory_data_out_synch_synch<= rand_memory_data_out_synch;
+ rand_memory_data_out_synch <= rand_memory_data_out;
+ zero_memory_read_synch <= zero_memory_read;
+ end if;
+ end if;
+ end process SYNCH_DATA;
+
+
+ LINK_DEBUG(3 downto 0) <= zero_memory_data_out(3 downto 0);
+ LINK_DEBUG(7 downto 4) <= rand_memory_data_out_synch_synch_synch(3 downto 0);
+ LINK_DEBUG(9 downto 8) <= link_debug_i;
+ LINK_DEBUG(10) <= VALID_IN;
+ LINK_DEBUG(11) <= random_memory_send;
+ LINK_DEBUG(12) <= zero_memory_read;
+ LINK_DEBUG(14 downto 13) <= LINK_INFO(2 downto 1);
+ LINK_DEBUG(15) <= mem_diff;
+ DATA_OUT <= rand_memory_data_out & rand_memory_data_out;
+
+end link_test;
--- /dev/null
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSC quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSC quad to the final design requirements.
+
+DEVICE_NAME "LFE2M35E"
+PROTOCOL "G8B10B"
+CH0_MODE "DISABLE"
+CH1_MODE "DISABLE"
+CH2_MODE "SINGLE"
+CH3_MODE "DISABLE"
+PLL_SRC "CORE_TXREFCLK"
+DATARANGE "MEDHIGH"
+CH2_CDR_SRC "CORE_RXREFCLK"
+CH2_DATA_WIDTH "16"
+CH2_REFCK_MULT "20X"
+#REFCLK_RATE 100
+#FPGAINTCLK_RATE 100
+CH2_TDRV_AMP "0"
+CH2_TX_PRE "DISABLE"
+CH2_RTERM_TX "50"
+CH2_RX_EQ "DISABLE"
+CH2_RTERM_RX "50"
+CH2_RX_DCC "DC"
+LOS_THRESHOLD "0"
+PLL_TERM "50"
+PLL_DCC "DC"
+PLL_LOL_SET "0"
+CH2_TX_SB "NORMAL"
+CH2_RX_SB "NORMAL"
+CH2_8B10B "NORMAL"
+COMMA_A "1100000101"
+COMMA_B "0011111010"
+COMMA_M "1111111111"
+CH2_COMMA_ALIGN "DYNAMIC"
+CH2_CTC_BYP "BYPASS"
+CC_MATCH1 "0000000000"
+CC_MATCH2 "0000000000"
+CC_MATCH3 "0100011100"
+CC_MATCH4 "0100011100"
+CC_MATCH_MODE "MATCH_4"
+CC_MIN_IPG "0"
+CCHMARK "4"
+CCLMARK "4"
+OS_REFCK2CORE "1"
+OS_PLLQCLKPORTS "0"
+OS_INT_ALL "0"
+
--- /dev/null
+
+
+--synopsys translate_off
+
+library pcsc_work;
+use pcsc_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSC is
+GENERIC(
+ CONFIG_FILE : String := "pcs_for_ecp2m.txt"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+
+end PCSC;
+
+architecture PCSC_arch of PCSC is
+
+component PCSC_sim
+GENERIC(
+ CONFIG_FILE : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+end component;
+
+begin
+
+PCSC_sim_inst : PCSC_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE)
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
+ FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
+ FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
+ FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
+ FF_TX_F_CLK => FF_TX_F_CLK,
+ FF_TX_H_CLK => FF_TX_H_CLK,
+ FF_TX_Q_CLK => FF_TX_Q_CLK,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ OOB_OUT_0 => OOB_OUT_0,
+ OOB_OUT_1 => OOB_OUT_1,
+ OOB_OUT_2 => OOB_OUT_2,
+ OOB_OUT_3 => OOB_OUT_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7
+ );
+
+end PCSC_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library ECP2;
+use ECP2.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity pcs_for_ecp2m is
+ GENERIC (USER_CONFIG_FILE : String := "pcs_for_ecp2m.txt");
+ port (
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp2, hdinn2 : in std_logic;
+ hdoutp2, hdoutn2 : out std_logic;
+ ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic;
+ ff_txdata_ch2 : in std_logic_vector (15 downto 0);
+ ff_rxdata_ch2 : out std_logic_vector (15 downto 0);
+ ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0);
+ ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0);
+ ff_rxfullclk_ch2 : out std_logic;
+ ff_rxhalfclk_ch2 : out std_logic;
+ ff_force_disp_ch2 : in std_logic_vector (1 downto 0);
+ ff_disp_sel_ch2 : in std_logic_vector (1 downto 0);
+ ff_correct_disp_ch2 : in std_logic_vector (1 downto 0);
+ ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0);
+ ffc_rrst_ch2 : in std_logic;
+ ffc_signal_detect_ch2 : in std_logic;
+ ffc_enable_cgalign_ch2 : in std_logic;
+ ffc_lane_tx_rst_ch2 : in std_logic;
+ ffc_lane_rx_rst_ch2 : in std_logic;
+ ffc_txpwdnb_ch2 : in std_logic;
+ ffc_rxpwdnb_ch2 : in std_logic;
+ ffs_rlos_lo_ch2 : out std_logic;
+ ffs_rlol_ch2 : out std_logic;
+ oob_out_ch2 : out std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ refck2core : out std_logic;
+ ffs_plol : out std_logic);
+
+end pcs_for_ecp2m;
+
+architecture pcs_for_ecp2m_arch of pcs_for_ecp2m is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+component PCSC
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+end component;
+ attribute IS_ASB: string;
+ attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSC_INST : PCSC
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map (
+ FFC_CK_CORE_TX => core_txrefclk,
+ FFC_CK_CORE_RX => core_rxrefclk,
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+ HDINP0 => fpsc_vlo,
+ HDINN0 => fpsc_vlo,
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => fpsc_vlo,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => open,
+ FF_RX_H_CLK_0 => open,
+ FF_RX_Q_CLK_0 => open,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => open,
+ FF_RX_D_0_1 => open,
+ FF_RX_D_0_2 => open,
+ FF_RX_D_0_3 => open,
+ FF_RX_D_0_4 => open,
+ FF_RX_D_0_5 => open,
+ FF_RX_D_0_6 => open,
+ FF_RX_D_0_7 => open,
+ FF_RX_D_0_8 => open,
+ FF_RX_D_0_9 => open,
+ FF_RX_D_0_10 => open,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+ FFC_RRST_0 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_RXPWDNB_0 => fpsc_vlo,
+ FFS_RLOS_LO_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_LS_SYNC_STATUS_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_RLOL_0 => open,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ OOB_OUT_0 => open,
+ HDINP1 => fpsc_vlo,
+ HDINN1 => fpsc_vlo,
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => fpsc_vlo,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => open,
+ FF_RX_H_CLK_1 => open,
+ FF_RX_Q_CLK_1 => open,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => open,
+ FF_RX_D_1_1 => open,
+ FF_RX_D_1_2 => open,
+ FF_RX_D_1_3 => open,
+ FF_RX_D_1_4 => open,
+ FF_RX_D_1_5 => open,
+ FF_RX_D_1_6 => open,
+ FF_RX_D_1_7 => open,
+ FF_RX_D_1_8 => open,
+ FF_RX_D_1_9 => open,
+ FF_RX_D_1_10 => open,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+ FFC_RRST_1 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_RXPWDNB_1 => fpsc_vlo,
+ FFS_RLOS_LO_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_LS_SYNC_STATUS_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_RLOL_1 => open,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ OOB_OUT_1 => open,
+ HDINP2 => hdinp2,
+ HDINN2 => hdinn2,
+ HDOUTP2 => hdoutp2,
+ HDOUTN2 => hdoutn2,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => ff_rxiclk_ch2,
+ FF_TXI_CLK_2 => ff_txiclk_ch2,
+ FF_EBRD_CLK_2 => ff_ebrd_clk_2,
+ FF_RX_F_CLK_2 => ff_rxfullclk_ch2,
+ FF_RX_H_CLK_2 => ff_rxhalfclk_ch2,
+ FF_RX_Q_CLK_2 => open,
+ FF_TX_D_2_0 => ff_txdata_ch2(0),
+ FF_TX_D_2_1 => ff_txdata_ch2(1),
+ FF_TX_D_2_2 => ff_txdata_ch2(2),
+ FF_TX_D_2_3 => ff_txdata_ch2(3),
+ FF_TX_D_2_4 => ff_txdata_ch2(4),
+ FF_TX_D_2_5 => ff_txdata_ch2(5),
+ FF_TX_D_2_6 => ff_txdata_ch2(6),
+ FF_TX_D_2_7 => ff_txdata_ch2(7),
+ FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0),
+ FF_TX_D_2_9 => ff_force_disp_ch2(0),
+ FF_TX_D_2_10 => ff_disp_sel_ch2(0),
+ FF_TX_D_2_11 => ff_correct_disp_ch2(0),
+ FF_TX_D_2_12 => ff_txdata_ch2(8),
+ FF_TX_D_2_13 => ff_txdata_ch2(9),
+ FF_TX_D_2_14 => ff_txdata_ch2(10),
+ FF_TX_D_2_15 => ff_txdata_ch2(11),
+ FF_TX_D_2_16 => ff_txdata_ch2(12),
+ FF_TX_D_2_17 => ff_txdata_ch2(13),
+ FF_TX_D_2_18 => ff_txdata_ch2(14),
+ FF_TX_D_2_19 => ff_txdata_ch2(15),
+ FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1),
+ FF_TX_D_2_21 => ff_force_disp_ch2(1),
+ FF_TX_D_2_22 => ff_disp_sel_ch2(1),
+ FF_TX_D_2_23 => ff_correct_disp_ch2(1),
+ FF_RX_D_2_0 => ff_rxdata_ch2(0),
+ FF_RX_D_2_1 => ff_rxdata_ch2(1),
+ FF_RX_D_2_2 => ff_rxdata_ch2(2),
+ FF_RX_D_2_3 => ff_rxdata_ch2(3),
+ FF_RX_D_2_4 => ff_rxdata_ch2(4),
+ FF_RX_D_2_5 => ff_rxdata_ch2(5),
+ FF_RX_D_2_6 => ff_rxdata_ch2(6),
+ FF_RX_D_2_7 => ff_rxdata_ch2(7),
+ FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0),
+ FF_RX_D_2_9 => ff_disp_err_ch2(0),
+ FF_RX_D_2_10 => ff_cv_ch2(0),
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => ff_rxdata_ch2(8),
+ FF_RX_D_2_13 => ff_rxdata_ch2(9),
+ FF_RX_D_2_14 => ff_rxdata_ch2(10),
+ FF_RX_D_2_15 => ff_rxdata_ch2(11),
+ FF_RX_D_2_16 => ff_rxdata_ch2(12),
+ FF_RX_D_2_17 => ff_rxdata_ch2(13),
+ FF_RX_D_2_18 => ff_rxdata_ch2(14),
+ FF_RX_D_2_19 => ff_rxdata_ch2(15),
+ FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1),
+ FF_RX_D_2_21 => ff_disp_err_ch2(1),
+ FF_RX_D_2_22 => ff_cv_ch2(1),
+ FF_RX_D_2_23 => open,
+ FFC_RRST_2 => ffc_rrst_ch2,
+ FFC_SIGNAL_DETECT_2 => ffc_signal_detect_ch2,
+ FFC_ENABLE_CGALIGN_2 => ffc_enable_cgalign_ch2,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFS_PCIE_DONE_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2,
+ FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2,
+ FFC_TXPWDNB_2 => ffc_txpwdnb_ch2,
+ FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2,
+ FFS_RLOS_LO_2 => ffs_rlos_lo_ch2,
+ FFS_LS_SYNC_STATUS_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ FFS_RLOL_2 => ffs_rlol_ch2,
+ OOB_OUT_2 => oob_out_ch2,
+ HDINP3 => fpsc_vlo,
+ HDINN3 => fpsc_vlo,
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => fpsc_vlo,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => open,
+ FF_RX_H_CLK_3 => open,
+ FF_RX_Q_CLK_3 => open,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => open,
+ FF_RX_D_3_1 => open,
+ FF_RX_D_3_2 => open,
+ FF_RX_D_3_3 => open,
+ FF_RX_D_3_4 => open,
+ FF_RX_D_3_5 => open,
+ FF_RX_D_3_6 => open,
+ FF_RX_D_3_7 => open,
+ FF_RX_D_3_8 => open,
+ FF_RX_D_3_9 => open,
+ FF_RX_D_3_10 => open,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+ FFC_RRST_3 => fpsc_vlo,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_RXPWDNB_3 => fpsc_vlo,
+ FFS_RLOS_LO_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_LS_SYNC_STATUS_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_RLOL_3 => open,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ OOB_OUT_3 => open,
+ SCIWDATA0 => fpsc_vlo,
+ SCIWDATA1 => fpsc_vlo,
+ SCIWDATA2 => fpsc_vlo,
+ SCIWDATA3 => fpsc_vlo,
+ SCIWDATA4 => fpsc_vlo,
+ SCIWDATA5 => fpsc_vlo,
+ SCIWDATA6 => fpsc_vlo,
+ SCIWDATA7 => fpsc_vlo,
+ SCIADDR0 => fpsc_vlo,
+ SCIADDR1 => fpsc_vlo,
+ SCIADDR2 => fpsc_vlo,
+ SCIADDR3 => fpsc_vlo,
+ SCIADDR4 => fpsc_vlo,
+ SCIADDR5 => fpsc_vlo,
+ SCIRDATA0 => open,
+ SCIRDATA1 => open,
+ SCIRDATA2 => open,
+ SCIRDATA3 => open,
+ SCIRDATA4 => open,
+ SCIRDATA5 => open,
+ SCIRDATA6 => open,
+ SCIRDATA7 => open,
+ SCIENAUX => fpsc_vlo,
+ SCISELAUX => fpsc_vlo,
+ SCIRD => fpsc_vlo,
+ SCIWSTN => fpsc_vlo,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_MACRO_RST => ffc_macro_rst,
+ FFC_QUAD_RST => ffc_quad_rst,
+ FFC_TRST => ffc_trst,
+ FF_TX_F_CLK => ff_txfullclk,
+ FF_TX_H_CLK => ff_txhalfclk,
+ FF_TX_Q_CLK => open,
+ REFCK2CORE => refck2core,
+ CIN0 => cin(0),
+ CIN1 => cin(1),
+ CIN2 => cin(2),
+ CIN3 => cin(3),
+ CIN4 => cin(4),
+ CIN5 => cin(5),
+ CIN6 => cin(6),
+ CIN7 => cin(7),
+ CIN8 => cin(8),
+ CIN9 => cin(9),
+ CIN10 => cin(10),
+ CIN11 => cin(11),
+ COUT0 => cout(0),
+ COUT1 => cout(1),
+ COUT2 => cout(2),
+ COUT3 => cout(3),
+ COUT4 => cout(4),
+ COUT5 => cout(5),
+ COUT6 => cout(6),
+ COUT7 => cout(7),
+ COUT8 => cout(8),
+ COUT9 => cout(9),
+ COUT10 => cout(10),
+ COUT11 => cout(11),
+ COUT12 => cout(12),
+ COUT13 => cout(13),
+ COUT14 => cout(14),
+ COUT15 => cout(15),
+ COUT16 => cout(16),
+ COUT17 => cout(17),
+ COUT18 => cout(18),
+ COUT19 => cout(19),
+ FFS_PLOL => ffs_plol);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+
+end pcs_for_ecp2m_arch ;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+
+
+entity rich is
+ port(
+ CLK40M : in std_logic;
+ CLK100M_P : in std_logic;
+ CLK100M_N : in std_logic;
+ FPGA_LED : out std_logic_vector(4 downto 0);
+ SD_RXD_P : in std_logic;
+ SD_RXD_N : in std_logic;
+ SD_TXD_P : out std_logic;
+ SD_TXD_N : out std_logic;
+ SD_MD : inout std_logic_vector(2 downto 0);
+ SD_TXDIS : out std_logic;
+ SD_LOS : in std_logic;
+ SD_TXFAULT : out std_logic;
+ SD_RATE : out std_logic;
+ ONEWIRE : inout std_logic;
+ FPGA_EXP : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture rich of rich is
+
+ component pcs_for_ecp2m
+ port(
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp2 : in std_logic;
+ hdinn2 : in std_logic;
+ ff_rxiclk_ch2 : in std_logic;
+ ff_txiclk_ch2 : in std_logic;
+ ff_ebrd_clk_2 : in std_logic;
+ ff_txdata_ch2 : in std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0);
+ ff_force_disp_ch2 : in std_logic_vector(1 downto 0);
+ ff_disp_sel_ch2 : in std_logic_vector(1 downto 0);
+ ff_correct_disp_ch2 : in std_logic_vector(1 downto 0);
+ ffc_rrst_ch2 : in std_logic;
+ ffc_signal_detect_ch2 : in std_logic;
+ ffc_enable_cgalign_ch2 : in std_logic;
+ ffc_lane_tx_rst_ch2 : in std_logic;
+ ffc_lane_rx_rst_ch2 : in std_logic;
+ ffc_txpwdnb_ch2 : in std_logic;
+ ffc_rxpwdnb_ch2 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp2 : out std_logic;
+ hdoutn2 : out std_logic;
+ ff_rxdata_ch2 : out std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch2 : out std_logic;
+ ff_rxhalfclk_ch2 : out std_logic;
+ ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch2 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch2 : OUT std_logic;
+ ffs_rlol_ch2 : OUT std_logic;
+ oob_out_ch2 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ END COMPONENT;
+
+ component flexi_PCS_channel_synch
+ port (
+ SYSTEM_CLK : in std_logic;
+ TX_CLK : in std_logic;
+ RX_CLK : in std_logic;
+ RESET : in std_logic;
+ RXD : in std_logic_vector(15 downto 0);
+ RXD_SYNCH : out std_logic_vector(15 downto 0);
+ RX_K : in std_logic_vector(1 downto 0);
+ RX_RST : out std_logic;
+ CV : in std_logic_vector(1 downto 0);
+ TXD : in std_logic_vector(15 downto 0);
+ TXD_SYNCH : out std_logic_vector(15 downto 0);
+ TX_K : out std_logic_vector(1 downto 0);
+ DATA_VALID_IN : in std_logic;
+ DATA_VALID_OUT : out std_logic;
+ FLEXI_PCS_STATUS : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(2 downto 0);
+ MED_READ_IN : in std_logic);
+ end component;
+
+ component flexi_PCS_synch
+ generic (
+ HOW_MANY_CHANNELS : positive);
+ port (
+ SYSTEM_CLK : in std_logic;
+ CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
+ RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ RESET : in std_logic;
+ RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+ TX_K : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0);
+ MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
+ MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
+ MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
+ );
+ end component;
+
+ component DCS
+-- synthesis translate_off
+ --sim
+ generic (
+ DCSMODE : string := "POS");
+-- synthesis translate_on
+ port (
+ CLK0 : in std_logic;
+ CLK1 : in std_logic;
+ SEL : in std_logic;
+ DCSOUT : out std_logic);
+ end component;
+
+ component link_test
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ VALID_IN : in std_logic;
+ VALID_OUT : out std_logic;
+ LINK_DEBUG : out std_logic_vector(31 downto 0);
+ LINK_INFO : in std_logic_vector(15 downto 0));
+ end component;
+
+ signal core_txrefclk_i : std_logic;
+ signal core_rxrefclk_i : std_logic;
+ signal hdinp2_i : std_logic;
+ signal hdinn2_i : std_logic;
+ signal ff_rxiclk_ch2_i : std_logic;
+ signal ff_txiclk_ch2_i : std_logic;
+ signal ff_ebrd_clk_2_i : std_logic;
+ signal ff_txdata_ch2_i : std_logic_vector(15 downto 0);
+ signal ff_tx_k_cntrl_ch2_i : std_logic_vector(1 downto 0);
+ signal ff_force_disp_ch2_i : std_logic_vector(1 downto 0);
+ signal ff_disp_sel_ch2_i : std_logic_vector(1 downto 0);
+ signal ff_correct_disp_ch2_i : std_logic_vector(1 downto 0);
+ signal ffc_rrst_ch2_i : std_logic;
+ signal ffc_signal_detect_ch2_i : std_logic;
+ signal ffc_enable_cgalign_ch2_i : std_logic;
+ signal ffc_lane_tx_rst_ch2_i : std_logic;
+ signal ffc_lane_rx_rst_ch2_i : std_logic;
+ signal ffc_txpwdnb_ch2_i : std_logic;
+ signal ffc_rxpwdnb_ch2_i : std_logic;
+ signal ffc_macro_rst_i : std_logic;
+ signal ffc_quad_rst_i : std_logic;
+ signal ffc_trst_i : std_logic;
+ signal hdoutp2_i : std_logic;
+ signal hdoutn2_i : std_logic;
+ signal ff_rxdata_ch2_i : std_logic_vector(15 downto 0);
+ signal ff_rx_k_cntrl_ch2_i : std_logic_vector(1 downto 0);
+ signal ff_rxfullclk_ch2_i : std_logic;
+ signal ff_rxhalfclk_ch2_i : std_logic;
+ signal ff_disp_err_ch2_i : std_logic_vector(1 downto 0);
+ signal ff_cv_ch2_i : std_logic_vector(1 downto 0);
+ signal ffs_rlos_lo_ch2_i : std_logic;
+ signal ffs_rlol_ch2_i : std_logic;
+ signal oob_out_ch2_i : std_logic;
+ signal ff_txfullclk_i : std_logic;
+ signal ff_txhalfclk_i : std_logic;
+ signal refck2core_i : std_logic;
+ signal ffs_plol_i : std_logic;
+ -- reset
+ signal global_reset_cnt : std_logic_vector(3 downto 0);
+ signal global_reset_i : std_logic:='0';
+ signal counter : std_logic_vector(31 downto 0);
+ -- dcs_clock
+ signal dcs_clk_out : std_logic;
+ signal not_lock : std_logic;
+ --synch
+ signal data_valid_out_i : std_logic;
+ signal flexi_PCS_status_i : std_logic_vector(15 downto 0);
+ signal ffc_lane_rx_rst_ch2_start : std_logic;
+ signal ffc_lane_rx_rst_ch2_resync : std_logic;
+ --test
+ signal data_out_i : std_logic_vector(15 downto 0);
+ signal data_in_i : std_logic_vector(15 downto 0);
+ signal data_valid_in_i : std_logic;
+ signal test_link_debug : std_logic_vector(31 downto 0);
+ signal test_link_info : std_logic_vector(15 downto 0);
+begin -- rich
+ RESET_COUNTER_a : process (CLK40M)
+ begin
+ if rising_edge(CLK40M) then
+ if counter < x"0ffffffe" then
+ counter <= counter +1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+ end process RESET_COUNTER_a;
+
+ ffc_quad_rst_i <= '1' when (counter > x"0000ffff" and counter < x"0001000f") else '0';
+ ffc_lane_tx_rst_ch2_i <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0';
+ ffc_lane_rx_rst_ch2_start <= '1' when (counter > x"00ffffff" and counter < x"0f00000f") else '0';
+
+ REF_CLK_SELECT: DCS
+ -- synthesis translate_off
+
+ generic map (--no_sim--
+ DCSMODE => "POS")--no_sim--
+ -- synthesis translate_on
+ port map (
+ CLK0 => ff_rxhalfclk_ch2_i,
+ CLK1 => CLK40M,
+ SEL => ffs_rlol_ch2_i,--hub_register_0a_i(0),--'0',--switch_rx_clk,
+ DCSOUT => dcs_clk_out);
+
+ serdes : pcs_for_ecp2m port map(
+ core_txrefclk => CLK40M,
+ core_rxrefclk => dcs_clk_out,--CLK40M,--ff_rxhalfclk_ch2_i,
+ hdinp2 => SD_RXD_P,
+ hdinn2 => SD_RXD_N,
+ hdoutp2 => SD_TXD_P,
+ hdoutn2 => SD_TXD_N,
+ ff_rxiclk_ch2 => ff_rxhalfclk_ch2_i,
+ ff_txiclk_ch2 => ff_txhalfclk_i,
+ ff_ebrd_clk_2 => open,--ff_ebrd_clk_2_i,
+ ff_txdata_ch2 => ff_txdata_ch2_i,
+ ff_rxdata_ch2 => ff_rxdata_ch2_i,
+ ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2_i,
+ ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2_i,
+ ff_rxfullclk_ch2 => ff_rxfullclk_ch2_i,
+ ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2_i,
+ ff_force_disp_ch2 => "00",--ff_force_disp_ch2_i,
+ ff_disp_sel_ch2 => "00",--ff_disp_sel_ch2_i,
+ ff_correct_disp_ch2 => ff_correct_disp_ch2_i,
+ ff_disp_err_ch2 => ff_disp_err_ch2_i,
+ ff_cv_ch2 => ff_cv_ch2_i,
+ ffc_rrst_ch2 => '0',--ffc_rrst_ch2_i,
+ ffc_signal_detect_ch2 => '1',--ffc_signal_detect_ch2_i,
+ ffc_enable_cgalign_ch2 => '1',--ffc_enable_cgalign_ch2_i,
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2_i,
+ ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2_i,
+ ffc_txpwdnb_ch2 => '1',--ffc_txpwdnb_ch2_i,
+ ffc_rxpwdnb_ch2 => '1',--ffc_rxpwdnb_ch2_i,
+ ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2_i,
+ ffs_rlol_ch2 => ffs_rlol_ch2_i,
+ oob_out_ch2 => oob_out_ch2_i,
+ ffc_macro_rst => '0',--ffc_macro_rst_i,
+ ffc_quad_rst => global_reset_i,--ffc_quad_rst_i,
+ ffc_trst => '0',--ffc_trst_i,
+ ff_txfullclk => ff_txfullclk_i,
+ ff_txhalfclk => ff_txhalfclk_i,
+ refck2core => refck2core_i,
+ ffs_plol => ffs_plol_i
+ );
+ ffc_lane_rx_rst_ch2_i <= ffc_lane_rx_rst_ch2_resync or ffc_lane_rx_rst_ch2_start;
+
+ SYNCH: flexi_PCS_channel_synch
+ port map (
+ SYSTEM_CLK => CLK40M,
+ TX_CLK => ff_txhalfclk_i,
+ RX_CLK => ff_rxhalfclk_ch2_i,
+ RESET => global_reset_i,
+ RXD => ff_rxdata_ch2_i,
+ RXD_SYNCH => data_in_i,
+ RX_K => ff_rx_k_cntrl_ch2_i,
+ RX_RST => ffc_lane_rx_rst_ch2_resync,
+ CV => ff_cv_ch2_i,
+ TXD => data_out_i,
+ TXD_SYNCH => ff_txdata_ch2_i,
+ TX_K => ff_tx_k_cntrl_ch2_i,
+ DATA_VALID_IN => data_valid_in_i,
+ DATA_VALID_OUT => data_valid_out_i,
+ FLEXI_PCS_STATUS => flexi_pcs_status_i,
+ MED_PACKET_NUM_OUT => open,
+ MED_ERROR_OUT => open,
+ MED_READ_IN => '1');
+
+ test_link_info(2 downto 0) <= ff_cv_ch2_i & flexi_pcs_status_i(2);
+
+ LINK_TETS_INST: link_test
+ port map (
+ CLK => CLK40M,
+ RESET => global_reset_i,
+ DATA_IN => data_in_i,
+ DATA_OUT => data_out_i,
+ VALID_IN => data_valid_out_i,
+ VALID_OUT => data_valid_in_i,
+ LINK_DEBUG => test_link_debug,
+ LINK_INFO => test_link_info);
+
+
+
+ GLOBAL_RESET: process(CLK40M,global_reset_cnt,global_reset_i)
+ begin
+ if rising_edge(CLK40M) then
+ if global_reset_cnt < x"e" or global_reset_cnt =x"f" then
+ global_reset_cnt <= global_reset_cnt + 1;
+ global_reset_i <= '1';
+ elsif global_reset_cnt = x"e" then
+ global_reset_i <= '0';
+ global_reset_cnt <= x"e";
+ else
+ global_reset_i <= '0';
+ global_reset_cnt <= global_reset_cnt;
+ end if;
+ end if;
+ end process GLOBAL_RESET;
+
+-- ff_tx_k_cntrl_ch2_i <= "10";
+-- ff_txdata_ch2_i <= x"bcc5";
+ FPGA_LED(4 downto 1) <= "1010";
+ FPGA_LED(0) <= not flexi_pcs_status_i(2);
+
+ FPGA_EXP <= test_link_debug(15 downto 0);
+
+-- FPGA_EXP(0) <= CLK40M;
+-- FPGA_EXP(1) <= ff_rxhalfclk_ch2_i;
+-- FPGA_EXP(2) <= dcs_clk_out;
+-- FPGA_EXP(3) <= ff_cv_ch2_i(0);
+-- FPGA_EXP(4) <= ff_cv_ch2_i(1);
+-- FPGA_EXP(5) <= ff_rx_k_cntrl_ch2_i(0);
+-- FPGA_EXP(6) <= ff_rx_k_cntrl_ch2_i(1);
+-- FPGA_EXP(7) <= ff_disp_err_ch2_i(0);
+-- FPGA_EXP(8) <= ff_disp_err_ch2_i(1);
+-- FPGA_EXP(9) <= ffs_rlos_lo_ch2_i;
+-- FPGA_EXP(10)<= ffs_rlol_ch2_i;
+-- FPGA_EXP(11)<= global_reset_i;
+-- FPGA_EXP(12)<= ffs_plol_i;
+-- FPGA_EXP(13) <= not flexi_pcs_status_i(2);
+-- FPGA_EXP(14) <= ffc_lane_rx_rst_ch2_i;
+
+end rich;
--- /dev/null
+
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCS quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCS quad to the final design requirements.
+# channel_0 is in "8b10b" mode
+# channel_1 is in "8b10b" mode
+# channel_2 is in "8b10b" mode
+# channel_3 is in "8b10b" mode
+
+ch0 13 03 # Powerup Channel
+ch0 00 00
+ch1 13 03 # Powerup Channel
+ch1 00 00
+ch2 13 03 # Powerup Channel
+ch2 00 00
+ch3 13 03 # Powerup Channel
+ch3 00 00
+quad 00 00
+quad 01 E4
+quad 28 40 # Reference clock multiplier
+quad 29 11 # FPGA sourced refclk
+quad 02 00 # ref_pclk source is ch0
+quad 04 00 # MCA enable 4 channels
+
+quad 18 10 # 8b10b Mode
+quad 14 FF # Word Alignment Mask
+quad 15 7c # +ve K
+quad 16 b6 # -ve K
+quad 17 36
+
+quad 19 8C # Enable word_align_en port, FPGA bus width is 16-bit/20-bit
+
+#quad 1e 01 #SOP EOP only 1 word 24.04.2008
+#quad 1f ff
+#quad 20 7c
+#quad 21 7c
+#quad 22 5
+#quad 23 7c
+#quad 24 7c
+#quad 25 5
+
+
+ch0 14 90 # 16% pre-emphasis
+ch0 15 10 # +6dB equalization
+ch1 14 90 # 16% pre-emphasis
+ch1 15 10 # +6dB equalization
+ch2 14 90 # 16% pre-emphasis
+ch2 15 10 # +6dB equalization
+ch3 14 90 # 16% pre-emphasis
+ch3 15 10 # +6dB equalization
+
+# These lines must appear last in the autoconfig file. These lines apply the correct
+# reset sequence to the PCS block upon bitstream configuration
+quad 41 00 # de-assert serdes_rst
+quad 40 ff # assert datapath reset for all channels
+quad 40 00 # de-assert datapath reset for all channels
+
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity up_down_counter is
+
+ generic (
+ NUMBER_OF_BITS : positive
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic
+ );
+
+end up_down_counter;
+
+architecture up_down_counter of up_down_counter is
+
+signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0);
+
+begin
+
+ COUNTER_PROC : process (CLK, RESET, UP_IN, DOWN_IN)
+ begin
+ if rising_edge(clk) then
+ if RESET = '1' then
+ counter <= (others => '0');
+ elsif UP_IN = '1' and DOWN_IN = '0' then
+ counter <= counter + 1;
+ elsif UP_IN = '0' and DOWN_IN = '1' then
+ counter <= counter - 1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+ end process COUNTER_PROC;
+
+ COUNT_OUT <= counter;
+
+end up_down_counter;
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