###########################################################
##Relax some timing constraints
###########################################################
-MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
+#MULTICYCLE FROM CELL "MuPix3_Board_*/board_interface_1/hbus_from_mupix_sync" TO CELL "MuPix3_Board_*/HitbusHistogram_1/hitbus_buffer" 2 X;
signal sensor_id : std_logic_vector(31 downto 0) := (others => '0');
signal triggering : std_logic := '0';
- signal busy_r : std_logic := '0';
signal continousread : std_logic := '0';
signal readnow : std_logic := '0';
signal readmanual : std_logic := '0';
-----------------------------------------------------------------------------
--Readout Control
-----------------------------------------------------------------------------
-
- process(rst, clk)
+ process(clk)
begin
if rising_edge(clk) then
if(rst = '1') then
-----------------------------------------------------------------------------
--MuPix 3/4/6 Readout Statemachine
-----------------------------------------------------------------------------
- ro_statemachine : process(rst, clk)
+ ro_statemachine : process(clk)
begin
if rising_edge(clk) then
if(rst = '1') then
delcounter <= "00000100";
eventcounter <= eventcounter + 1;
end if;
- when others =>
- testoutro(8) <= '1';
- state <= waiting;
end case;
end if;
end if;
end process;
- tsgen :
- process(rst, clk)
- begin
- if(rst = '1') then
- mupixcontrol.timestamps <= (others => '0');
- elsif(clk'event and clk = '1') then
- if(timestampcontrolbits(8) = '1') then
- mupixcontrol.timestamps <= graycount;
- else
- mupixcontrol.timestamps <= timestampcontrolbits(7 downto 0);
- end if;
- end if;
- end process;
+ tsgen : process(clk)
+ begin
+ if rising_edge(clk) then
+ if (rst = '1') then
+ mupixcontrol.timestamps <= (others => '0');
+ else
+ if (timestampcontrolbits(8) = '1') then
+ mupixcontrol.timestamps <= graycount;
+ else
+ mupixcontrol.timestamps <= timestampcontrolbits(7 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
resetgraycounter <= timestampreset_in or timestampcontrolbits(9);
signal timing_trigger_int : std_logic := '0';
signal timing_trigger_edge : std_logic_vector(1 downto 0) := "00";
signal status_trigger_int : std_logic := '0';
- signal calibration_trigger_int : std_logic := '0';
signal fast_clear_int : std_logic := '0';
signal flush_buffer_int : std_logic := '0';
signal trigger_busy_int : std_logic := '0';
signal fee_trg_release_int : std_logic := '0';
signal fee_trg_statusbit_int : std_logic_vector(31 downto 0) := (others => '0');
--event buffer
- signal fast_clear_o : std_logic := '0';
--registers
signal reset_trigger_counters : std_logic := '0';