+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
-Post processing for ecp5um.extrefb.syn_black_box
-Post processing for work.extref.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
+++ /dev/null
-./synlog/extref_compiler.srr,extref_compiler.srr,Compile Log
+++ /dev/null
-# Mon May 13 09:10:16 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Mon May 13 09:10:18 2019
-#
-
-
-Top view: extref
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: NA
-
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 NA NA system system_clkgroup
-===============================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------
-========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EXTREFB: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Mon May 13 09:10:18 2019
-
-###########################################################]
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:15 2019
-
-###########################################################]
+++ /dev/null
-# Mon May 13 09:10:15 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist extref
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------
-=========================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Mon May 13 09:10:16 2019
-
-###########################################################]
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>7</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:01s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557731414</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>0</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>0</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>0 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>7</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>1</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Peak Memory">
-<data>146MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557731418</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>NA</data>
-<data>NA</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>2</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>142MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557731416</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-./extref_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-@P: Worst Slack : NA
-@P: System - Estimated Frequency : NA
-@P: System - Requested Frequency : 100.0 MHz
-@P: System - Estimated Period : NA
-@P: System - Requested Period : 10.000
-@P: System - Slack : NA
-@P: Total Area : 0.0
-@P: CPU Time : 0h:00m:02s
+++ /dev/null
-<html><body><samp><pre>
-<!@TC:1557731413>
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux
-#Hostname: lxhadeb07
-
-# Mon May 13 09:10:13 2019
-
-#Implementation: syn_results
-
-<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557731414> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557731414> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557731414> | Setting time resolution to ps
-@N: : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:18:7:18:13:@N::@XP_MSG">extref.vhd(18)</a><!@TM:1557731414> | Top entity is set to extref.
-VHDL syntax check successful!
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:18:7:18:13:@N:CD630:@XP_MSG">extref.vhd(18)</a><!@TM:1557731414> | Synthesizing work.extref.v1.
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:2147:10:2147:17:@N:CD630:@XP_MSG">ecp5um.vhd(2147)</a><!@TM:1557731414> | Synthesizing ecp5um.extrefb.syn_black_box.
-Post processing for ecp5um.extrefb.syn_black_box
-Post processing for work.extref.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557731414> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:14 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557731413>
-<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557731415> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:10:15 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557731413>
-Pre-mapping Report
-
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557731413>
-# Mon May 13 09:10:15 2019
-
-<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-Linked File: <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt:@XP_FILE">extref_scck.rpt</a>
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731416> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731416> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist extref
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-
-<a name=mapperReport6></a>Clock Summary</a>
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------
-=========================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Mon May 13 09:10:16 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557731413>
-Map & Optimize Report
-
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557731413>
-# Mon May 13 09:10:16 2019
-
-<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731418> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731418> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557731418> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557731418> | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
-M-2017.03L-SP1-1
-@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557731418> | Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:31:4:31:16:@W:MT246:@XP_MSG">extref.vhd(31)</a><!@TM:1557731418> | Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
-
-
-<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
-# Timing Report written on Mon May 13 09:10:18 2019
-#
-
-
-Top view: extref
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
-
-@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557731418> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557731418> | Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-<a name=performanceSummary10></a>Performance Summary</a>
-*******************
-
-
-Worst slack in design: NA
-
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 NA NA system system_clkgroup
-===============================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-<a name=clockRelationships11></a>Clock Relationships</a>
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------
-========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-<a name=interfaceInfo12></a>Interface Information </a>
-*********************
-
-No IO constraint found
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
----------------------------------------
-<a name=resourceUsage13></a>Resource Usage Report</a>
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EXTREFB: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Mon May 13 09:10:18 2019
-
-###########################################################]
-
-</pre></samp></body></html>
+++ /dev/null
- <html>
- <head>
- <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
- <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />
- </head>
-
- <body style="background-color:#e0e0ff;">
- <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
- <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
- <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">extref (syn_results)</b>
- <ul rel="open" style="font-size:small;">
-
-<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
-<ul rel="open">
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#resourceUsage13" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt" target="srrFrame" title="">Constraint Checker Report (09:10 13-May)</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/stdout.log" target="srrFrame" title="">Session Log (09:10 13-May)</a>
-<ul ></ul></li> </ul>
- </li>
- </ul>
-
- <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
-
- </body>
- </html>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>
-<!--
- Synopsys, Inc.
- Version M-2017.03L-SP1-1
- Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml
- Written on Mon May 13 09:10:13 2019
-
-
--->
-<project_attribute_list name="Project Settings">
- <option name="project_name" display_name="Project Name">extref</option>
- <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
- <option name="impl_name" display_name="Implementation Name">syn_results</option>
- <option name="top_module" display_name="Top Module">extref</option>
- <option name="pipe" display_name="Pipelining">0</option>
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- <option name="resource_sharing" display_name="Resource Sharing">1</option>
- <option name="maxfan" display_name="Fanout Guide">50</option>
- <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
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- <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
- <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
-</project_attribute_list>
-
+++ /dev/null
-<html>
- <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
- <title>Project Status Summary Page</title>
- <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
- <script type = "text/javascript" src="projectstatuspage.js"></script>
- </head>
-
- <body style="background-color:#f0f0ff;">
-
-<table style="border:none;" width="100%" ><tr> <td class="outline">
-<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
- <tr> <td class="optionTitle" align="left"> Project Name</td> <td> extref</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
-<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> extref</td> </tr>
- </thead>
- <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
-<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
-
-</tbody>
- </table><br> <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
- <tbody>
- <tr>
- <th align="left" width="17%">Job Name</th>
- <th align="left">Status</th>
- <td class="lnote" align="center" title="Notes"></td>
- <td class="lwarn" align="center" title="Warnings"></td>
- <td class="lerror" align="center" title="Errors"></td>
- <th align="left">CPU Time</th>
- <th align="left">Real Time</th>
- <th align="left">Memory</th>
- <th align="left">Date/Time</th>
- </tr>
- <tr>
- <td class="optionTitle"> (compiler)</td><td>Complete</td>
- <td>7</td>
-<td>0</td>
-<td>0</td>
-<td>-</td>
-<td>00m:01s</td>
-<td>-</td>
-<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (premap)</td><td>Complete</td>
- <td>2</td>
-<td>0</td>
-<td>0</td>
-<td>0m:00s</td>
-<td>0m:00s</td>
-<td>142MB</td>
-<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
- <td>7</td>
- <td>1</td>
-<td>0</td>
-<td>0m:02s</td>
-<td>0m:02s</td>
-<td>146MB</td>
-<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
-</tr>
-
-<tr>
- <td class="optionTitle">Multi-srs Generator</td>
- <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td> </tbody>
- </table>
- <br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
- </tfoot>
- <tbody> <tr>
-<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
-<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
-(v_ram)</td> <td>0</td>
-<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
-(dsp_used)</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
-(total_luts)</td> <td>0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr>
- </tfoot>
-<tbody>
- <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
-<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
-</tbody>
- </table>
-<br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Optimizations Summary</th></tr></thead>
- <tbody> <tr>
-<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
-<br>
-</td></tr></table></body>
- </html>
\ No newline at end of file
+++ /dev/null
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work extref 0
-arch work extref v1 0
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work extref v1 0
-module work extref 0
-
-
-# Configuration files used
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work extref v1 0
-module work extref 0
+++ /dev/null
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
-Post processing for ecp5um.extrefb.syn_black_box
-Post processing for work.extref.v1
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>15</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>76</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:02s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557731345</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>221</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>154</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>3 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>22</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>4</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Peak Memory">
-<data>153MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557731351</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>sgmii_ecp5|pll_refclki</data>
-<data>100.0 MHz</data>
-<data>168.9 MHz</data>
-<data>4.079</data>
-</row>
-<row>
-<data>sgmii_ecp5|rxrefclk</data>
-<data>100.0 MHz</data>
-<data>167.9 MHz</data>
-<data>4.043</data>
-</row>
-<row>
-<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
-<data>100.0 MHz</data>
-<data>237.5 MHz</data>
-<data>5.789</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>840.7 MHz</data>
-<data>8.810</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>9</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>3</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>144MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557731347</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-VHDL syntax check successful!
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Mon May 13 09:09:04 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Mon May 13 09:09:04 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-Post processing for work.sgmii_ecp5.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Mon May 13 09:09:04 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-
- PDATA_RST_VAL=32'b00000000000000000000000000000000
- Generated name = sync_0s
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-
- PPROTOCOL=24'b010001110100001001000101
- PLOL_SETTING=32'b00000000000000000000000000000000
- PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
- PPCIE_MAX_RATE=24'b001100100010111000110101
- PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
- PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
- PPCLK_TC=32'b00000000000000100000000000000000
- PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
- PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
- PPCLK_DIV11_TC=32'b00000000000000000000000000000000
- LPLL_LOSS_ST=2'b00
- LPLL_PRELOSS_ST=2'b01
- LPLL_PRELOCK_ST=2'b10
- LPLL_LOCK_ST=2'b11
- LRCLK_TC=16'b1111111111111111
- LRCLK_TC_PUL_WIDTH=16'b0000000000110010
- LHB_WAIT_CNT=8'b11111111
- LPCLK_TC_0=32'b00000000000000001000000000000000
- LPCLK_TC_1=32'b00000000000000010000000000000000
- LPCLK_TC_2=32'b00000000000000100000000000000000
- LPCLK_TC_3=32'b00000000000000101000000000000000
- LPCLK_TC_4=32'b00000000000000010000000000000000
- LPDIFF_LOCK_00=32'b00000000000000000000000000001001
- LPDIFF_LOCK_10=32'b00000000000000000000000000010011
- LPDIFF_LOCK_20=32'b00000000000000000000000000100111
- LPDIFF_LOCK_30=32'b00000000000000000000000000110001
- LPDIFF_LOCK_40=32'b00000000000000000000000000010011
- LPDIFF_LOCK_01=32'b00000000000000000000000000001001
- LPDIFF_LOCK_11=32'b00000000000000000000000000010011
- LPDIFF_LOCK_21=32'b00000000000000000000000000100111
- LPDIFF_LOCK_31=32'b00000000000000000000000000110001
- LPDIFF_LOCK_41=32'b00000000000000000000000000010011
- LPDIFF_LOCK_02=32'b00000000000000000000000000110001
- LPDIFF_LOCK_12=32'b00000000000000000000000001100010
- LPDIFF_LOCK_22=32'b00000000000000000000000011000100
- LPDIFF_LOCK_32=32'b00000000000000000000000011110101
- LPDIFF_LOCK_42=32'b00000000000000000000000001100010
- LPDIFF_LOCK_03=32'b00000000000000000000000010000011
- LPDIFF_LOCK_13=32'b00000000000000000000000100000110
- LPDIFF_LOCK_23=32'b00000000000000000000001000001100
- LPDIFF_LOCK_33=32'b00000000000000000000001010001111
- LPDIFF_LOCK_43=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
- LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
- LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
- LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
- LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
- LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
- LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
- LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
- LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
- LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
- LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
- LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
- LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
- Generated name = sgmii_ecp5sll_core_Z1_layer1
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = sgmii_ecp5rsl_core_Z2_layer1
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-Extracted state machine for register sll_state
-State machine has 4 reachable states with original encodings of:
- 00
- 01
- 10
- 11
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
-
-
-Process completed successfully.
-# Mon May 13 09:09:05 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:09:05 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:09:05 2019
-
-###########################################################]
+++ /dev/null
-./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log
+++ /dev/null
-# Mon May 13 09:09:07 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:01s 4.90ns 155 / 221
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-============================================= Non-Gated/Non-Generated Clocks =============================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------------------------------------
-@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
-@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
-@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21]
-==========================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Mon May 13 09:09:11 2019
-#
-
-
-Top view: sgmii_ecp5
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.043
-
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------------------------
-sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1
-sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2
-System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup
-========================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths -
-============================================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-====================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-=======================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
- The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[2] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043
-rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170
-rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-===================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104
-rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165
-rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-=================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.902
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.043
-
- Number of logic level(s): 11
- Starting point: rsl_inst.genblk2\.rxs_rst / Q
- Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
- The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 -
-rxs_rst Net - - - - 6
-rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 -
-rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 -
-rsl_rx_serdes_rst_c Net - - - - 3
-rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 -
-rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 -
-dual_or_rserd_rst Net - - - - 9
-rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 -
-rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 -
-rx_any_rst Net - - - - 2
-rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 -
-rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 -
-rxr_wt_cnt9 Net - - - - 14
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 -
-rxr_wt_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 -
-rxr_wt_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 -
-rxr_wt_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 -
-rxr_wt_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 -
-rxr_wt_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 -
-rxr_wt_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 -
-rxr_wt_cnt_s[11] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 -
-=================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789
-sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789
-sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147
-sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178
-sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239
-sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239
-sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287
-sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287
-sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300
-sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300
-========================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------------------------
-sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789
-sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850
-sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850
-sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911
-sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911
-sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972
-sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972
-sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033
-sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033
-sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034
-=========================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 4.157
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 5.789
-
- Number of logic level(s): 13
- Starting point: sll_inst.ppul_sync_p1 / Q
- Ending point: sll_inst.pcount[21] / D
- The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
- The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 -
-ppul_sync_p1 Net - - - - 25
-sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 -
-sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 -
-N_8 Net - - - - 25
-sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 -
-sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 -
-pcount_cry[0] Net - - - - 1
-sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 -
-sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 -
-pcount_cry[2] Net - - - - 1
-sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 -
-sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 -
-pcount_cry[4] Net - - - - 1
-sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 -
-sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 -
-pcount_cry[6] Net - - - - 1
-sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 -
-sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 -
-pcount_cry[8] Net - - - - 1
-sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 -
-sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 -
-pcount_cry[10] Net - - - - 1
-sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 -
-sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 -
-pcount_cry[12] Net - - - - 1
-sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 -
-sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 -
-pcount_cry[14] Net - - - - 1
-sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 -
-sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 -
-pcount_cry[16] Net - - - - 1
-sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 -
-sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 -
-pcount_cry[18] Net - - - - 1
-sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 -
-sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 -
-pcount_cry[20] Net - - - - 1
-sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 -
-sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 -
-pcount_s[21] Net - - - - 1
-sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 -
-============================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-----------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-=============================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.194
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.806
-
- - Propagation time: 0.996
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 8.810
-
- Number of logic level(s): 2
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
- The start point is clocked by System [rising]
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 4
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 -
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 -
-un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 -
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 -
-un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 -
-===================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 221 of 24288 (1%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 113
-DCUA: 1
-FD1P3BX: 20
-FD1P3DX: 92
-FD1S3BX: 12
-FD1S3DX: 97
-GSR: 1
-INV: 3
-ORCALUT4: 154
-PFUMX: 2
-PUR: 1
-VHI: 6
-VLO: 6
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Mon May 13 09:09:11 2019
-
-###########################################################]
+++ /dev/null
-CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
-CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002
-CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Mon May 13 09:09:06 2019
-
-###########################################################]
+++ /dev/null
-# Mon May 13 09:09:07 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
-@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93
-
-0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77
-
-0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53
-======================================================================================================================
-
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Mon May 13 09:09:07 2019
-
-###########################################################]
+++ /dev/null
-./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info|
-|2|
+++ /dev/null
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-
-@
+++ /dev/null
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-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
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-# Design Unit to File Association
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-module work sgmii_ecp5 0
-
-# Unbound Instances to File Association
-inst work sgmii_ecp5 sgmii_ecp5sll_core 0
-inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
-inst work sgmii_ecp5 dcua 0
-
-
-# Configuration files used
+++ /dev/null
-#defaultlanguage:vhdl
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-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
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-module work sgmii_ecp5 0
-
-# Unbound Instances to File Association
-inst work sgmii_ecp5 sgmii_ecp5sll_core 0
-inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
-inst work sgmii_ecp5 dcua 0
+++ /dev/null
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-Post processing for work.sgmii_ecp5.v1
+++ /dev/null
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-#Unbound instances to file Association.
+++ /dev/null
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-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-
- PDATA_RST_VAL=32'b00000000000000000000000000000000
- Generated name = sync_0s
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-
- PPROTOCOL=24'b010001110100001001000101
- PLOL_SETTING=32'b00000000000000000000000000000000
- PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
- PPCIE_MAX_RATE=24'b001100100010111000110101
- PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
- PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
- PPCLK_TC=32'b00000000000000100000000000000000
- PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
- PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
- PPCLK_DIV11_TC=32'b00000000000000000000000000000000
- LPLL_LOSS_ST=2'b00
- LPLL_PRELOSS_ST=2'b01
- LPLL_PRELOCK_ST=2'b10
- LPLL_LOCK_ST=2'b11
- LRCLK_TC=16'b1111111111111111
- LRCLK_TC_PUL_WIDTH=16'b0000000000110010
- LHB_WAIT_CNT=8'b11111111
- LPCLK_TC_0=32'b00000000000000001000000000000000
- LPCLK_TC_1=32'b00000000000000010000000000000000
- LPCLK_TC_2=32'b00000000000000100000000000000000
- LPCLK_TC_3=32'b00000000000000101000000000000000
- LPCLK_TC_4=32'b00000000000000010000000000000000
- LPDIFF_LOCK_00=32'b00000000000000000000000000001001
- LPDIFF_LOCK_10=32'b00000000000000000000000000010011
- LPDIFF_LOCK_20=32'b00000000000000000000000000100111
- LPDIFF_LOCK_30=32'b00000000000000000000000000110001
- LPDIFF_LOCK_40=32'b00000000000000000000000000010011
- LPDIFF_LOCK_01=32'b00000000000000000000000000001001
- LPDIFF_LOCK_11=32'b00000000000000000000000000010011
- LPDIFF_LOCK_21=32'b00000000000000000000000000100111
- LPDIFF_LOCK_31=32'b00000000000000000000000000110001
- LPDIFF_LOCK_41=32'b00000000000000000000000000010011
- LPDIFF_LOCK_02=32'b00000000000000000000000000110001
- LPDIFF_LOCK_12=32'b00000000000000000000000001100010
- LPDIFF_LOCK_22=32'b00000000000000000000000011000100
- LPDIFF_LOCK_32=32'b00000000000000000000000011110101
- LPDIFF_LOCK_42=32'b00000000000000000000000001100010
- LPDIFF_LOCK_03=32'b00000000000000000000000010000011
- LPDIFF_LOCK_13=32'b00000000000000000000000100000110
- LPDIFF_LOCK_23=32'b00000000000000000000001000001100
- LPDIFF_LOCK_33=32'b00000000000000000000001010001111
- LPDIFF_LOCK_43=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
- LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
- LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
- LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
- LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
- LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
- LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
- LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
- LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
- LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
- LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
- LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
- LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
- Generated name = sgmii_ecp5sll_core_Z1_layer1
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = sgmii_ecp5rsl_core_Z2_layer1
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-Extracted state machine for register sll_state
-State machine has 4 reachable states with original encodings of:
- 00
- 01
- 10
- 11
+++ /dev/null
-#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557731344
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
-#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557731342
-0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
-1 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
-#Dependency Lists(Uses List)
-0 1
-1 -1
-#Dependency Lists(Users Of)
-0 -1
-1 0
-#Design Unit to File Association
-module work sgmii_ecp5sll_core 1
-module work sync 1
-module work sgmii_ecp5rsl_core 1
-module work sgmii_ecp5 0
-arch work sgmii_ecp5 v1 0
+++ /dev/null
- -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs -top pll_200_125_100 -hdllog /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr -encrypt -mp 4 -verification_mode 0 -vhdl -prodtype synplify_pro -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver -encrypt -pro -dmgen /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/dm -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm -ignore_undefined_lib -lib work /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd -jobname "compiler"
\ No newline at end of file
+++ /dev/null
--link -encrypt -top pll_200_125_100 -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs
\ No newline at end of file
+++ /dev/null
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+++ /dev/null
-----------------------------------------------------------------------
-Report for cell pll_200_125_100.structure
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
- Cell usage:
- cell count Res Usage(%)
- EHXPLLL 1 100.0
- GSR 1 100.0
- PUR 1 100.0
- VHI 1 100.0
- VLO 1 100.0
-
- TOTAL 5
+++ /dev/null
-<html>
- <head>
- <title>syntmp/pll_200_125_100_srr.htm log file</title>
- </head>
- <frameset cols="20%, 80%">
- <frame src="syntmp/pll_200_125_100_toc.htm" name="tocFrame" />
- <frame src="syntmp/pll_200_125_100_srr.htm" name="srrFrame"/>
-</frameset>
- </html>
+++ /dev/null
-#-- Lattice Semiconductor Corporation Ltd.
-#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj
-#-- Written on Fri May 10 14:33:10 2019
-
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM-85F
-set_option -speed_grade 8
-
-#use verilog 2001 standard option
-set_option -vlog_std v2001
-
-#map options
-set_option -frequency 100
-set_option -fanout_limit 50
-set_option -disable_io_insertion true
-set_option -retiming false
-set_option -pipe false
-set_option -pipe false
-set_option -force_gsr false
-
-#simulation options
-set_option -write_verilog true
-set_option -write_vhdl true
-
-#timing analysis options
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#-- add_file options
-add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
-add_file -constraint {"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"}
-
-#-- top module name
-set_option -top_module pll_200_125_100
-
-#-- set result format/file last
-project -result_file "pll_200_125_100.edn"
-
-#-- error message log file
-project -log_file pll_200_125_100.srf
-
-#-- run Synplify with 'arrange VHDL file'
-project -run
+++ /dev/null
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux
-#Hostname: lxhadeb07
-
-# Fri May 10 14:33:10 2019
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:12 2019
-
-###########################################################]
-Pre-mapping Report
-
-# Fri May 10 14:33:12 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 14:33:13 2019
-
-###########################################################]
-Map & Optimize Report
-
-# Fri May 10 14:33:13 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 14:33:15 2019
-#
-
-
-Top view: pll_200_125_100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000
-===================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKINTFB
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 -
-CLKFB_t Net - - - - 1
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 14:33:15 2019
-
-###########################################################]
+++ /dev/null
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux
-#Hostname: lxhadeb07
-
-# Fri May 10 14:33:10 2019
-
-#Implementation: syn_results
-
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:12 2019
-
-###########################################################]
-Pre-mapping Report
-
-# Fri May 10 14:33:12 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 14:33:13 2019
-
-###########################################################]
-Map & Optimize Report
-
-# Fri May 10 14:33:13 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 14:33:15 2019
-#
-
-
-Top view: pll_200_125_100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000
-===================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKINTFB
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 -
-CLKFB_t Net - - - - 1
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 14:33:15 2019
-
-###########################################################]
+++ /dev/null
---
--- Written by Synplicity
--- Product Version "M-2017.03L-SP1-1"
--- Program "Synplify Pro", Mapper "maplat, Build 1796R"
--- Fri May 10 14:33:15 2019
---
-
---
--- Written by Synplify Pro version Build 1796R
--- Fri May 10 14:33:15 2019
---
-
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library synplify;
-use synplify.components.all;
-library pmi;
-use pmi.pmi_components.all;
-library ecp5um;
-use ecp5um.components.all;
-
-entity pll_200_125_100 is
-port(
- CLKI : in std_logic;
- CLKOP : out std_logic;
- CLKOS : out std_logic;
- CLKOS2 : out std_logic;
- LOCK : out std_logic);
-end pll_200_125_100;
-
-architecture beh of pll_200_125_100 is
- signal CLKOS3 : std_logic ;
- signal INTLOCK : std_logic ;
- signal CLKFB_T : std_logic ;
- signal REFCLK : std_logic ;
- signal GND : std_logic ;
- signal VCC : std_logic ;
-begin
-GND_0: VLO port map (
- Z => GND);
-VCC_0: VHI port map (
- Z => VCC);
-PUR_INST: PUR port map (
- PUR => VCC);
-GSR_INST: GSR port map (
- GSR => VCC);
-PLLINST_0: EHXPLLL
- generic map(
- CLKI_DIV => 2,
- CLKFB_DIV => 1,
- CLKOP_DIV => 1,
- CLKOS_DIV => 5,
- CLKOS2_DIV => 4,
- CLKOS3_DIV => 1,
- CLKOP_ENABLE => "ENABLED",
- CLKOS_ENABLE => "ENABLED",
- CLKOS2_ENABLE => "ENABLED",
- CLKOS3_ENABLE => "DISABLED",
- CLKOP_CPHASE => 0,
- CLKOS_CPHASE => 4,
- CLKOS2_CPHASE => 3,
- CLKOS3_CPHASE => 0,
- CLKOP_FPHASE => 0,
- CLKOS_FPHASE => 0,
- CLKOS2_FPHASE => 0,
- CLKOS3_FPHASE => 0,
- FEEDBK_PATH => "INT_OS",
- CLKOP_TRIM_POL => "FALLING",
- CLKOP_TRIM_DELAY => 0,
- CLKOS_TRIM_POL => "FALLING",
- CLKOS_TRIM_DELAY => 0,
- OUTDIVIDER_MUXA => "REFCLK",
- OUTDIVIDER_MUXB => "DIVB",
- OUTDIVIDER_MUXC => "DIVC",
- OUTDIVIDER_MUXD => "DIVD",
- PLL_LOCK_MODE => 0,
- STDBY_ENABLE => "DISABLED",
- DPHASE_SOURCE => "DISABLED",
- PLLRST_ENA => "DISABLED",
- INTFB_WAKE => "DISABLED"
- )
- port map (
- CLKI => CLKI,
- CLKFB => CLKFB_T,
- PHASESEL1 => GND,
- PHASESEL0 => GND,
- PHASEDIR => GND,
- PHASESTEP => GND,
- PHASELOADREG => GND,
- STDBY => GND,
- PLLWAKESYNC => GND,
- RST => GND,
- ENCLKOP => GND,
- ENCLKOS => GND,
- ENCLKOS2 => GND,
- ENCLKOS3 => GND,
- CLKOP => CLKOP,
- CLKOS => CLKOS,
- CLKOS2 => CLKOS2,
- CLKOS3 => CLKOS3,
- LOCK => LOCK,
- INTLOCK => INTLOCK,
- REFCLK => REFCLK,
- CLKINTFB => CLKFB_T);
-end beh;
-
+++ /dev/null
-//
-// Written by Synplify Pro
-// Product Version "M-2017.03L-SP1-1"
-// Program "Synplify Pro", Mapper "maplat, Build 1796R"
-// Fri May 10 14:33:14 2019
-//
-// Source file index table:
-// Object locations will have the form <file>:<line>
-// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
-// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
-// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
-// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
-// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
-// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
-// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
-// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
-// file 8 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd "
-// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
-// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
-// file 11 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc "
-
-`timescale 100 ps/100 ps
-(* NGD_DRC_MASK=1 *)module pll_200_125_100 (
- CLKI,
- CLKOP,
- CLKOS,
- CLKOS2,
- LOCK
-)
-;
-input CLKI ;
-output CLKOP ;
-output CLKOS ;
-output CLKOS2 ;
-output LOCK ;
-wire CLKI ;
-wire CLKOP ;
-wire CLKOS ;
-wire CLKOS2 ;
-wire LOCK ;
-wire CLKOS3 ;
-wire INTLOCK ;
-wire CLKFB_t ;
-wire REFCLK ;
-wire GND ;
-wire VCC ;
- VLO GND_0 (
- .Z(GND)
-);
- VHI VCC_0 (
- .Z(VCC)
-);
- PUR PUR_INST (
- .PUR(VCC)
-);
- GSR GSR_INST (
- .GSR(VCC)
-);
-// @8:56
-(* LPF_RESISTOR="24" , ICP_CURRENT="13" , FREQUENCY_PIN_CLKI="200.000000" , FREQUENCY_PIN_CLKOP="200.000000" , FREQUENCY_PIN_CLKOS="100.000000" , FREQUENCY_PIN_CLKOS2="125.000000" *) EHXPLLL PLLInst_0 (
- .CLKI(CLKI),
- .CLKFB(CLKFB_t),
- .PHASESEL1(GND),
- .PHASESEL0(GND),
- .PHASEDIR(GND),
- .PHASESTEP(GND),
- .PHASELOADREG(GND),
- .STDBY(GND),
- .PLLWAKESYNC(GND),
- .RST(GND),
- .ENCLKOP(GND),
- .ENCLKOS(GND),
- .ENCLKOS2(GND),
- .ENCLKOS3(GND),
- .CLKOP(CLKOP),
- .CLKOS(CLKOS),
- .CLKOS2(CLKOS2),
- .CLKOS3(CLKOS3),
- .LOCK(LOCK),
- .INTLOCK(INTLOCK),
- .REFCLK(REFCLK),
- .CLKINTFB(CLKFB_t)
-);
-defparam PLLInst_0.CLKI_DIV = 2;
-defparam PLLInst_0.CLKFB_DIV = 1;
-defparam PLLInst_0.CLKOP_DIV = 1;
-defparam PLLInst_0.CLKOS_DIV = 5;
-defparam PLLInst_0.CLKOS2_DIV = 4;
-defparam PLLInst_0.CLKOS3_DIV = 1;
-defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
-defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
-defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED";
-defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
-defparam PLLInst_0.CLKOP_CPHASE = 0;
-defparam PLLInst_0.CLKOS_CPHASE = 4;
-defparam PLLInst_0.CLKOS2_CPHASE = 3;
-defparam PLLInst_0.CLKOS3_CPHASE = 0;
-defparam PLLInst_0.CLKOP_FPHASE = 0;
-defparam PLLInst_0.CLKOS_FPHASE = 0;
-defparam PLLInst_0.CLKOS2_FPHASE = 0;
-defparam PLLInst_0.CLKOS3_FPHASE = 0;
-defparam PLLInst_0.FEEDBK_PATH = "INT_OS";
-defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
-defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
-defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
-defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
-defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK";
-defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
-defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC";
-defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
-defparam PLLInst_0.PLL_LOCK_MODE = 0;
-defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
-defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
-defparam PLLInst_0.PLLRST_ENA = "DISABLED";
-defparam PLLInst_0.INTFB_WAKE = "DISABLED";
-endmodule /* pll_200_125_100 */
-
+++ /dev/null
-#
-# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
-#
-
-# Period Constraints
-
-
-# Output Constraints
-
-# Input Constraints
-
-# Point-to-point Delay Constraints
-
-
-
-# Block Path Constraints
-
-BLOCK ASYNCPATHS;
-
-# End of generated Logical Preferences.
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version M-2017.03L-SP1-1
-#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt
-#-- Written on Fri May 10 14:33:10 2019
-
-
-#project files
-add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
-add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"
-
-
-
-#implementation: "syn_results"
-impl -add syn_results -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM_25F
-set_option -package MG285C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "pll_200_125_100"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-
-# mapper_without_write_options
-set_option -frequency 100
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 1
-set_option -write_vhdl 1
-
-# Lattice XP
-set_option -maxfan 50
-set_option -disable_io_insertion 1
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./pll_200_125_100.edn"
-
-#set log file
-set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf"
-impl -active "syn_results"
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version M-2017.03L-SP1-1
-#-- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs
-
-#project files
-add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
-add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"
-
-
-
-#implementation: "syn_results"
-impl -add /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-
-#device options
-set_option -technology ecp5um
-set_option -part LFE5UM_25F
-set_option -package MG285C
-set_option -speed_grade -6
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "pll_200_125_100"
-
-# hdl_compiler_options
-set_option -distributed_compile 0
-
-# mapper_without_write_options
-set_option -frequency 100
-set_option -srs_instrumentation 1
-
-# mapper_options
-set_option -write_verilog 1
-set_option -write_vhdl 1
-
-# Lattice XP
-set_option -maxfan 50
-set_option -disable_io_insertion 1
-set_option -retiming 0
-set_option -pipe 0
-set_option -forcegsr false
-set_option -fix_gated_and_generated_clocks 1
-set_option -rw_check_on_ram 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-set_option -Write_declared_clocks_only 1
-
-# NFilter
-set_option -no_sequential_opt 0
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-
-# Compiler Options
-set_option -auto_infer_blackbox 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn"
-
-#set log file
-set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf"
-impl -active "syn_results"
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
+++ /dev/null
-./synlog/pll_200_125_100_compiler.srr,pll_200_125_100_compiler.srr,Compile Log
+++ /dev/null
-# Fri May 10 14:33:13 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 14:33:15 2019
-#
-
-
-Top view: pll_200_125_100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000
-===================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKINTFB
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 -
-CLKFB_t Net - - - - 1
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 14:33:15 2019
-
-###########################################################]
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:12 2019
-
-###########################################################]
+++ /dev/null
-# Fri May 10 14:33:12 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 14:33:13 2019
-
-###########################################################]
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>9</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>1</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:01s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557491591</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>0</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>0</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>0 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>8</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>1</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Peak Memory">
-<data>146MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557491595</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>NA</data>
-<data>10.000</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>2</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>143MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557491593</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-./pll_200_125_100_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-@P: Worst Slack : 10.000
-@P: System - Estimated Frequency : NA
-@P: System - Requested Frequency : 100.0 MHz
-@P: System - Estimated Period : 0.000
-@P: System - Requested Period : 10.000
-@P: System - Slack : 10.000
-@P: Total Area : 0.0
-@P: CPU Time : 0h:00m:02s
+++ /dev/null
-<html><body><samp><pre>
-<!@TC:1557491590>
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux
-#Hostname: lxhadeb07
-
-# Fri May 10 14:33:10 2019
-
-#Implementation: syn_results
-
-<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557491591> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557491591> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557491591> | Setting time resolution to ps
-@N: : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:12:7:12:22:@N::@XP_MSG">pll_200_125_100.vhd(12)</a><!@TM:1557491591> | Top entity is set to pll_200_125_100.
-VHDL syntax check successful!
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:12:7:12:22:@N:CD630:@XP_MSG">pll_200_125_100.vhd(12)</a><!@TM:1557491591> | Synthesizing work.pll_200_125_100.structure.
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:2083:10:2083:17:@N:CD630:@XP_MSG">ecp5um.vhd(2083)</a><!@TM:1557491591> | Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:832:10:832:13:@N:CD630:@XP_MSG">ecp5um.vhd(832)</a><!@TM:1557491591> | Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:825:10:825:13:@N:CD630:@XP_MSG">ecp5um.vhd(825)</a><!@TM:1557491591> | Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:50:4:50:18:@W:CL168:@XP_MSG">pll_200_125_100.vhd(50)</a><!@TM:1557491591> | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.</font>
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557491591> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:11 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557491590>
-<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1557491592> | Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 14:33:12 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557491590>
-Pre-mapping Report
-
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557491590>
-# Fri May 10 14:33:12 2019
-
-<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-Linked File: <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt:@XP_FILE">pll_200_125_100_scck.rpt</a>
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557491593> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557491593> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_200_125_100
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-<a name=mapperReport6></a>Clock Summary</a>
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 14:33:13 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557491590>
-Map & Optimize Report
-
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1557491590>
-# Fri May 10 14:33:13 2019
-
-<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557491595> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557491595> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557491595> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557491595> | Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
-M-2017.03L-SP1-1
-@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557491595> | Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:56:4:56:13:@W:MT246:@XP_MSG">pll_200_125_100.vhd(56)</a><!@TM:1557491595> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
-
-
-<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
-# Timing Report written on Fri May 10 14:33:15 2019
-#
-
-
-Top view: pll_200_125_100
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
-
-@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557491595> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557491595> | Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-<a name=performanceSummary10></a>Performance Summary</a>
-*******************
-
-
-Worst slack in design: 10.000
-
-@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1557491595> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-<a name=clockRelationships11></a>Clock Relationships</a>
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-<a name=interfaceInfo12></a>Interface Information </a>
-*********************
-
-No IO constraint found
-
-
-
-====================================
-<a name=clockReport13></a>Detailed Report for Clock: System</a>
-====================================
-
-
-
-<a name=startingSlack14></a>Starting Points with Worst Slack</a>
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000
-===================================================================================
-
-
-<a name=endingSlack15></a>Ending Points with Worst Slack</a>
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000
-=================================================================================
-
-
-
-<a name=worstPaths16></a>Worst Path Information</a>
-<a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr:srsf/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srs:fp:17491:17746:@XP_NAMES_GATE">View Worst Path in Analyst</a>
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKINTFB
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 -
-CLKFB_t Net - - - - 1
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-<a name=resourceUsage17></a>Resource Usage Report</a>
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 14:33:15 2019
-
-###########################################################]
-
-</pre></samp></body></html>
+++ /dev/null
- <html>
- <head>
- <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
- <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />
- </head>
-
- <body style="background-color:#e0e0ff;">
- <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
- <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
- <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">pll_200_125_100 (syn_results)</b>
- <ul rel="open" style="font-size:small;">
-
-<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
-<ul rel="open">
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a> </li>
-<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockReport13" target="srrFrame" title="">Clock: System</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt" target="srrFrame" title="">Constraint Checker Report (14:33 10-May)</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/stdout.log" target="srrFrame" title="">Session Log (14:33 10-May)</a>
-<ul ></ul></li> </ul>
- </li>
- </ul>
-
- <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
-
- </body>
- </html>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>
-<!--
- Synopsys, Inc.
- Version M-2017.03L-SP1-1
- Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml
- Written on Fri May 10 14:33:10 2019
-
-
--->
-<project_attribute_list name="Project Settings">
- <option name="project_name" display_name="Project Name">pll_200_125_100</option>
- <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
- <option name="impl_name" display_name="Implementation Name">syn_results</option>
- <option name="top_module" display_name="Top Module">pll_200_125_100</option>
- <option name="pipe" display_name="Pipelining">0</option>
- <option name="retiming" display_name="Retiming">0</option>
- <option name="resource_sharing" display_name="Resource Sharing">1</option>
- <option name="maxfan" display_name="Fanout Guide">50</option>
- <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
- <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
- <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
- <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
-</project_attribute_list>
-
+++ /dev/null
-<html>
- <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
- <title>Project Status Summary Page</title>
- <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
- <script type = "text/javascript" src="projectstatuspage.js"></script>
- </head>
-
- <body style="background-color:#f0f0ff;">
-
-<table style="border:none;" width="100%" ><tr> <td class="outline">
-<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
- <tr> <td class="optionTitle" align="left"> Project Name</td> <td> pll_200_125_100</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
-<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> pll_200_125_100</td> </tr>
- </thead>
- <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
-<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
-
-</tbody>
- </table><br> <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
- <tbody>
- <tr>
- <th align="left" width="17%">Job Name</th>
- <th align="left">Status</th>
- <td class="lnote" align="center" title="Notes"></td>
- <td class="lwarn" align="center" title="Warnings"></td>
- <td class="lerror" align="center" title="Errors"></td>
- <th align="left">CPU Time</th>
- <th align="left">Real Time</th>
- <th align="left">Memory</th>
- <th align="left">Date/Time</th>
- </tr>
- <tr>
- <td class="optionTitle"> (compiler)</td><td>Complete</td>
- <td>9</td>
- <td>1</td>
-<td>0</td>
-<td>-</td>
-<td>00m:01s</td>
-<td>-</td>
-<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (premap)</td><td>Complete</td>
- <td>2</td>
-<td>0</td>
-<td>0</td>
-<td>0m:00s</td>
-<td>0m:00s</td>
-<td>143MB</td>
-<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
- <td>8</td>
- <td>1</td>
-<td>0</td>
-<td>0m:02s</td>
-<td>0m:02s</td>
-<td>146MB</td>
-<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
-</tr>
-
-<tr>
- <td class="optionTitle">Multi-srs Generator</td>
- <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td> </tbody>
- </table>
- <br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
- </tfoot>
- <tbody> <tr>
-<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
-<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
-(v_ram)</td> <td>0</td>
-<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
-(dsp_used)</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
-(total_luts)</td> <td>0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr>
- </tfoot>
-<tbody>
- <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
-<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">10.000</td></tr>
-</tbody>
- </table>
-<br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Optimizations Summary</th></tr></thead>
- <tbody> <tr>
-<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
-<br>
-</td></tr></table></body>
- </html>
\ No newline at end of file
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work pll_200_125_100 structure 0
-module work pll_200_125_100 0
-
-
-# Configuration files used
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
-0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work pll_200_125_100 structure 0
-module work pll_200_125_100 0
+++ /dev/null
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_200_125_100.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+++ /dev/null
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work pll_200_125_100 0
-arch work pll_200_125_100 structure 0
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:44 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
-Post processing for work.pcsd.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = PCSDrsl_core_Z1_layer1
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
+++ /dev/null
-./synlog/PCSD_compiler.srr,PCSD_compiler.srr,Compile Log
+++ /dev/null
-# Tue Apr 30 12:09:48 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:00s 5.36ns 63 / 92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=================================== Non-Gated/Non-Generated Clocks ====================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
--------------------------------------------------------------------------------------------------------
-@K:CKID0001 rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18]
-@K:CKID0002 pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1
-=======================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Tue Apr 30 12:09:50 2019
-#
-
-
-Top view: PCSD
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.079
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------
-PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1
-System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup
-=========================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths -
-PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths -
-PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths -
-PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths -
-===========================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: PCSD|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684
-==============================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-=================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by PCSD|pll_refclki [rising] on pin CK
- The end point is clocked by PCSD|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[1] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: PCSD|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170
-rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742
-===============================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231
-rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231
-rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258
-rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258
-rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292
-==================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.809
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.136
-
- Number of logic level(s): 14
- Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q
- Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D
- The start point is clocked by PCSD|rxrefclk [rising] on pin CK
- The end point is clocked by PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 -
-rlol1_cnt[14] Net - - - - 2
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 -
-rlol1_cnt_tc_1_10 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 -
-rlol1_cnt_tc_1_14 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 -
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 -
-rlol1_cnt_tc_1 Net - - - - 6
-rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 -
-rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 -
-rlol1_cnt Net - - - - 20
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 -
-rlol1_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 -
-rlol1_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 -
-rlol1_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 -
-rlol1_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 -
-rlol1_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 -
-rlol1_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 -
-rlol1_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 -
-rlol1_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 -
-rlol1_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 -
-rlol1_cnt_s[18] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 -
-========================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946
-DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000
-===========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000
-DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000
-================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 9.946
-
- Number of logic level(s): 0
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.rlol_p1 / D
- The start point is clocked by System [rising]
- The end point is clocked by PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 2
-rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 -
-===================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 92 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 37
-DCUA: 1
-FD1P3BX: 4
-FD1P3DX: 42
-FD1S3BX: 10
-FD1S3DX: 36
-GSR: 1
-ORCALUT4: 63
-PFUMX: 2
-PUR: 1
-VHI: 2
-VLO: 2
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Apr 30 12:09:51 2019
-
-###########################################################]
+++ /dev/null
-CKID0001:@|S:rxrefclk@|E:rsl_inst.genblk2\.rlol1_cnt[18]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
-CKID0002:@|S:pll_refclki@|E:rsl_inst.genblk1\.pll_lol_p1@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:47 2019
-
-###########################################################]
+++ /dev/null
-# Tue Apr 30 12:09:47 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist PCSD
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59
-
-0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33
-=====================================================================================================
-
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Apr 30 12:09:48 2019
-
-###########################################################]
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/PCSD_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>10</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>50</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:02s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1556618986</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>92</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>63</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>2 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>11</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>3</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Peak Memory">
-<data>148MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1556618991</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>PCSD|pll_refclki</data>
-<data>100.0 MHz</data>
-<data>168.9 MHz</data>
-<data>4.079</data>
-</row>
-<row>
-<data>PCSD|rxrefclk</data>
-<data>100.0 MHz</data>
-<data>170.5 MHz</data>
-<data>4.136</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>18518.5 MHz</data>
-<data>9.946</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>2</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>2</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>143MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1556618988</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
+++ /dev/null
-./PCSD_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-@P: Worst Slack : 4.079
-@P: PCSD|pll_refclki - Estimated Frequency : 168.9 MHz
-@P: PCSD|pll_refclki - Requested Frequency : 100.0 MHz
-@P: PCSD|pll_refclki - Estimated Period : 5.921
-@P: PCSD|pll_refclki - Requested Period : 10.000
-@P: PCSD|pll_refclki - Slack : 4.079
-@P: PCSD|rxrefclk - Estimated Frequency : 170.5 MHz
-@P: PCSD|rxrefclk - Requested Frequency : 100.0 MHz
-@P: PCSD|rxrefclk - Estimated Period : 5.864
-@P: PCSD|rxrefclk - Requested Period : 10.000
-@P: PCSD|rxrefclk - Slack : 4.136
-@P: System - Estimated Frequency : 18518.5 MHz
-@P: System - Requested Frequency : 100.0 MHz
-@P: System - Estimated Period : 0.054
-@P: System - Requested Period : 10.000
-@P: System - Slack : 9.946
-@P: Total Area : 63.0
-@P: Total Area : 0.0
-@P: CPU Time : 0h:00m:02s
+++ /dev/null
-<html><body><samp><pre>
-<!@TC:1556618984>
-#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017
-#install: /home/soft/lattice/diamond/3.10_x64/synpbase
-#OS: Linux
-#Hostname: lxhadeb07
-
-# Tue Apr 30 12:09:44 2019
-
-#Implementation: syn_results
-
-<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1556618986> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1556618986> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1556618986> | Setting time resolution to ps
-@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N::@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Top entity is set to PCSD.
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:44 2019
-
-###########################################################]
-<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1556618986> | Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1556618986> | Setting time resolution to ps
-@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N::@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Top entity is set to PCSD.
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N:CD630:@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Synthesizing work.pcsd.v1.
-Post processing for work.pcsd.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:92:7:92:19:@N:CG364:@XP_MSG">PCSD_softlogic.v(92)</a><!@TM:1556618986> | Synthesizing module PCSDrsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = PCSDrsl_core_Z1_layer1
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:274:33:274:49:@W:CG360:@XP_MSG">PCSD_softlogic.v(274)</a><!@TM:1556618986> | Removing wire dual_or_serd_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:275:33:275:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(275)</a><!@TM:1556618986> | Removing wire tx_any_pcs_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:276:33:276:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(276)</a><!@TM:1556618986> | Removing wire tx_any_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:277:33:277:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(277)</a><!@TM:1556618986> | Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:278:33:278:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(278)</a><!@TM:1556618986> | Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:279:33:279:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(279)</a><!@TM:1556618986> | Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:280:33:280:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(280)</a><!@TM:1556618986> | Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:281:33:281:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(281)</a><!@TM:1556618986> | Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:282:33:282:42:@W:CG360:@XP_MSG">PCSD_softlogic.v(282)</a><!@TM:1556618986> | Removing wire txr_wt_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:283:33:283:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(283)</a><!@TM:1556618986> | Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">PCSD_softlogic.v(326)</a><!@TM:1556618986> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">PCSD_softlogic.v(327)</a><!@TM:1556618986> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(328)</a><!@TM:1556618986> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">PCSD_softlogic.v(341)</a><!@TM:1556618986> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">PCSD_softlogic.v(342)</a><!@TM:1556618986> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(343)</a><!@TM:1556618986> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(346)</a><!@TM:1556618986> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">PCSD_softlogic.v(347)</a><!@TM:1556618986> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">PCSD_softlogic.v(350)</a><!@TM:1556618986> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">PCSD_softlogic.v(351)</a><!@TM:1556618986> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(352)</a><!@TM:1556618986> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(353)</a><!@TM:1556618986> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:356:33:356:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(356)</a><!@TM:1556618986> | Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:357:33:357:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(357)</a><!@TM:1556618986> | Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:358:33:358:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(358)</a><!@TM:1556618986> | Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:359:33:359:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(359)</a><!@TM:1556618986> | Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:360:33:360:49:@W:CG360:@XP_MSG">PCSD_softlogic.v(360)</a><!@TM:1556618986> | Removing wire rxsdr_or_sr_appd, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:361:33:361:50:@W:CG360:@XP_MSG">PCSD_softlogic.v(361)</a><!@TM:1556618986> | Removing wire dual_or_rserd_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:362:33:362:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(362)</a><!@TM:1556618986> | Removing wire rx_any_pcs_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:363:33:363:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(363)</a><!@TM:1556618986> | Removing wire rx_any_rst, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:364:33:364:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(364)</a><!@TM:1556618986> | Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:365:33:365:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(365)</a><!@TM:1556618986> | Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:366:33:366:42:@W:CG360:@XP_MSG">PCSD_softlogic.v(366)</a><!@TM:1556618986> | Removing wire rxr_wt_tc, as there is no assignment to it.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:367:33:367:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(367)</a><!@TM:1556618986> | Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:507:10:507:11:@W:CG133:@XP_MSG">PCSD_softlogic.v(507)</a><!@TM:1556618986> | Object m is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:880:10:880:11:@W:CG133:@XP_MSG">PCSD_softlogic.v(880)</a><!@TM:1556618986> | Object l is declared but not assigned. Either assign a value or remove the declaration.</font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(806)</a><!@TM:1556618986> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618986> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618986> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
-<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(694)</a><!@TM:1556618986> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
-<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(461)</a><!@TM:1556618986> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
-<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(422)</a><!@TM:1556618986> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
-<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(422)</a><!@TM:1556618986> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
-<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(461)</a><!@TM:1556618986> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
-<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(694)</a><!@TM:1556618986> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(200)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">PCSD_softlogic.v(204)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(205)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(206)</a><!@TM:1556618986> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(207)</a><!@TM:1556618986> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
-
-
-Process completed successfully.
-# Tue Apr 30 12:09:45 2019
-
-###########################################################]
-<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1556618986> | Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog:@XP_FILE">PCSD_comp.linkerlog</a>
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:46 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1556618984>
-<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017</a>
-@N: : <!@TM:1556618987> | Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Tue Apr 30 12:09:47 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1556618984>
-# Tue Apr 30 12:09:47 2019
-
-<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt:@XP_FILE">PCSD_scck.rpt</a>
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1556618988> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1556618988> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist PCSD
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-<a name=mapperReport7></a>Clock Summary</a>
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - PCSD|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 59
-
-0 - PCSD|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 33
-=====================================================================================================
-
-<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:412:3:412:9:@W:MT529:@XP_MSG">PCSD_softlogic.v(412)</a><!@TM:1556618988> | Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
-<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618988> | Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Tue Apr 30 12:09:48 2019
-
-###########################################################]
-
-</pre></samp></body></html>
-<html><body><samp><pre>
-<!@TC:1556618984>
-# Tue Apr 30 12:09:48 2019
-
-<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35</a>
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1556618991> | Running in 64-bit mode.
-@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1556618991> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(412)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(778)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(680)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:00s 5.36ns 63 / 92
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1556618991> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
-
-2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=================================== Non-Gated/Non-Generated Clocks ====================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
--------------------------------------------------------------------------------------------------------
-<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.rlol1_cnt[18]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> rxrefclk port 59 rsl_inst.genblk2\.rlol1_cnt[18]
-<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.pll_lol_p1@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 @XP_NAMES_BY_PROP">ClockId0002 </a> pll_refclki port 33 rsl_inst.genblk1\.pll_lol_p1
-=======================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
-
-Writing EDIF Netlist and constraint files
-@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1556618991> | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
-M-2017.03L-SP1-1
-@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1556618991> | Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:118:4:118:13:@W:MT246:@XP_MSG">PCSD.vhd(118)</a><!@TM:1556618991> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
-<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1556618991> | Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font>
-<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1556618991> | Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font>
-
-
-<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
-# Timing Report written on Tue Apr 30 12:09:50 2019
-#
-
-
-Top view: PCSD
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
-
-@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1556618991> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1556618991> | Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-<a name=performanceSummary11></a>Performance Summary</a>
-*******************
-
-
-Worst slack in design: 4.079
-
-@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1556618991> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------
-PCSD|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-PCSD|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1
-System 100.0 MHz 18518.5 MHz 10.000 0.054 9.946 system system_clkgroup
-=========================================================================================================================
-
-
-
-
-
-<a name=clockRelationships12></a>Clock Relationships</a>
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-System PCSD|rxrefclk | 10.000 9.946 | No paths - | No paths - | No paths -
-PCSD|pll_refclki System | 10.000 8.385 | No paths - | No paths - | No paths -
-PCSD|pll_refclki PCSD|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-PCSD|rxrefclk System | 10.000 8.283 | No paths - | No paths - | No paths -
-PCSD|rxrefclk PCSD|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths -
-===========================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-<a name=interfaceInfo13></a>Interface Information </a>
-*********************
-
-No IO constraint found
-
-
-
-====================================
-<a name=clockReport14></a>Detailed Report for Clock: PCSD|pll_refclki</a>
-====================================
-
-
-
-<a name=startingSlack15></a>Starting Points with Worst Slack</a>
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] PCSD|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[6] PCSD|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[7] PCSD|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[2] PCSD|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[3] PCSD|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] PCSD|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] PCSD|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] PCSD|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684
-==============================================================================================================
-
-
-<a name=endingSlack16></a>Ending Points with Worst Slack</a>
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] PCSD|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] PCSD|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] PCSD|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] PCSD|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] PCSD|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] PCSD|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] PCSD|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] PCSD|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] PCSD|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] PCSD|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-=================================================================================================================
-
-
-
-<a name=worstPaths17></a>Worst Path Information</a>
-<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:38560:43552:@XP_NAMES_GATE">View Worst Path in Analyst</a>
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by PCSD|pll_refclki [rising] on pin CK
- The end point is clocked by PCSD|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[1] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-<a name=clockReport18></a>Detailed Report for Clock: PCSD|rxrefclk</a>
-====================================
-
-
-
-<a name=startingSlack19></a>Starting Points with Worst Slack</a>
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[10] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[10] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[14] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[14] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[16] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX Q rlols0_cnt[17] 0.907 4.170
-rsl_inst.genblk2\.rlol1_cnt[0] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-rsl_inst.genblk2\.rlol1_cnt[1] PCSD|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742
-===============================================================================================================
-
-
-<a name=endingSlack20></a>Ending Points with Worst Slack</a>
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[17] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.rlols0_cnt[17] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-rsl_inst.genblk2\.rlols0_cnt[15] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231
-rsl_inst.genblk2\.rlols0_cnt[16] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231
-rsl_inst.genblk2\.rlol1_cnt[13] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258
-rsl_inst.genblk2\.rlol1_cnt[14] PCSD|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258
-rsl_inst.genblk2\.rlols0_cnt[13] PCSD|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292
-==================================================================================================================
-
-
-
-<a name=worstPaths21></a>Worst Path Information</a>
-<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:48462:53187:@XP_NAMES_GATE">View Worst Path in Analyst</a>
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.809
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.136
-
- Number of logic level(s): 14
- Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q
- Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D
- The start point is clocked by PCSD|rxrefclk [rising] on pin CK
- The end point is clocked by PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 -
-rlol1_cnt[14] Net - - - - 2
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 -
-rlol1_cnt_tc_1_10 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 -
-rlol1_cnt_tc_1_14 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 -
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 -
-rlol1_cnt_tc_1 Net - - - - 6
-rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 A In 0.000 2.887 -
-rsl_inst.genblk2\.rxs_rst_RNIS0OP ORCALUT4 Z Out 0.837 3.724 -
-rlol1_cnt Net - - - - 20
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 -
-rlol1_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 -
-rlol1_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 -
-rlol1_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 -
-rlol1_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 -
-rlol1_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 -
-rlol1_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 -
-rlol1_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 -
-rlol1_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 -
-rlol1_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 -
-rlol1_cnt_s[18] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 -
-========================================================================================================
-
-
-
-
-====================================
-<a name=clockReport22></a>Detailed Report for Clock: System</a>
-====================================
-
-
-
-<a name=startingSlack23></a>Starting Points with Worst Slack</a>
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 9.946
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 9.946
-DCU0_inst System DCUA CH0_FF_TX_PCLK tx_pclk 0.000 10.000
-===========================================================================================
-
-
-<a name=endingSlack24></a>Ending Points with Worst Slack</a>
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-----------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-DCU0_inst System DCUA CH0_FF_EBRD_CLK tx_pclk 10.000 10.000
-DCU0_inst System DCUA CH0_FF_RXI_CLK tx_pclk 10.000 10.000
-================================================================================================================
-
-
-
-<a name=worstPaths25></a>Worst Path Information</a>
-<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:56441:56741:@XP_NAMES_GATE">View Worst Path in Analyst</a>
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 9.946
-
- Number of logic level(s): 0
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.rlol_p1 / D
- The start point is clocked by System [rising]
- The end point is clocked by PCSD|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 2
-rsl_inst.genblk2\.rlol_p1 FD1S3DX D In 0.000 0.000 -
-===================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
-
----------------------------------------
-<a name=resourceUsage26></a>Resource Usage Report</a>
-Part: lfe5um_25f-6
-
-Register bits: 92 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 37
-DCUA: 1
-FD1P3BX: 4
-FD1P3DX: 42
-FD1S3BX: 10
-FD1S3DX: 36
-GSR: 1
-ORCALUT4: 63
-PFUMX: 2
-PUR: 1
-VHI: 2
-VLO: 2
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Tue Apr 30 12:09:51 2019
-
-###########################################################]
-
-</pre></samp></body></html>
+++ /dev/null
- <html>
- <head>
- <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
- <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />
- </head>
-
- <body style="background-color:#e0e0ff;">
- <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
- <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
- <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">PCSD (syn_results)</b>
- <ul rel="open" style="font-size:small;">
-
-<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
-<ul rel="open">
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>
-<ul rel="open" >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a> </li>
-<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport14" target="srrFrame" title="">Clock: PCSD|pll_refclki</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport18" target="srrFrame" title="">Clock: PCSD|rxrefclk</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport22" target="srrFrame" title="">Clock: System</a>
-<ul >
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a> </li></ul></li></ul></li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#resourceUsage26" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_cck.rpt" target="srrFrame" title="">Constraint Checker Report (12:09 30-Apr)</a> </li></ul></li>
-<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/stdout.log" target="srrFrame" title="">Session Log (12:09 30-Apr)</a>
-<ul ></ul></li> </ul>
- </li>
- </ul>
-
- <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
-
- </body>
- </html>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>
-<!--
- Synopsys, Inc.
- Version M-2017.03L-SP1-1
- Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/run_option.xml
- Written on Tue Apr 30 12:09:44 2019
-
-
--->
-<project_attribute_list name="Project Settings">
- <option name="project_name" display_name="Project Name">PCSD</option>
- <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
- <option name="impl_name" display_name="Implementation Name">syn_results</option>
- <option name="top_module" display_name="Top Module">PCSD</option>
- <option name="pipe" display_name="Pipelining">0</option>
- <option name="retiming" display_name="Retiming">0</option>
- <option name="resource_sharing" display_name="Resource Sharing">1</option>
- <option name="maxfan" display_name="Fanout Guide">50</option>
- <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
- <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
- <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
- <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
-</project_attribute_list>
-
+++ /dev/null
-<html>
- <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
- <title>Project Status Summary Page</title>
- <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
- <script type = "text/javascript" src="projectstatuspage.js"></script>
- </head>
-
- <body style="background-color:#f0f0ff;">
-
-<table style="border:none;" width="100%" ><tr> <td class="outline">
-<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
- <tr> <td class="optionTitle" align="left"> Project Name</td> <td> PCSD</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
-<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> PCSD</td> </tr>
- </thead>
- <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
-<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
-<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
-
-</tbody>
- </table><br> <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
- <tbody>
- <tr>
- <th align="left" width="17%">Job Name</th>
- <th align="left">Status</th>
- <td class="lnote" align="center" title="Notes"></td>
- <td class="lwarn" align="center" title="Warnings"></td>
- <td class="lerror" align="center" title="Errors"></td>
- <th align="left">CPU Time</th>
- <th align="left">Real Time</th>
- <th align="left">Memory</th>
- <th align="left">Date/Time</th>
- </tr>
- <tr>
- <td class="optionTitle"> (compiler)</td><td>Complete</td>
- <td>10</td>
- <td>50</td>
-<td>0</td>
-<td>-</td>
-<td>00m:02s</td>
-<td>-</td>
-<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (premap)</td><td>Complete</td>
- <td>2</td>
- <td>2</td>
-<td>0</td>
-<td>0m:00s</td>
-<td>0m:00s</td>
-<td>143MB</td>
-<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
-</tr>
-
- <tr>
- <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
- <td>11</td>
- <td>3</td>
-<td>0</td>
-<td>0m:02s</td>
-<td>0m:02s</td>
-<td>148MB</td>
-<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
-</tr>
-
-<tr>
- <td class="optionTitle">Multi-srs Generator</td>
- <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td> </tbody>
- </table>
- <br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
- </tfoot>
- <tbody> <tr>
-<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>92</td>
-<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
-(v_ram)</td> <td>0</td>
-<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
-(dsp_used)</td> <td>0</td>
-</tr>
-<tr>
-<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
-(total_luts)</td> <td>63</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
-<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr>
- </tfoot>
-<tbody>
- <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
-<tr> <td align="left">PCSD|pll_refclki</td><td align="left">100.0 MHz</td><td align="left">168.9 MHz</td><td align="left">4.079</td></tr>
-<tr> <td align="left">PCSD|rxrefclk</td><td align="left">100.0 MHz</td><td align="left">170.5 MHz</td><td align="left">4.136</td></tr>
-<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">18518.5 MHz</td><td align="left">9.946</td></tr>
-</tbody>
- </table>
-<br>
- <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
- <thead class="tablehead"><tr><th colspan="4">Optimizations Summary</th></tr></thead>
- <tbody> <tr>
-<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>2 / 0</td>
-<td class="optionTitle"></td><td></td></tr>
-</tbody>
- </table><br>
-<br>
-</td></tr></table></body>
- </html>
\ No newline at end of file
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-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983
-0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work pcsd v1 0
-module work pcsd 0
-
-# Unbound Instances to File Association
-inst work pcsd pcsdrsl_core 0
-inst work pcsd dcua 0
+++ /dev/null
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
-Post processing for work.pcsd.v1
+++ /dev/null
-#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile|-top|work.PCSDrsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile":1556618984
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1556618983
-#numinternalfiles:6
-#defaultlanguage:verilog
-0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" verilog
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work PCSDrsl_core 0
-#Unbound instances to file Association.
+++ /dev/null
-|work.PCSDrsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "DISABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "DISABLED";,parameter pwait_rx_rdy 3000;|
+++ /dev/null
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = PCSDrsl_core_Z1_layer1
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
-File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_in125_out125_out33.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 15:07:25 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 15:07:26 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 15:07:26 2019
-
-###########################################################]
+++ /dev/null
-./synlog/pll_in125_out125_out33_compiler.srr,pll_in125_out125_out33_compiler.srr,Compile Log
+++ /dev/null
-# Fri May 10 15:07:28 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 15:07:30 2019
-#
-
-
-Top view: pll_in125_out125_out33
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 10.000
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------
-System 100.0 MHz NA 10.000 0.000 10.000 system system_clkgroup
-================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-=========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKINTFB CLKFB_t 0.000 10.000
-===================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------
-PLLInst_0 System EHXPLLL CLKFB CLKFB_t 10.000 10.000
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.000
- + Clock delay at ending point: 0.000 (ideal)
- + Estimated clock delay at ending point: 0.000
- = Required time: 10.000
-
- - Propagation time: 0.000
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (critical) : 10.000
-
- Number of logic level(s): 0
- Starting point: PLLInst_0 / CLKINTFB
- Ending point: PLLInst_0 / CLKFB
- The start point is clocked by System [rising]
- The end point is clocked by System [rising]
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
-PLLInst_0 EHXPLLL CLKINTFB Out 0.000 0.000 -
-CLKFB_t Net - - - - 1
-PLLInst_0 EHXPLLL CLKFB In 0.000 0.000 -
-====================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 0 of 24288 (0%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-EHXPLLL: 1
-GSR: 1
-PUR: 1
-VHI: 1
-VLO: 1
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
-
-Process took 0h:00m:02s realtime, 0h:00m:02s cputime
-# Fri May 10 15:07:30 2019
-
-###########################################################]
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 15:07:27 2019
-
-###########################################################]
+++ /dev/null
-# Fri May 10 15:07:27 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
-@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist pll_in125_out125_out33
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-=====================================================================================
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 15:07:28 2019
-
-###########################################################]
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>9</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>1</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:01s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557493646</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>0</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>0</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>0 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>8</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>1</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:02s</data>
-</info>
-<info name="Peak Memory">
-<data>146MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557493650</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>NA</data>
-<data>10.000</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>2</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>143MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557493648</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-./pll_in125_out125_out33_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work pll_in125_out125_out33 structure 0
-module work pll_in125_out125_out33 0
-
-
-# Configuration files used
+++ /dev/null
-#defaultlanguage:vhdl
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
-0 "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
-
-# Dependency Lists (Uses list)
-0 -1
-
-# Dependency Lists (Users Of)
-0 -1
-
-# Design Unit to File Association
-arch work pll_in125_out125_out33 structure 0
-module work pll_in125_out125_out33 0
+++ /dev/null
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
-Post processing for ecp5um.ehxplll.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
-Post processing for ecp5um.vlo.syn_black_box
-@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
-Post processing for ecp5um.vhi.syn_black_box
-Post processing for work.pll_in125_out125_out33.structure
-@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+++ /dev/null
-#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
-#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
-#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
-0 "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
-#Dependency Lists(Uses List)
-0 -1
-#Dependency Lists(Users Of)
-0 -1
-#Design Unit to File Association
-module work pll_in125_out125_out33 0
-arch work pll_in125_out125_out33 structure 0
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>15</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>76</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:02s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557471731</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>221</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>154</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>3 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>22</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>4</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Peak Memory">
-<data>153MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557471736</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>sgmii_ecp5|pll_refclki</data>
-<data>100.0 MHz</data>
-<data>168.9 MHz</data>
-<data>4.079</data>
-</row>
-<row>
-<data>sgmii_ecp5|rxrefclk</data>
-<data>100.0 MHz</data>
-<data>167.9 MHz</data>
-<data>4.043</data>
-</row>
-<row>
-<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
-<data>100.0 MHz</data>
-<data>237.5 MHz</data>
-<data>5.789</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>840.7 MHz</data>
-<data>8.810</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>9</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>3</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>144MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557471733</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 09:02:09 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 09:02:10 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-Post processing for work.sgmii_ecp5.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Fri May 10 09:02:10 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-
- PDATA_RST_VAL=32'b00000000000000000000000000000000
- Generated name = sync_0s
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-
- PPROTOCOL=24'b010001110100001001000101
- PLOL_SETTING=32'b00000000000000000000000000000000
- PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
- PPCIE_MAX_RATE=24'b001100100010111000110101
- PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
- PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
- PPCLK_TC=32'b00000000000000100000000000000000
- PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
- PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
- PPCLK_DIV11_TC=32'b00000000000000000000000000000000
- LPLL_LOSS_ST=2'b00
- LPLL_PRELOSS_ST=2'b01
- LPLL_PRELOCK_ST=2'b10
- LPLL_LOCK_ST=2'b11
- LRCLK_TC=16'b1111111111111111
- LRCLK_TC_PUL_WIDTH=16'b0000000000110010
- LHB_WAIT_CNT=8'b11111111
- LPCLK_TC_0=32'b00000000000000001000000000000000
- LPCLK_TC_1=32'b00000000000000010000000000000000
- LPCLK_TC_2=32'b00000000000000100000000000000000
- LPCLK_TC_3=32'b00000000000000101000000000000000
- LPCLK_TC_4=32'b00000000000000010000000000000000
- LPDIFF_LOCK_00=32'b00000000000000000000000000001001
- LPDIFF_LOCK_10=32'b00000000000000000000000000010011
- LPDIFF_LOCK_20=32'b00000000000000000000000000100111
- LPDIFF_LOCK_30=32'b00000000000000000000000000110001
- LPDIFF_LOCK_40=32'b00000000000000000000000000010011
- LPDIFF_LOCK_01=32'b00000000000000000000000000001001
- LPDIFF_LOCK_11=32'b00000000000000000000000000010011
- LPDIFF_LOCK_21=32'b00000000000000000000000000100111
- LPDIFF_LOCK_31=32'b00000000000000000000000000110001
- LPDIFF_LOCK_41=32'b00000000000000000000000000010011
- LPDIFF_LOCK_02=32'b00000000000000000000000000110001
- LPDIFF_LOCK_12=32'b00000000000000000000000001100010
- LPDIFF_LOCK_22=32'b00000000000000000000000011000100
- LPDIFF_LOCK_32=32'b00000000000000000000000011110101
- LPDIFF_LOCK_42=32'b00000000000000000000000001100010
- LPDIFF_LOCK_03=32'b00000000000000000000000010000011
- LPDIFF_LOCK_13=32'b00000000000000000000000100000110
- LPDIFF_LOCK_23=32'b00000000000000000000001000001100
- LPDIFF_LOCK_33=32'b00000000000000000000001010001111
- LPDIFF_LOCK_43=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
- LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
- LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
- LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
- LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
- LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
- LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
- LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
- LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
- LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
- LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
- LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
- LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
- Generated name = sgmii_ecp5sll_core_Z1_layer1
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = sgmii_ecp5rsl_core_Z2_layer1
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-Extracted state machine for register sll_state
-State machine has 4 reachable states with original encodings of:
- 00
- 01
- 10
- 11
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
-
-
-Process completed successfully.
-# Fri May 10 09:02:10 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 09:02:11 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 09:02:11 2019
-
-###########################################################]
+++ /dev/null
-./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log
+++ /dev/null
-# Fri May 10 09:02:13 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
-
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:01s 4.90ns 155 / 221
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-============================================= Non-Gated/Non-Generated Clocks =============================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------------------------------------
-@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
-@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
-@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21]
-==========================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 09:02:16 2019
-#
-
-
-Top view: sgmii_ecp5
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.043
-
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------------------------
-sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-sgmii_ecp5|rxrefclk 100.0 MHz 167.9 MHz 10.000 5.957 4.043 inferred Inferred_clkgroup_1
-sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2
-System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup
-========================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk System | 10.000 8.277 | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.043 | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths -
-============================================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-====================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-=======================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
- The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[2] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.043
-rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170
-rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-===================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[11] 9.946 4.043
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[9] 9.946 4.104
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[10] 9.946 4.104
-rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[7] 9.946 4.165
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX D rxr_wt_cnt_s[8] 9.946 4.165
-rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-=================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.902
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.043
-
- Number of logic level(s): 11
- Starting point: rsl_inst.genblk2\.rxs_rst / Q
- Ending point: rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
- The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rxs_rst FD1P3DX Q Out 1.015 1.015 -
-rxs_rst Net - - - - 6
-rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 B In 0.000 1.015 -
-rsl_inst.rdo_rx_serdes_rst_c_1[0] ORCALUT4 Z Out 0.708 1.723 -
-rsl_rx_serdes_rst_c Net - - - - 3
-rsl_inst.dual_or_rserd_rst ORCALUT4 A In 0.000 1.723 -
-rsl_inst.dual_or_rserd_rst ORCALUT4 Z Out 0.798 2.521 -
-dual_or_rserd_rst Net - - - - 9
-rsl_inst.rx_any_rst ORCALUT4 A In 0.000 2.521 -
-rsl_inst.rx_any_rst ORCALUT4 Z Out 0.660 3.181 -
-rx_any_rst Net - - - - 2
-rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 A In 0.000 3.181 -
-rsl_inst.rx_any_rst_RNIFD021 ORCALUT4 Z Out 0.819 4.000 -
-rxr_wt_cnt9 Net - - - - 14
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C A1 In 0.000 4.000 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0] CCU2C COUT Out 0.900 4.900 -
-rxr_wt_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C CIN In 0.000 4.900 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1] CCU2C COUT Out 0.061 4.961 -
-rxr_wt_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C CIN In 0.000 4.961 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3] CCU2C COUT Out 0.061 5.022 -
-rxr_wt_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C CIN In 0.000 5.022 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5] CCU2C COUT Out 0.061 5.083 -
-rxr_wt_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C CIN In 0.000 5.083 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7] CCU2C COUT Out 0.061 5.144 -
-rxr_wt_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C CIN In 0.000 5.144 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9] CCU2C COUT Out 0.061 5.205 -
-rxr_wt_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C CIN In 0.000 5.205 -
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11] CCU2C S0 Out 0.698 5.902 -
-rxr_wt_cnt_s[11] Net - - - - 1
-rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] FD1P3DX D In 0.000 5.902 -
-=================================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789
-sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789
-sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147
-sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178
-sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239
-sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239
-sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287
-sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287
-sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300
-sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300
-========================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------------------------
-sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789
-sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850
-sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850
-sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911
-sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911
-sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972
-sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972
-sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033
-sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033
-sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034
-=========================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 4.157
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 5.789
-
- Number of logic level(s): 13
- Starting point: sll_inst.ppul_sync_p1 / Q
- Ending point: sll_inst.pcount[21] / D
- The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
- The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 -
-ppul_sync_p1 Net - - - - 25
-sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 -
-sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 -
-N_8 Net - - - - 25
-sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 -
-sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 -
-pcount_cry[0] Net - - - - 1
-sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 -
-sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 -
-pcount_cry[2] Net - - - - 1
-sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 -
-sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 -
-pcount_cry[4] Net - - - - 1
-sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 -
-sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 -
-pcount_cry[6] Net - - - - 1
-sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 -
-sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 -
-pcount_cry[8] Net - - - - 1
-sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 -
-sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 -
-pcount_cry[10] Net - - - - 1
-sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 -
-sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 -
-pcount_cry[12] Net - - - - 1
-sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 -
-sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 -
-pcount_cry[14] Net - - - - 1
-sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 -
-sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 -
-pcount_cry[16] Net - - - - 1
-sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 -
-sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 -
-pcount_cry[18] Net - - - - 1
-sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 -
-sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 -
-pcount_cry[20] Net - - - - 1
-sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 -
-sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 -
-pcount_s[21] Net - - - - 1
-sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 -
-============================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-----------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-=============================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.194
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.806
-
- - Propagation time: 0.996
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 8.810
-
- Number of logic level(s): 2
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
- The start point is clocked by System [rising]
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 4
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 -
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 -
-un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 -
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 -
-un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 -
-===================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 221 of 24288 (1%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 113
-DCUA: 1
-FD1P3BX: 20
-FD1P3DX: 92
-FD1S3BX: 12
-FD1S3DX: 97
-GSR: 1
-INV: 3
-ORCALUT4: 154
-PFUMX: 2
-PUR: 1
-VHI: 6
-VLO: 6
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Fri May 10 09:02:16 2019
-
-###########################################################]
+++ /dev/null
-CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
-CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002
-CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 09:02:12 2019
-
-###########################################################]
+++ /dev/null
-# Fri May 10 09:02:12 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
-@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93
-
-0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77
-
-0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53
-======================================================================================================================
-
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 09:02:13 2019
-
-###########################################################]
+++ /dev/null
-./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;|
-|work.sgmii_ecp5sll_core|parameter PPROTOCOL "GBE";,parameter PLOL_SETTING 0;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 39;,parameter PDIFF_VAL_UNLOCK 78;,parameter PPCLK_TC 131072;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;|
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>15</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>77</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:02s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557482336</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>221</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>153</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>3 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>22</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>4</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Peak Memory">
-<data>153MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557482342</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>sgmii_ecp5|pll_refclki</data>
-<data>100.0 MHz</data>
-<data>168.9 MHz</data>
-<data>4.079</data>
-</row>
-<row>
-<data>sgmii_ecp5|rxrefclk</data>
-<data>100.0 MHz</data>
-<data>170.5 MHz</data>
-<data>4.136</data>
-</row>
-<row>
-<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
-<data>100.0 MHz</data>
-<data>237.5 MHz</data>
-<data>5.789</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>840.7 MHz</data>
-<data>8.810</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>9</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>3</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>144MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557482338</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-VHDL syntax check successful!
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 11:58:55 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 11:58:55 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
-VHDL syntax check successful!
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
-Post processing for work.sgmii_ecp5.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Fri May 10 11:58:55 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-
- PDATA_RST_VAL=32'b00000000000000000000000000000000
- Generated name = sync_0s
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
-
- PPROTOCOL=24'b010001110100001001000101
- PLOL_SETTING=32'b00000000000000000000000000000000
- PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
- PPCIE_MAX_RATE=24'b001100100010111000110101
- PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
- PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
- PPCLK_TC=32'b00000000000000010000000000000000
- PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
- PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
- PPCLK_DIV11_TC=32'b00000000000000000000000000000000
- LPLL_LOSS_ST=2'b00
- LPLL_PRELOSS_ST=2'b01
- LPLL_PRELOCK_ST=2'b10
- LPLL_LOCK_ST=2'b11
- LRCLK_TC=16'b1111111111111111
- LRCLK_TC_PUL_WIDTH=16'b0000000000110010
- LHB_WAIT_CNT=8'b11111111
- LPCLK_TC_0=32'b00000000000000001000000000000000
- LPCLK_TC_1=32'b00000000000000010000000000000000
- LPCLK_TC_2=32'b00000000000000100000000000000000
- LPCLK_TC_3=32'b00000000000000101000000000000000
- LPCLK_TC_4=32'b00000000000000010000000000000000
- LPDIFF_LOCK_00=32'b00000000000000000000000000001001
- LPDIFF_LOCK_10=32'b00000000000000000000000000010011
- LPDIFF_LOCK_20=32'b00000000000000000000000000100111
- LPDIFF_LOCK_30=32'b00000000000000000000000000110001
- LPDIFF_LOCK_40=32'b00000000000000000000000000010011
- LPDIFF_LOCK_01=32'b00000000000000000000000000001001
- LPDIFF_LOCK_11=32'b00000000000000000000000000010011
- LPDIFF_LOCK_21=32'b00000000000000000000000000100111
- LPDIFF_LOCK_31=32'b00000000000000000000000000110001
- LPDIFF_LOCK_41=32'b00000000000000000000000000010011
- LPDIFF_LOCK_02=32'b00000000000000000000000000110001
- LPDIFF_LOCK_12=32'b00000000000000000000000001100010
- LPDIFF_LOCK_22=32'b00000000000000000000000011000100
- LPDIFF_LOCK_32=32'b00000000000000000000000011110101
- LPDIFF_LOCK_42=32'b00000000000000000000000001100010
- LPDIFF_LOCK_03=32'b00000000000000000000000010000011
- LPDIFF_LOCK_13=32'b00000000000000000000000100000110
- LPDIFF_LOCK_23=32'b00000000000000000000001000001100
- LPDIFF_LOCK_33=32'b00000000000000000000001010001111
- LPDIFF_LOCK_43=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
- LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
- LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
- LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
- LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
- LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
- LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
- LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
- LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
- LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
- LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
- LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
- LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
- Generated name = sgmii_ecp5sll_core_Z1_layer1
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=24'b010001110100001001000101
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = sgmii_ecp5rsl_core_Z2_layer1
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-Extracted state machine for register sll_state
-State machine has 4 reachable states with original encodings of:
- 00
- 01
- 10
- 11
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
-
-
-Process completed successfully.
-# Fri May 10 11:58:56 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 11:58:56 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 11:58:56 2019
-
-###########################################################]
+++ /dev/null
-./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log
+++ /dev/null
-# Fri May 10 11:58:58 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
-
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:01s 5.36ns 154 / 221
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-============================================= Non-Gated/Non-Generated Clocks =============================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------------------------------------
-@K:CKID0001 pll_refclki port 91 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
-@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
-@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount[21]
-==========================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 11:59:02 2019
-#
-
-
-Top view: sgmii_ecp5
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.079
-
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------------------------
-sgmii_ecp5|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-sgmii_ecp5|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1
-sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2
-System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup
-========================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-System sgmii_ecp5|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki System | 10.000 8.253 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-sgmii_ecp5|pll_refclki sgmii_ecp5|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk System | 10.000 8.184 | No paths - | No paths - | No paths -
-sgmii_ecp5|rxrefclk sgmii_ecp5|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|pll_refclki | Diff grp - | No paths - | No paths - | No paths -
-sgmii_ecp5|tx_pclk_inferred_clock sgmii_ecp5|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths -
-============================================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[3] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[17] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[19] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[1] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[6] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[7] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] sgmii_ecp5|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-====================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] sgmii_ecp5|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-=======================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[2] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
- The end point is clocked by sgmii_ecp5|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[2] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[2] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[7] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[7] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[8] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[8] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[9] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[9] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[10] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[10] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[1] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[1] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[2] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[2] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[3] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[3] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[4] sgmii_ecp5|rxrefclk FD1P3DX Q rlols0_cnt[4] 0.907 4.170
-rsl_inst.genblk2\.rxs_rst sgmii_ecp5|rxrefclk FD1P3DX Q rxs_rst 1.015 4.700
-rsl_inst.genblk2\.rlol1_cnt[0] sgmii_ecp5|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-===================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.rlols0_cnt[17] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-rsl_inst.genblk2\.rlols0_cnt[15] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231
-rsl_inst.genblk2\.rlols0_cnt[16] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231
-rsl_inst.genblk2\.rlol1_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258
-rsl_inst.genblk2\.rlol1_cnt[14] sgmii_ecp5|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258
-rsl_inst.genblk2\.rlols0_cnt[13] sgmii_ecp5|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292
-========================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.809
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.136
-
- Number of logic level(s): 14
- Starting point: rsl_inst.genblk2\.rlol1_cnt[7] / Q
- Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D
- The start point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[7] FD1P3DX Q Out 0.907 0.907 -
-rlol1_cnt[7] Net - - - - 2
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 -
-rlol1_cnt_tc_1_10 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 -
-rlol1_cnt_tc_1_14 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 -
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 -
-rlol1_cnt_tc_1 Net - - - - 6
-rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 -
-rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 -
-rlol1_cnt Net - - - - 20
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 -
-rlol1_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 -
-rlol1_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 -
-rlol1_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 -
-rlol1_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 -
-rlol1_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 -
-rlol1_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 -
-rlol1_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 -
-rlol1_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 -
-rlol1_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 -
-rlol1_cnt_s[18] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 -
-========================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789
-sll_inst.ppul_sync_p2 sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789
-sll_inst.pcount_diff[0] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147
-sll_inst.pcount[0] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178
-sll_inst.pcount_diff[1] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239
-sll_inst.pcount_diff[2] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239
-sll_inst.pcount[1] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287
-sll_inst.pcount[2] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287
-sll_inst.pcount_diff[3] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300
-sll_inst.pcount_diff[4] sgmii_ecp5|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300
-========================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------------------------
-sll_inst.pcount[21] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789
-sll_inst.pcount[19] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850
-sll_inst.pcount[20] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850
-sll_inst.pcount[17] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911
-sll_inst.pcount[18] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911
-sll_inst.pcount[15] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972
-sll_inst.pcount[16] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972
-sll_inst.pcount[13] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033
-sll_inst.pcount[14] sgmii_ecp5|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033
-sll_inst.pcount_diff[21] sgmii_ecp5|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034
-=========================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 4.157
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 5.789
-
- Number of logic level(s): 13
- Starting point: sll_inst.ppul_sync_p1 / Q
- Ending point: sll_inst.pcount[21] / D
- The start point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
- The end point is clocked by sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 -
-ppul_sync_p1 Net - - - - 25
-sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 -
-sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 -
-N_8 Net - - - - 25
-sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 -
-sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 -
-pcount_cry[0] Net - - - - 1
-sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 -
-sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 -
-pcount_cry[2] Net - - - - 1
-sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 -
-sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 -
-pcount_cry[4] Net - - - - 1
-sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 -
-sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 -
-pcount_cry[6] Net - - - - 1
-sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 -
-sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 -
-pcount_cry[8] Net - - - - 1
-sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 -
-sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 -
-pcount_cry[10] Net - - - - 1
-sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 -
-sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 -
-pcount_cry[12] Net - - - - 1
-sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 -
-sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 -
-pcount_cry[14] Net - - - - 1
-sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 -
-sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 -
-pcount_cry[16] Net - - - - 1
-sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 -
-sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 -
-pcount_cry[18] Net - - - - 1
-sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 -
-sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 -
-pcount_cry[20] Net - - - - 1
-sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 -
-sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 -
-pcount_s[21] Net - - - - 1
-sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 -
-============================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-----------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810
-========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D rxpr_appd_RNO[0] 9.946 9.556
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-=============================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.194
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.806
-
- - Propagation time: 0.996
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 8.810
-
- Number of logic level(s): 2
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
- The start point is clocked by System [rising]
- The end point is clocked by sgmii_ecp5|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 4
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 A In 0.000 0.000 -
-rsl_inst.un2_rdo_serdes_rst_dual_c_1_1 ORCALUT4 Z Out 0.606 0.606 -
-un2_rdo_serdes_rst_dual_c_1_1 Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 B In 0.000 0.606 -
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0] ORCALUT4 Z Out 0.390 0.996 -
-un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 -
-===================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 221 of 24288 (1%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 113
-DCUA: 1
-FD1P3BX: 20
-FD1P3DX: 92
-FD1S3BX: 12
-FD1S3DX: 97
-GSR: 1
-INV: 3
-ORCALUT4: 153
-PFUMX: 2
-PUR: 1
-VHI: 6
-VLO: 6
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Fri May 10 11:59:02 2019
-
-###########################################################]
+++ /dev/null
-CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
-CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002
-CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 11:58:57 2019
-
-###########################################################]
+++ /dev/null
-# Fri May 10 11:58:57 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
-@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
-
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist sgmii_ecp5
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - sgmii_ecp5|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 93
-
-0 - sgmii_ecp5|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77
-
-0 - sgmii_ecp5|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53
-======================================================================================================================
-
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 10 -> 10
- 11 -> 11
-@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 11:58:58 2019
-
-###########################################################]
+++ /dev/null
-./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-#XMR Information
+++ /dev/null
-
-fsm_encoding {61801018011} sequential
-
-fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
-
-fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
-
-fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
-
-fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
-
-fsm_registers {61801018011} {sll_state[1]} {sll_state[0]}
+++ /dev/null
-## UMR3 MESSAGE PORT CONFIGURATION FILE
-## ************************************
-XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0
+++ /dev/null
-./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.
+++ /dev/null
-./synwork/serdes_sync_1_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind
+++ /dev/null
-@N|Running in 64-bit mode
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
-@N|Running in 64-bit mode
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-@N|Running in 64-bit mode
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from compiler to be displayed as part of the summary report.
-*******************************************************************************************-->
-
-<job_run_status name="compiler">
- <report_link name="Detailed report">
- <data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr</data>
- <title>Synopsys HDL Compiler</title>
- </report_link>
- <job_status>
- <data>Completed </data>
- </job_status>
-<job_info>
- <info name="Notes">
- <data>15</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt</data></report_link>
- </info>
- <info name="Warnings">
- <data>77</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt</data></report_link>
- </info>
- <info name="Errors">
- <data>0</data>
- <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_errors.txt</data></report_link>
- </info>
- <info name="CPU Time">
- <data>-</data>
- </info>
- <info name="Real Time">
- <data>00h:00m:02s</data>
- </info>
- <info name="Peak Memory">
- <data>-</data>
- </info>
- <info name="Date &Time">
- <data type="timestamp">1557476612</data>
- </info>
- </job_info>
-</job_run_status>
\ No newline at end of file
+++ /dev/null
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the area information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="1" name="Area Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_resourceusage.rpt</data>
-<title>Resource Usage</title>
-</report_link>
-<parameter tooltip="Total Register bits used" name="Register bits">
-<data>220</data>
-</parameter>
-<parameter tooltip="Total I/O cells used" name="I/O cells">
-<data>0</data>
-</parameter>
-<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
-<data>0</data>
-</parameter>
-<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
-<data>150</data>
-</parameter>
-</report_table>
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the optimization information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<report_table display_priority="3" name="Optimizations Summary">
-<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
-<data>3 / 0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_combined_clk.rpt</data>
-<title>START OF CLOCK OPTIMIZATION REPORT</title>
-</report_link>
-</parameter>
-</report_table>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr</data>
-<title>Synopsys Lattice Technology Mapper</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>23</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>4</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:03s</data>
-</info>
-<info name="Peak Memory">
-<data>152MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557476618</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
-*******************************************************************************************-->
-<report_table display_priority="2" name="Timing Summary">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr</data>
-<title>START OF TIMING REPORT</title>
-</report_link>
-<row>
-<data tcl_name="clock_name">Clock Name</data>
-<data tcl_name="req_freq">Req Freq</data>
-<data tcl_name="est_freq">Est Freq</data>
-<data tcl_name="slack">Slack</data>
-</row>
-<row>
-<data>serdes_sync_1|pll_refclki</data>
-<data>100.0 MHz</data>
-<data>168.9 MHz</data>
-<data>4.079</data>
-</row>
-<row>
-<data>serdes_sync_1|rxrefclk</data>
-<data>100.0 MHz</data>
-<data>170.5 MHz</data>
-<data>4.136</data>
-</row>
-<row>
-<data>serdes_sync_1|tx_pclk_inferred_clock</data>
-<data>100.0 MHz</data>
-<data>237.5 MHz</data>
-<data>5.789</data>
-</row>
-<row>
-<data>System</data>
-<data>100.0 MHz</data>
-<data>840.7 MHz</data>
-<data>8.810</data>
-</row>
-</report_table>
+++ /dev/null
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+++ /dev/null
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8" ?>
-<!-- *************************************************************************************
-FILE DESCRIPTION
-The file contains the job information from mapper to be displayed as part of the summary report.
-*******************************************************************************************-->
-<job_run_status name="Mapper">
-<report_link name="Detailed report">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr</data>
-<title>Synopsys Lattice Technology Pre-mapping</title>
-</report_link>
-<job_status>
-<data>Completed</data>
-</job_status>
-<job_info>
-<info name="Notes">
-<data>8</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt</data>
-</report_link>
-</info>
-<info name="Warnings">
-<data>3</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt</data>
-</report_link>
-</info>
-<info name="Errors">
-<data>0</data>
-<report_link name="more">
-<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt</data>
-</report_link>
-</info>
-<info name="CPU Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Real Time">
-<data>0h:00m:00s</data>
-</info>
-<info name="Peak Memory">
-<data>145MB</data>
-</info>
-<info name="Date & Time">
-<data type="timestamp">1557476614</data>
-</info>
-</job_info>
-</job_run_status>
+++ /dev/null
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
+++ /dev/null
-Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 10:23:30 2019
-
-###########################################################]
-Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
-Verilog syntax check successful!
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
-
-
-Process completed successfully.
-# Fri May 10 10:23:31 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
-@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
-File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
-VHDL syntax check successful!
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
-@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
-Post processing for work.serdes_sync_1.v1
-
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
-
-
-Process completed successfully.
-# Fri May 10 10:23:31 2019
-
-###########################################################]
-Running on host :lxhadeb07
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
-@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
-@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
-Verilog syntax check successful!
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
-
- PDATA_RST_VAL=32'b00000000000000000000000000000000
- Generated name = sync_0s
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
-
- PPROTOCOL=48'b010001110011100001000010001100010011000001000010
- PLOL_SETTING=32'b00000000000000000000000000000001
- PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
- PPCIE_MAX_RATE=24'b001100100010111000110101
- PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
- PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
- PPCLK_TC=32'b00000000000000100000000000000000
- PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
- PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
- PPCLK_DIV11_TC=32'b00000000000000000000000000000000
- LPLL_LOSS_ST=2'b00
- LPLL_PRELOSS_ST=2'b01
- LPLL_PRELOCK_ST=2'b10
- LPLL_LOCK_ST=2'b11
- LRCLK_TC=16'b1111111111111111
- LRCLK_TC_PUL_WIDTH=16'b0000000000110010
- LHB_WAIT_CNT=8'b11111111
- LPCLK_TC_0=32'b00000000000000001000000000000000
- LPCLK_TC_1=32'b00000000000000010000000000000000
- LPCLK_TC_2=32'b00000000000000100000000000000000
- LPCLK_TC_3=32'b00000000000000101000000000000000
- LPCLK_TC_4=32'b00000000000000010000000000000000
- LPDIFF_LOCK_00=32'b00000000000000000000000000001001
- LPDIFF_LOCK_10=32'b00000000000000000000000000010011
- LPDIFF_LOCK_20=32'b00000000000000000000000000100111
- LPDIFF_LOCK_30=32'b00000000000000000000000000110001
- LPDIFF_LOCK_40=32'b00000000000000000000000000010011
- LPDIFF_LOCK_01=32'b00000000000000000000000000001001
- LPDIFF_LOCK_11=32'b00000000000000000000000000010011
- LPDIFF_LOCK_21=32'b00000000000000000000000000100111
- LPDIFF_LOCK_31=32'b00000000000000000000000000110001
- LPDIFF_LOCK_41=32'b00000000000000000000000000010011
- LPDIFF_LOCK_02=32'b00000000000000000000000000110001
- LPDIFF_LOCK_12=32'b00000000000000000000000001100010
- LPDIFF_LOCK_22=32'b00000000000000000000000011000100
- LPDIFF_LOCK_32=32'b00000000000000000000000011110101
- LPDIFF_LOCK_42=32'b00000000000000000000000001100010
- LPDIFF_LOCK_03=32'b00000000000000000000000010000011
- LPDIFF_LOCK_13=32'b00000000000000000000000100000110
- LPDIFF_LOCK_23=32'b00000000000000000000001000001100
- LPDIFF_LOCK_33=32'b00000000000000000000001010001111
- LPDIFF_LOCK_43=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
- LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
- LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
- LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
- LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
- LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
- LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
- LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
- LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
- LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
- LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
- LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
- LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
- LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
- LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
- LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
- LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
- Generated name = serdes_sync_1sll_core_Z1_layer1
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
-@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-Could not match passed parameter, trying a case insensitive search ...
-@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
-
- pnum_channels=32'b00000000000000000000000000000001
- pprotocol=48'b010001110011100001000010001100010011000001000010
- pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
- pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_tx_rdy=32'b00000000000000000000101110111000
- pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
- pwait_rx_rdy=32'b00000000000000000000101110111000
- wa_num_cycles=32'b00000000000000000000010000000000
- dac_num_cycles=32'b00000000000000000000000000000011
- lreset_pwidth=32'b00000000000000000000000000000011
- lwait_b4_trst=32'b00000000000010111110101111000010
- lwait_b4_trst_s=32'b00000000000000000000001100001101
- lplol_cnt_width=32'b00000000000000000000000000010100
- lwait_after_plol0=32'b00000000000000000000000000000100
- lwait_b4_rrst=32'b00000000000000101100000000000000
- lrrst_wait_width=32'b00000000000000000000000000010100
- lwait_after_rrst=32'b00000000000011000011010100000000
- lwait_b4_rrst_s=32'b00000000000000000000000111001100
- lrlol_cnt_width=32'b00000000000000000000000000010011
- lwait_after_lols=32'b00000000000000001100010000000000
- lwait_after_lols_s=32'b00000000000000000000000010010110
- llols_cnt_width=32'b00000000000000000000000000010010
- lrdb_max=32'b00000000000000000000000000001111
- ltxr_wait_width=32'b00000000000000000000000000001100
- lrxr_wait_width=32'b00000000000000000000000000001100
- Generated name = serdes_sync_1rsl_core_Z2_layer1
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
-@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
-@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
-@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
-Extracted state machine for register sll_state
-State machine has 3 reachable states with original encodings of:
- 00
- 01
- 11
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
-
-
-Process completed successfully.
-# Fri May 10 10:23:32 2019
-
-###########################################################]
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
-
-=======================================================================================
-For a summary of linker messages for components that did not bind, please see log file:
-@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
-=======================================================================================
-
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 10:23:32 2019
-
-###########################################################]
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 10:23:32 2019
-
-###########################################################]
+++ /dev/null
-./synlog/serdes_sync_1_compiler.srr,serdes_sync_1_compiler.srr,Compile Log
+++ /dev/null
-# Fri May 10 10:23:34 2019
-
-Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
-
-
-Available hyper_sources - for debug and ip models
- None Found
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 11 -> 10
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0]
-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
-@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
-
-
-Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
-
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
-
-Pass CPU time Worst Slack Luts / Registers
-------------------------------------------------------------
- 1 0h:00m:01s 5.35ns 151 / 220
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
-
-
-
-@S |Clock Optimization Summary
-
-
-#### START OF CLOCK OPTIMIZATION REPORT #####[
-
-3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-============================================= Non-Gated/Non-Generated Clocks =============================================
-Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------------------------------------------
-@K:CKID0001 pll_refclki port 90 rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
-@K:CKID0002 rxrefclk port 77 rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
-@K:CKID0003 DCU0_inst DCUA 53 sll_inst.pcount_diff[21]
-==========================================================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######]
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
-
-Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
-M-2017.03L-SP1-1
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
-
-Writing Verilog Simulation files
-
-Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
-
-Writing VHDL Simulation files
-
-Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
-
-@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
-@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
-@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
-
-
-##### START OF TIMING REPORT #####[
-# Timing Report written on Fri May 10 10:23:38 2019
-#
-
-
-Top view: serdes_sync_1
-Requested Frequency: 100.0 MHz
-Wire load mode: top
-Paths requested: 5
-Constraint File(s): /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
-
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 4.079
-
-@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
- Requested Estimated Requested Estimated Clock Clock
-Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------------------------
-serdes_sync_1|pll_refclki 100.0 MHz 168.9 MHz 10.000 5.921 4.079 inferred Inferred_clkgroup_0
-serdes_sync_1|rxrefclk 100.0 MHz 170.5 MHz 10.000 5.864 4.136 inferred Inferred_clkgroup_1
-serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 237.5 MHz 10.000 4.211 5.789 inferred Inferred_clkgroup_2
-System 100.0 MHz 840.7 MHz 10.000 1.190 8.810 system system_clkgroup
-===========================================================================================================================================
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-System System | 10.000 10.000 | No paths - | No paths - | No paths -
-System serdes_sync_1|rxrefclk | 10.000 8.811 | No paths - | No paths - | No paths -
-serdes_sync_1|pll_refclki System | 10.000 8.307 | No paths - | No paths - | No paths -
-serdes_sync_1|pll_refclki serdes_sync_1|pll_refclki | 10.000 4.079 | No paths - | No paths - | No paths -
-serdes_sync_1|pll_refclki serdes_sync_1|tx_pclk_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
-serdes_sync_1|rxrefclk System | 10.000 8.193 | No paths - | No paths - | No paths -
-serdes_sync_1|rxrefclk serdes_sync_1|rxrefclk | 10.000 4.136 | No paths - | No paths - | No paths -
-serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|pll_refclki | Diff grp - | No paths - | No paths - | No paths -
-serdes_sync_1|tx_pclk_inferred_clock serdes_sync_1|tx_pclk_inferred_clock | 10.000 5.789 | No paths - | No paths - | No paths -
-===================================================================================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
- 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: serdes_sync_1|pll_refclki
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[1] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[6] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[6] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[7] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[7] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[12] 0.907 4.079
-rsl_inst.genblk1\.plol_cnt[2] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[2] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[3] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[3] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[4] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[4] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[5] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[5] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[8] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[8] 0.907 4.684
-rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX Q plol_cnt[9] 0.907 4.684
-=======================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[19] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[19] 9.946 4.079
-rsl_inst.genblk1\.plol_cnt[17] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[17] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[18] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[18] 9.946 4.139
-rsl_inst.genblk1\.plol_cnt[15] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[15] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[16] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[16] 9.946 4.200
-rsl_inst.genblk1\.plol_cnt[13] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[13] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[14] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[14] 9.946 4.261
-rsl_inst.genblk1\.plol_cnt[11] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[11] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[12] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[12] 9.946 4.322
-rsl_inst.genblk1\.plol_cnt[9] serdes_sync_1|pll_refclki FD1S3DX D plol_cnt_s[9] 9.946 4.383
-==========================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.867
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (critical) : 4.079
-
- Number of logic level(s): 15
- Starting point: rsl_inst.genblk1\.plol_cnt[1] / Q
- Ending point: rsl_inst.genblk1\.plol_cnt[19] / D
- The start point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK
- The end point is clocked by serdes_sync_1|pll_refclki [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
-rsl_inst.genblk1\.plol_cnt[1] FD1S3DX Q Out 0.907 0.907 -
-plol_cnt[1] Net - - - - 2
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_10 ORCALUT4 Z Out 0.606 1.513 -
-un1_plol_cnt_tc_10 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.genblk1\.un1_plol_cnt_tc_14 ORCALUT4 Z Out 0.606 2.119 -
-un1_plol_cnt_tc_14 Net - - - - 1
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 D In 0.000 2.119 -
-rsl_inst.genblk1\.un1_plol_cnt_tc ORCALUT4 Z Out 0.762 2.881 -
-un1_plol_cnt_tc Net - - - - 5
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 B In 0.000 2.881 -
-rsl_inst.genblk1\.plol_cnt11_i ORCALUT4 Z Out 0.840 3.721 -
-plol_cnt Net - - - - 21
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C A1 In 0.000 3.721 -
-rsl_inst.genblk1\.plol_cnt_cry_0[0] CCU2C COUT Out 0.900 4.621 -
-plol_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C CIN In 0.000 4.621 -
-rsl_inst.genblk1\.plol_cnt_cry_0[1] CCU2C COUT Out 0.061 4.682 -
-plol_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C CIN In 0.000 4.682 -
-rsl_inst.genblk1\.plol_cnt_cry_0[3] CCU2C COUT Out 0.061 4.743 -
-plol_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C CIN In 0.000 4.743 -
-rsl_inst.genblk1\.plol_cnt_cry_0[5] CCU2C COUT Out 0.061 4.804 -
-plol_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C CIN In 0.000 4.804 -
-rsl_inst.genblk1\.plol_cnt_cry_0[7] CCU2C COUT Out 0.061 4.865 -
-plol_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C CIN In 0.000 4.865 -
-rsl_inst.genblk1\.plol_cnt_cry_0[9] CCU2C COUT Out 0.061 4.926 -
-plol_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C CIN In 0.000 4.926 -
-rsl_inst.genblk1\.plol_cnt_cry_0[11] CCU2C COUT Out 0.061 4.987 -
-plol_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C CIN In 0.000 4.987 -
-rsl_inst.genblk1\.plol_cnt_cry_0[13] CCU2C COUT Out 0.061 5.048 -
-plol_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C CIN In 0.000 5.048 -
-rsl_inst.genblk1\.plol_cnt_cry_0[15] CCU2C COUT Out 0.061 5.109 -
-plol_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C CIN In 0.000 5.109 -
-rsl_inst.genblk1\.plol_cnt_cry_0[17] CCU2C COUT Out 0.061 5.170 -
-plol_cnt_cry[18] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C CIN In 0.000 5.170 -
-rsl_inst.genblk1\.plol_cnt_s_0[19] CCU2C S0 Out 0.698 5.867 -
-plol_cnt_s[19] Net - - - - 1
-rsl_inst.genblk1\.plol_cnt[19] FD1S3DX D In 0.000 5.867 -
-=======================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: serdes_sync_1|rxrefclk
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
-------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[14] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[15] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[16] 0.907 4.136
-rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[17] 0.907 4.136
-rsl_inst.genblk2\.rlols0_cnt[9] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[9] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[11] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[11] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[12] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[12] 0.907 4.170
-rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX Q rlols0_cnt[13] 0.907 4.170
-rsl_inst.genblk2\.rlol1_cnt[0] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[0] 0.907 4.742
-rsl_inst.genblk2\.rlol1_cnt[1] serdes_sync_1|rxrefclk FD1P3DX Q rlol1_cnt[1] 0.907 4.742
-========================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[17] 9.946 4.136
-rsl_inst.genblk2\.rlol1_cnt[18] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[18] 9.946 4.136
-rsl_inst.genblk2\.rlols0_cnt[17] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[17] 9.946 4.170
-rsl_inst.genblk2\.rlol1_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[15] 9.946 4.197
-rsl_inst.genblk2\.rlol1_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[16] 9.946 4.197
-rsl_inst.genblk2\.rlols0_cnt[15] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[15] 9.946 4.231
-rsl_inst.genblk2\.rlols0_cnt[16] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[16] 9.946 4.231
-rsl_inst.genblk2\.rlol1_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[13] 9.946 4.258
-rsl_inst.genblk2\.rlol1_cnt[14] serdes_sync_1|rxrefclk FD1P3DX D rlol1_cnt_s[14] 9.946 4.258
-rsl_inst.genblk2\.rlols0_cnt[13] serdes_sync_1|rxrefclk FD1P3DX D rlols0_cnt_s[13] 9.946 4.292
-===========================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 5.809
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 4.136
-
- Number of logic level(s): 14
- Starting point: rsl_inst.genblk2\.rlol1_cnt[14] / Q
- Ending point: rsl_inst.genblk2\.rlol1_cnt[18] / D
- The start point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK
- The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.rlol1_cnt[14] FD1P3DX Q Out 0.907 0.907 -
-rlol1_cnt[14] Net - - - - 2
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 A In 0.000 0.907 -
-rsl_inst.rlol1_cnt_tc_1_10 ORCALUT4 Z Out 0.606 1.513 -
-rlol1_cnt_tc_1_10 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 D In 0.000 1.513 -
-rsl_inst.rlol1_cnt_tc_1_14 ORCALUT4 Z Out 0.606 2.119 -
-rlol1_cnt_tc_1_14 Net - - - - 1
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 D In 0.000 2.119 -
-rsl_inst.rlol1_cnt_tc_1 ORCALUT4 Z Out 0.768 2.887 -
-rlol1_cnt_tc_1 Net - - - - 6
-rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 A In 0.000 2.887 -
-rsl_inst.genblk2\.rlos_db_p1_RNIS0OP ORCALUT4 Z Out 0.837 3.724 -
-rlol1_cnt Net - - - - 20
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C A1 In 0.000 3.724 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[0] CCU2C COUT Out 0.900 4.624 -
-rlol1_cnt_cry[0] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C CIN In 0.000 4.624 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[1] CCU2C COUT Out 0.061 4.685 -
-rlol1_cnt_cry[2] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C CIN In 0.000 4.685 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[3] CCU2C COUT Out 0.061 4.746 -
-rlol1_cnt_cry[4] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C CIN In 0.000 4.746 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[5] CCU2C COUT Out 0.061 4.807 -
-rlol1_cnt_cry[6] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C CIN In 0.000 4.807 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[7] CCU2C COUT Out 0.061 4.868 -
-rlol1_cnt_cry[8] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C CIN In 0.000 4.868 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[9] CCU2C COUT Out 0.061 4.929 -
-rlol1_cnt_cry[10] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C CIN In 0.000 4.929 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[11] CCU2C COUT Out 0.061 4.990 -
-rlol1_cnt_cry[12] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C CIN In 0.000 4.990 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[13] CCU2C COUT Out 0.061 5.051 -
-rlol1_cnt_cry[14] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C CIN In 0.000 5.051 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[15] CCU2C COUT Out 0.061 5.112 -
-rlol1_cnt_cry[16] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C CIN In 0.000 5.112 -
-rsl_inst.genblk2\.rlol1_cnt_cry_0[17] CCU2C S1 Out 0.698 5.809 -
-rlol1_cnt_s[18] Net - - - - 1
-rsl_inst.genblk2\.rlol1_cnt[18] FD1P3DX D In 0.000 5.809 -
-========================================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p1 1.098 5.789
-sll_inst.ppul_sync_p2 serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q ppul_sync_p2 1.098 5.789
-sll_inst.pcount_diff[0] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_0 0.985 6.147
-sll_inst.pcount[0] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[0] 0.955 6.178
-sll_inst.pcount_diff[1] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_1 0.955 6.239
-sll_inst.pcount_diff[2] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_2 0.955 6.239
-sll_inst.pcount[1] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[1] 0.907 6.287
-sll_inst.pcount[2] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX Q pcount[2] 0.907 6.287
-sll_inst.pcount_diff[3] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_3 0.955 6.300
-sll_inst.pcount_diff[4] serdes_sync_1|tx_pclk_inferred_clock FD1P3BX Q un13_lock_4 0.955 6.300
-===========================================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
---------------------------------------------------------------------------------------------------------------------------------------------
-sll_inst.pcount[21] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[21] 9.946 5.789
-sll_inst.pcount[19] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[19] 9.946 5.850
-sll_inst.pcount[20] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[20] 9.946 5.850
-sll_inst.pcount[17] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[17] 9.946 5.911
-sll_inst.pcount[18] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[18] 9.946 5.911
-sll_inst.pcount[15] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[15] 9.946 5.972
-sll_inst.pcount[16] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[16] 9.946 5.972
-sll_inst.pcount[13] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[13] 9.946 6.033
-sll_inst.pcount[14] serdes_sync_1|tx_pclk_inferred_clock FD1S3DX D pcount_s[14] 9.946 6.033
-sll_inst.pcount_diff[21] serdes_sync_1|tx_pclk_inferred_clock FD1P3DX D un1_pcount_diff_1_s_21_0_S0 9.946 6.034
-============================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.054
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.946
-
- - Propagation time: 4.157
- - Clock delay at starting point: 0.000 (ideal)
- = Slack (non-critical) : 5.789
-
- Number of logic level(s): 13
- Starting point: sll_inst.ppul_sync_p1 / Q
- Ending point: sll_inst.pcount[21] / D
- The start point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
- The end point is clocked by serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
-sll_inst.ppul_sync_p1 FD1S3DX Q Out 1.098 1.098 -
-ppul_sync_p1 Net - - - - 25
-sll_inst.pcount10_0_o3 ORCALUT4 A In 0.000 1.098 -
-sll_inst.pcount10_0_o3 ORCALUT4 Z Out 0.851 1.950 -
-N_8 Net - - - - 25
-sll_inst.pcount_cry_0[0] CCU2C A1 In 0.000 1.950 -
-sll_inst.pcount_cry_0[0] CCU2C COUT Out 0.900 2.850 -
-pcount_cry[0] Net - - - - 1
-sll_inst.pcount_cry_0[1] CCU2C CIN In 0.000 2.850 -
-sll_inst.pcount_cry_0[1] CCU2C COUT Out 0.061 2.911 -
-pcount_cry[2] Net - - - - 1
-sll_inst.pcount_cry_0[3] CCU2C CIN In 0.000 2.911 -
-sll_inst.pcount_cry_0[3] CCU2C COUT Out 0.061 2.972 -
-pcount_cry[4] Net - - - - 1
-sll_inst.pcount_cry_0[5] CCU2C CIN In 0.000 2.972 -
-sll_inst.pcount_cry_0[5] CCU2C COUT Out 0.061 3.033 -
-pcount_cry[6] Net - - - - 1
-sll_inst.pcount_cry_0[7] CCU2C CIN In 0.000 3.033 -
-sll_inst.pcount_cry_0[7] CCU2C COUT Out 0.061 3.094 -
-pcount_cry[8] Net - - - - 1
-sll_inst.pcount_cry_0[9] CCU2C CIN In 0.000 3.094 -
-sll_inst.pcount_cry_0[9] CCU2C COUT Out 0.061 3.155 -
-pcount_cry[10] Net - - - - 1
-sll_inst.pcount_cry_0[11] CCU2C CIN In 0.000 3.155 -
-sll_inst.pcount_cry_0[11] CCU2C COUT Out 0.061 3.216 -
-pcount_cry[12] Net - - - - 1
-sll_inst.pcount_cry_0[13] CCU2C CIN In 0.000 3.216 -
-sll_inst.pcount_cry_0[13] CCU2C COUT Out 0.061 3.277 -
-pcount_cry[14] Net - - - - 1
-sll_inst.pcount_cry_0[15] CCU2C CIN In 0.000 3.277 -
-sll_inst.pcount_cry_0[15] CCU2C COUT Out 0.061 3.338 -
-pcount_cry[16] Net - - - - 1
-sll_inst.pcount_cry_0[17] CCU2C CIN In 0.000 3.338 -
-sll_inst.pcount_cry_0[17] CCU2C COUT Out 0.061 3.399 -
-pcount_cry[18] Net - - - - 1
-sll_inst.pcount_cry_0[19] CCU2C CIN In 0.000 3.399 -
-sll_inst.pcount_cry_0[19] CCU2C COUT Out 0.061 3.460 -
-pcount_cry[20] Net - - - - 1
-sll_inst.pcount_s_0[21] CCU2C CIN In 0.000 3.460 -
-sll_inst.pcount_s_0[21] CCU2C S0 Out 0.698 4.157 -
-pcount_s[21] Net - - - - 1
-sll_inst.pcount[21] FD1S3DX D In 0.000 4.157 -
-============================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
- Starting Arrival
-Instance Reference Type Pin Net Time Slack
- Clock
--------------------------------------------------------------------------------------------
-DCU0_inst System DCUA CH0_FFS_RLOL rx_cdr_lol_s 0.000 8.810
-DCU0_inst System DCUA CH0_FFS_RLOS rx_los_low_s 0.000 8.810
-DCU0_inst System DCUA CH0_FF_RX_PCLK rx_pclk 0.000 10.000
-===========================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
- Starting Required
-Instance Reference Type Pin Net Time Slack
- Clock
----------------------------------------------------------------------------------------------------------------------------------------------------------
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX SP un2_rdo_serdes_rst_dual_c_2_i 9.806 8.810
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] System FD1P3DX D un2_rdo_serdes_rst_dual_c_1 9.946 9.556
-rsl_inst.genblk2\.rlol_p1 System FD1S3DX D rx_cdr_lol_s 9.946 9.946
-rsl_inst.genblk2\.rlos_p1 System FD1S3DX D rx_los_low_s 9.946 9.946
-DCU0_inst System DCUA CH0_FF_RXI_CLK rx_pclk 10.000 10.000
-=========================================================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1:
- Requested Period: 10.000
- - Setup time: 0.194
- + Clock delay at ending point: 0.000 (ideal)
- = Required time: 9.806
-
- - Propagation time: 0.996
- - Clock delay at starting point: 0.000 (ideal)
- - Estimated clock delay at start point: -0.000
- = Slack (non-critical) : 8.810
-
- Number of logic level(s): 2
- Starting point: DCU0_inst / CH0_FFS_RLOL
- Ending point: rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
- The start point is clocked by System [rising]
- The end point is clocked by serdes_sync_1|rxrefclk [rising] on pin CK
-
-Instance / Net Pin Pin Arrival No. of
-Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------
-DCU0_inst DCUA CH0_FFS_RLOL Out 0.000 0.000 -
-rx_cdr_lol_s Net - - - - 4
-rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 B In 0.000 0.000 -
-rsl_inst.un2_rdo_serdes_rst_dual_c_2_0 ORCALUT4 Z Out 0.606 0.606 -
-un2_rdo_serdes_rst_dual_c_2_0 Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 B In 0.000 0.606 -
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0] ORCALUT4 Z Out 0.390 0.996 -
-un2_rdo_serdes_rst_dual_c_2_i Net - - - - 1
-rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] FD1P3DX SP In 0.000 0.996 -
-=================================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-None
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
-
----------------------------------------
-Resource Usage Report
-Part: lfe5um_25f-6
-
-Register bits: 220 of 24288 (1%)
-PIC Latch: 0
-I/O cells: 0
-
-
-Details:
-CCU2C: 113
-DCUA: 1
-FD1P3BX: 20
-FD1P3DX: 92
-FD1S3BX: 12
-FD1S3DX: 96
-GSR: 1
-INV: 3
-ORCALUT4: 150
-PFUMX: 2
-PUR: 1
-VHI: 6
-VLO: 6
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Fri May 10 10:23:38 2019
-
-###########################################################]
+++ /dev/null
-CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001
-CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002
-CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount_diff[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003
+++ /dev/null
-Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017
-@N|Running in 64-bit mode
-File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Fri May 10 10:23:33 2019
-
-###########################################################]
+++ /dev/null
-# Fri May 10 10:23:33 2019
-
-Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug 4 2017 09:36:35
-Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
-Product Version M-2017.03L-SP1-1
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
-
-Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
-@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt
-Printing clock summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
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-@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
-@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed: 0
-syn_allowed_resources : blockrams=56 set on top level netlist serdes_sync_1
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
-
-
-
-Clock Summary
-******************
-
- Start Requested Requested Clock Clock Clock
-Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------------------------
-0 - System 100.0 MHz 10.000 system system_clkgroup 0
-
-0 - serdes_sync_1|pll_refclki 100.0 MHz 10.000 inferred Inferred_clkgroup_0 92
-
-0 - serdes_sync_1|rxrefclk 100.0 MHz 10.000 inferred Inferred_clkgroup_1 77
-
-0 - serdes_sync_1|tx_pclk_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 53
-=========================================================================================================================
-
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
-
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
-
-Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
-original code -> new code
- 00 -> 00
- 01 -> 01
- 11 -> 10
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
-
-None
-None
-
-Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri May 10 10:23:34 2019
-
-###########################################################]
+++ /dev/null
-./serdes_sync_1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report
+++ /dev/null
-#XMR Information
jspc29 / trb5sc.git / commitdiff
