*** empty log message ***

diff --git a/tdc_test/compile_constraints.pl b/tdc_test/compile_constraints.pl
new file mode 100644 (file)
index 0000000..cd5dc4f
--- /dev/null
+++ b/tdc_test/compile_constraints.pl
@@ -0,0 +1,12 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+my $TOPNAME                      = "trb3_periph";  #Name of top-level entity
+my $BasePath                     = "../base/";     #path to "base" directory
+
+#create full lpf file
+system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+

diff --git a/tdc_test/trb3_central_20111012.bit b/tdc_test/trb3_central_20111012.bit
new file mode 100644 (file)
index 0000000..8e70ba5
Binary files /dev/null and b/tdc_test/trb3_central_20111012.bit differ

diff --git a/tdc_test/trb3_periph.vhd b/tdc_test/trb3_periph.vhd
index b3e45f03f0282049f87d0eff78fc82be028927d2..528f540f58720aa32d1c465be83b5c835630588f 100644 (file)
--- a/tdc_test/trb3_periph.vhd
+++ b/tdc_test/trb3_periph.vhd
@@ -13,7 +13,7 @@ use work.version.all;
 entity trb3_periph is
   port(
     --Clocks
-    CLK_GPLL_LEFT  : in std_logic;      --Clock Manager 1/(2468), 125 MHz
+    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
     CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
     CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
     CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
@@ -404,6 +404,8 @@ begin
       DEBUG_LVL1_HANDLER_OUT      => open
       );
 
+  timing_trg_received_i <= TRIGGER_LEFT;
+
 ---------------------------------------------------------------------------
 -- AddOn
 ---------------------------------------------------------------------------