--- /dev/null
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+my $TOPNAME = "trb3_periph"; #Name of top-level entity
+my $BasePath = "../base/"; #path to "base" directory
+
+#create full lpf file
+system("cp $BasePath/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
entity trb3_periph is
port(
--Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
DEBUG_LVL1_HANDLER_OUT => open
);
+ timing_trg_received_i <= TRIGGER_LEFT;
+
---------------------------------------------------------------------------
-- AddOn
---------------------------------------------------------------------------