signal chnl_out_write_cnt : std_logic_vector( 6 downto 0);
signal FPGA_out_write_cnt : std_logic_vector( 3 downto 0);
- signal docal_debug_out, docal_debug_in : unsigned(31 downto 0);
- signal Debug_Data_min, Debug_Data_max : std_logic_vector(31 downto 0);
+ signal docal_debug_out : unsigned(31 downto 0);
+ signal docal_debug_in : unsigned(31 downto 0);
+ signal Debug_Data_min : std_logic_vector(31 downto 0);
+ signal Debug_Data_max : std_logic_vector(31 downto 0);
+ type array_16_16_t is array (0 to 15) of std_logic_vector(15 downto 0);
+ signal FPGA_mntr_i : array_16_16_t := (others => (others=> '0'));
+ signal FPGA_cnt_mntr : std_logic_vector( 3 downto 0);
+ signal FPGA_mntr : std_logic_vector(15 downto 0);
+ type MinMax_t is array (0 to 15, 0 to 32) of std_logic_vector(19 downto 0);
+ signal MinMax_Monitor : MinMax_t := (others=>(others=>(others=>'0')));
begin
--BUS Handler
BUS_TX.nack <= '0';
BUS_TX.unknown <= '0';
Flash_flag <= '0';
-
+
if BUS_RX.write = '1' then
BUS_TX.ack <= '1';
- if BUS_RX.addr(11 downto 0) > x"006" and BUS_RX.addr(11 downto 0) < x"048" then
+ if BUS_RX.addr(11 downto 0) > x"010" and BUS_RX.addr(11 downto 0) < x"0d0" then
BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(7 downto 0))-7) & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0);
Flash_flag <= '1';
- else
+ elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg
case BUS_RX.addr(11 downto 0) is
when x"000" =>
BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration
BUS_TX.ack <= '0';
BUS_TX.unknown <= '1';
end case;
+ else --monitoring
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
end if;
elsif BUS_RX.read = '1' then
BUS_TX.ack <= '1';
- case BUS_RX.addr(11 downto 0) is
- when x"000" => BUS_TX.data(31 downto 1) <= (others => '0');
- BUS_TX.data( 0) <= BUS_do_Cal;
- when x"001" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
- when x"002" => BUS_TX.data( 3 downto 0) <= Bus_FPGA;
- BUS_TX.data(31 downto 4) <= (others => '0');
- when x"003" => BUS_TX.data( 6 downto 0) <= Bus_Chnl;
- BUS_TX.data(31 downto 7) <= (others => '0');
- when x"004" => BUS_TX.data(31 downto 10) <= (others => '0');
- BUS_TX.data( 9 downto 0) <= Bus_min;
- when x"005" => BUS_TX.data(31 downto 10) <= (others => '0');
- BUS_TX.data( 9 downto 0) <= Bus_max;
- when x"006" => BUS_TX.data <= std_logic_vector(docal_debug_in);
- when x"007" => BUS_TX.data <= std_logic_vector(docal_debug_out);
-
- when x"008" => BUS_TX.data(11 downto 8) <= FPGA_Lim;
- BUS_TX.data(7) <= '0';
- BUS_TX.data( 6 downto 0) <= chnl_Lim;
- BUS_TX.data(31 downto 12) <= (others => '0');
- when x"009" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= std_logic_vector(cal_cnt_in);
- when x"00A" => BUS_TX.data <= Debug_Data_min;
- when x"00B" => BUS_TX.data <= Debug_Data_max;
- when others => BUS_TX.ack <= '0';
- BUS_TX.unknown <= '1';
- end case;
+ if BUS_RX.addr(11 downto 4) = x"00" then
+ case BUS_RX.addr(3 downto 0) is
+ when x"0" => BUS_TX.data(31 downto 1) <= (others => '0');
+ BUS_TX.data( 0) <= BUS_do_Cal;
+ when x"1" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
+ when x"2" => BUS_TX.data( 3 downto 0) <= Bus_FPGA;
+ BUS_TX.data(31 downto 4) <= (others => '0');
+ when x"3" => BUS_TX.data( 6 downto 0) <= Bus_Chnl;
+ BUS_TX.data(31 downto 7) <= (others => '0');
+ when x"4" => BUS_TX.data(31 downto 10) <= (others => '0');
+ BUS_TX.data( 9 downto 0) <= Bus_min;
+ when x"5" => BUS_TX.data(31 downto 10) <= (others => '0');
+ BUS_TX.data( 9 downto 0) <= Bus_max;
+ when x"6" => BUS_TX.data <= std_logic_vector(docal_debug_in);
+ when x"7" => BUS_TX.data <= std_logic_vector(docal_debug_out);
+ when x"8" => BUS_TX.data(11 downto 8) <= FPGA_Lim;
+ BUS_TX.data(7) <= '0';
+ BUS_TX.data( 6 downto 0) <= chnl_Lim;
+ BUS_TX.data(31 downto 12) <= (others => '0');
+ when x"9" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_cnt_in);
+ when x"A" => BUS_TX.data <= Debug_Data_min;
+ when x"B" => BUS_TX.data <= Debug_Data_max;
+ when others => BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end case;
+ elsif BUS_RX.addr(11 downto 4) = x"01" then
+ BUS_TX.data(31 downto 16) <= x"0000";
+ BUS_TX.data(15 downto 0) <= FPGA_mntr_i(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
+ elsif (BUS_RX.addr(11 downto 4) = x"02" or BUS_RX.addr(11 downto 4) = x"03") then --ch 0
+ BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(3 downto 0))),0);
+ elsif (BUS_RX.addr(11 downto 4) > x"03") and (BUS_RX.addr(11 downto 4) < x"20") then
+ BUS_TX.data(31 downto 20) <= (others => '0');
+ if BUS_RX.addr(4) = '0' then -- ch1 to ch 16
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),to_integer(unsigned(BUS_RX.addr(3 downto 0)) + 1));
+ else--ch17 to ch 32
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),to_integer(unsigned(BUS_RX.addr(3 downto 0)) + 17));
+ end if;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
end if;
end process;
+
+ THE_MONITOR_FPGA_ID : process
+ begin
+ wait until rising_edge(CLK);
+ FPGA_mntr_i(to_integer(unsigned(FPGA_cnt_mntr))) <= FPGA_mntr;
+ end process;
read_cntr : entity work.read_cnt
DOUT_ready => DIN_o_cnt_ready,
DOUT_type => DIN_o_cnt_type,
Do_Cal => Do_Cal_read_cnt,
- FPGA_cnt_mntr => open,
- FPGA_mntr => open
+ FPGA_cnt_mntr => FPGA_cnt_mntr,
+ FPGA_mntr => FPGA_mntr
);
cal_cnt_out => cal_cnt_out,
DIN => DIN_o_cnt,
DIN_ready => DIN_o_cnt_ready,
- DIN_type => DIN_o_cnt_type,
- DOUT => DIN_o_cnt_val,
- DOUT_ready => DIN_o_cnt_val_ready,
- DOUT_type => DIN_o_cnt_val_type--,
+ DIN_type => DIN_o_cnt_type--,
+ --DOUT => DIN_o_cnt_val,
+ --DOUT_ready => DIN_o_cnt_val_ready,
+ --DOUT_type => DIN_o_cnt_val_type--,
-- FPGA_out => open,
-- CHNL_out => open
);
--- ent_dflt_val : entity work.dflt_val
--- port map(
--- CLK => CLK,
--- read => read_compare_old,
--- FPGA_read => FPGA_o_cnt,
--- chnl_read => chnl_read_cnt,
--- dflt_out => Default_val_Mem
--- );
---
Mem_next : entity work.Memory
port map(
Do_Cal_out => do_cal_LIM,
chnl_cnt_out => cal_cnt_in,
write_chnl_cnt => write_chnl_cnt,
- cal_Limit_set => cal_Limit_set--,
- --Debug_Data_min => Debug_Data_min,
- --Debug_Data_max => Debug_Data_max
+ cal_Limit_set => cal_Limit_set,
+ Debug_Data_min => Debug_Data_min,
+ Debug_Data_max => Debug_Data_max
);
overshoot => overshoot_LUT,
undershoot => undershoot_LUT
);
-
+
Calc_Output : entity work.calc_output
port map(
CLK => CLK,
end if;
end if;
end process;
-
-
+
+ Calib_monitor : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if do_cal_LIM = '1' then
+ MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim)))( 9 downto 0) <= min_out_Lim;
+ MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim)))(19 downto 10) <= max_out_Lim;
+ end if;
+ end if;
+ end process;
+
+
TX_statusbits : process (CLK)
begin
if rising_edge(CLK) then
architecture Behavioral of read_cnt is
- type t_Fpga is array (0 to 11) of std_logic_vector(15 downto 0);
- signal FPGA_num : t_Fpga;
- signal cnt : integer range 0 to 11 := 0;
- signal FPGA_i : integer range 0 to 11 := 0;
- signal save : std_logic_vector(11 downto 0);
+ type t_Fpga is array (0 to 15) of std_logic_vector(15 downto 0);
+ signal FPGA_num : t_Fpga := (others => (others => '0'));
+ signal cnt : integer range 0 to 15 := 0;
+ signal FPGA_i : integer range 0 to 15 := 0;
+ --signal save : std_logic_vector(11 downto 0);
begin
if (DIN(31) = '1') and (DIN_type = x"4") and (DIN_ready = '1') then
chnl <= DIN(28 downto 22);
FPGA_out <= std_logic_vector(to_unsigned(FPGA_i,4));
- if DIN(21 downto 12) /= "1111111111" and FPGA_in(15 downto 12) = x"1" then --3FF
+ if DIN(21 downto 12) /= "1111111111" and FPGA_in(15 downto 12) = x"1" then --3FF --toDO: without 15 downto 12
Do_Cal <= '1';
else
Do_Cal <= '0';
THE_FPGA_num : process(CLK)
- variable position : std_logic_vector(3 downto 0);
+ variable position : std_logic_vector( 3 downto 0);
+ variable save : std_logic_vector(11 downto 0) := X"000";
begin
position := x"f";
if RESET = '1' then
cnt <= 0;
else
--- if DIN_ready = '1' then
--- C1 : case FPGA_in is
--- when x"156d" => FPGA_i <= 0;
--- when x"1691" => FPGA_i <= 1;
--- when x"13f9" => FPGA_i <= 2;
--- when x"12ee" => FPGA_i <= 3;
--- when x"12f8" => FPGA_i <= 4;
--- when x"1403" => FPGA_i <= 5;
--- when x"1663" => FPGA_i <= 6;
--- when others => FPGA_i <= 7;
--- end case C1;
--- end if;
- for i in 0 to 11 loop
- if FPGA_in = FPGA_num(i) then
- save(i) <= '1';
+ if DIN_ready = '1' then
+ for i in 0 to 11 loop
+ if FPGA_in = FPGA_num(i) then
+ save(i) := '1';
+ else
+ save(i) := '0';
+ end if;
+ end loop;
+
+ if save(11 downto 4) = x"00" then
+ if save(3 downto 0) = x"0" then
+ FPGA_i <= cnt;
+ FPGA_num(cnt) <= FPGA_in;
+ cnt <= cnt + 1;
+ elsif save(0) = '1' then
+ FPGA_i <= 0;
+ elsif save(1) = '1' then
+ FPGA_i <= 1;
+ elsif save(2) = '1' then
+ FPGA_i <= 2;
+ elsif save(3) = '1' then
+ FPGA_i <= 3;
+ else
+ --ERROR
+ end if;
+ elsif save(11 downto 8) = x"0" and save(3 downto 0) = x"0" then
+ if save(4) = '1' then
+ FPGA_i <= 4;
+ elsif save(5) = '1' then
+ FPGA_i <= 5;
+ elsif save(6) = '1' then
+ FPGA_i <= 6;
+ elsif save(7) = '1' then
+ FPGA_i <= 7;
+ else
+ --ERROR
+ end if;
+ elsif save(7 downto 0) = x"00" then
+ if save(8) = '1' then
+ FPGA_i <= 8;
+ elsif save(9) = '1' then
+ FPGA_i <= 9;
+ elsif save(10) = '1' then
+ FPGA_i <= 10;
+ elsif save(11) = '1' then
+ FPGA_i <= 11;
+ else
+ --ERROR
+ end if;
else
- save(i) <= '0';
- end if;
- end loop;
-
- for i in 0 to 11 loop
- if save(i) = '1' then
- position := position and std_logic_vector(to_unsigned(i,4));
- end if;
- end loop;
-
- if position = x"f" then
- FPGA_i <= cnt;
- FPGA_num(cnt) <= FPGA_in;
- cnt <= cnt + 1;
- else
- FPGA_i <= to_integer(unsigned(position));
- end if;
+ --ERROR
+ end if;
+ end if;
end if;
+ FPGA_mntr <= FPGA_num(FPGA_i);
+ FPGA_cnt_mntr <= std_logic_vector(to_unsigned(FPGA_i,4));
end if;
end process;
- FPGA_mntr <= FPGA_num(cnt);
- FPGA_cnt_mntr <= std_logic_vector(to_unsigned(cnt,4));
-
end Behavioral;
\ No newline at end of file
jspc29 / dirich.git / commitdiff