fixed bugs in RX_LSM

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 53621cdd37ae0b2da3545291e62884022e537221..30ebef43835b05e441b4482ac21747a5a32758a0 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -496,7 +496,7 @@ end generate;
       -- WAP
       WA_POS_OUT  => wa_position_i,
       WA_READ_OUT => wa_read_i, --open,
-      LINK_RX_READY_IN => '0', -- BUG
+      LINK_RX_READY_IN => '0', -- NOT REALLY NEEDED
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,
@@ -517,14 +517,9 @@ end generate;
   STAT_DEBUG(3 downto 0)   <= clk_rx_full(3 downto 0);
   STAT_DEBUG(7 downto 4)   <= clk_tx_full(3 downto 0);
   STAT_DEBUG(63 downto 8)  <= (others => '0');
-  
+
+  -- SerDes #3 is used for debugging
   DEBUG_OUT <= debug_i(3*32+31 downto 3*32);
---  DEBUG_OUT(11 downto 0)  <= debug_i(3*32+11 downto 3*32);
---  DEBUG_OUT(12)           <= debug_i(3*32+12); --debug_tx_control_i(3*32+4);
---  DEBUG_OUT(13)           <= debug_i(3*32+13); --debug_tx_control_i(3*32+5);
---  DEBUG_OUT(14)           <= debug_i(3*32+14); --debug_tx_control_i(3*32+30);
---  DEBUG_OUT(15)           <= debug_i(3*32+15); --debug_tx_control_i(3*32+31);
---  DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16);
   
 end architecture;
 

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index fc1dd569e290dc2809e3ad3050269033264d20fb..e2a31da1a50c0641d1d87acde6a054aec7d9ee08 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -155,9 +155,9 @@ begin
       SD_LOS_IN         => SFP_LOS_IN,
       WAP_ZERO_IN       => is_wap_zero_i,
       -- outputs
-      RX_SERDES_RST_OUT => rx_serdes_rst_i,
-      RX_PCS_RST_OUT    => rx_pcs_rst_i,
-      LINK_RX_READY_OUT => link_rx_ready_i,
+      RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based
+      RX_PCS_RST_OUT    => rx_pcs_rst_i, -- CLK_REF based
+      LINK_RX_READY_OUT => link_rx_ready_i, -- CLK_REF based
       STATE_OUT         => rx_fsm_state
     );
 
@@ -220,8 +220,8 @@ begin
       CLK_RXI                => CLK_RXI,
       RX_K_IN                => RX_K_IN,
       RX_DATA_IN             => RX_DATA_IN,
-      LINK_HALF_DONE_OUT     => link_half_done_i,
-      LINK_FULL_DONE_OUT     => link_full_done_i,
+      LINK_HALF_DONE_OUT     => link_half_done_i, -- CLK_RXI based
+      LINK_FULL_DONE_OUT     => link_full_done_i, -- CLK_RXI based
       STATE_OUT              => rx_lsm_state --open
     );
 
@@ -317,7 +317,7 @@ begin
   
   link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1')) 
                  else x"7";
-
+                 
   SYNC_MEDIA_SIGS : entity work.signal_sync
     generic map(
       WIDTH => 6,

diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd
index 9bcfcbb550f99c9fb68cfa9b08b481b7b132e309..82aa3436a057d6031e6be0166b19953145d2df07 100644 (file)
--- a/media_interfaces/sync/rx_control_RS.vhd
+++ b/media_interfaces/sync/rx_control_RS.vhd
@@ -30,8 +30,8 @@ entity rx_control_RS is
     RX_RST_WORD_OUT                : out std_logic_vector(7 downto 0);\r
     -- link status signals\r
     LINK_RX_READY_IN               : in  std_logic;\r
-    LINK_TX_READY_IN               : in  std_logic;\r
-    LINK_HALF_DONE_IN              : in  std_logic;\r
+    LINK_TX_READY_IN               : in  std_logic; -- unused\r
+    LINK_HALF_DONE_IN              : in  std_logic; -- unused\r
     LINK_FULL_DONE_IN              : in  std_logic;\r
     -- debug\r
     DEBUG_OUT                      : out std_logic_vector(31 downto 0);\r

diff --git a/media_interfaces/sync/rx_lsm_RS.vhd b/media_interfaces/sync/rx_lsm_RS.vhd
index 7e9bbe7ade1598ce745c4a33f2ac93fdc0087cf0..85c47579b0a0eb6f2aab68200444ea81009d3bfc 100644 (file)
--- a/media_interfaces/sync/rx_lsm_RS.vhd
+++ b/media_interfaces/sync/rx_lsm_RS.vhd
@@ -26,10 +26,12 @@ architecture rx_lsm_arch of rx_lsm_RS is
   \r
   signal reset_ctr_t            : std_logic;\r
   signal ce_ctr_t               : std_logic;\r
+  signal ce_ctr_t_q             : std_logic;\r
   signal ctr_t                  : unsigned(4 downto 0);\r
   signal ctr_t_done             : std_logic;\r
   signal reset_ctr_s            : std_logic;\r
   signal ce_ctr_s               : std_logic;\r
+  signal ce_ctr_s_q             : std_logic;\r
   signal ctr_s                  : unsigned(4 downto 0);\r
   signal ctr_s_done             : std_logic;\r
   signal link_toggling_int      : std_logic;\r
@@ -39,15 +41,13 @@ begin
 \r
   THE_CTR_T_PROC: process( CLK_RXI, LINK_RX_READY_IN ) \r
   begin\r
-    if  ( LINK_RX_READY_IN <= '0' ) then\r
+    if( LINK_RX_READY_IN = '0' ) then\r
       ctr_t <= (others => '0');\r
     elsif( rising_edge(CLK_RXI) ) then\r
       if( reset_ctr_t = '1' ) then\r
         ctr_t <= (others => '0');\r
-      else\r
-        if( (ctr_t(4) = '0') and (ce_ctr_t = '1') ) then\r
-          ctr_t <= ctr_t + 1 ;\r
-        end if;\r
+      elsif( (ctr_t_done = '0') and (ce_ctr_t_q = '1') ) then\r
+        ctr_t <= ctr_t + 1 ;\r
       end if;\r
     end if;\r
   end process THE_CTR_T_PROC;\r
@@ -56,15 +56,13 @@ begin
 \r
   THE_CTR_S_PROC: process( CLK_RXI, LINK_RX_READY_IN ) \r
   begin\r
-    if   ( LINK_RX_READY_IN = '0' ) then\r
+    if( LINK_RX_READY_IN = '0' ) then\r
       ctr_s <= (others => '0');\r
     elsif( rising_edge(CLK_RXI) ) then\r
       if( reset_ctr_s = '1' ) then\r
         ctr_s <= (others => '0');\r
-      else\r
-        if( (ctr_s(4) = '0') and (ce_ctr_s = '1') and (ctr_t_done = '1') ) then -- added to make sure correct sequence is done\r
-          ctr_s <= ctr_s + 1 ;\r
-        end if;\r
+      elsif( (ctr_s_done = '0') and (ce_ctr_s_q = '1') and (ctr_t_done = '1') ) then -- added to make sure correct sequence is done\r
+        ctr_s <= ctr_s + 1 ;\r
       end if;\r
     end if;\r
   end process THE_CTR_S_PROC;\r
@@ -74,10 +72,10 @@ begin
   -- toggling idles sequence detected\r
   THE_TOGGLE_DETECTED_PROC: process( CLK_RXI, LINK_RX_READY_IN )\r
   begin\r
-    if   ( LINK_RX_READY_IN = '0' ) then\r
+    if( LINK_RX_READY_IN = '0' ) then\r
       link_toggling_int <= '0';\r
     elsif( rising_edge(CLK_RXI) ) then\r
-      if( ctr_t_done = '1' ) then\r
+      if( (ce_ctr_t_q = '1') and (ctr_t_done = '1') ) then\r
         link_toggling_int <= '1';\r
       end if;   \r
     end if;\r
@@ -88,10 +86,10 @@ begin
   -- steady idles sequence detected\r
   THE_STEADY_DETECTED_PROC: process( CLK_RXI, LINK_RX_READY_IN )\r
   begin\r
-    if   ( LINK_RX_READY_IN = '0' ) then\r
+    if( LINK_RX_READY_IN = '0' ) then\r
       link_steady_int <= '0';\r
     elsif( rising_edge(CLK_RXI) ) then\r
-      if( ctr_s_done = '1' ) then\r
+      if( (ce_ctr_s_q = '1') and (ctr_s_done = '1') ) then\r
         link_steady_int <= '1';\r
       end if;   \r
     end if;\r
@@ -104,10 +102,12 @@ begin
   begin\r
     if( LINK_RX_READY_IN = '0' ) then\r
       CURRENT_STATE <= IDLE;\r
-    else\r
-      if( rising_edge(CLK_RXI) ) then\r
-        CURRENT_STATE <= NEXT_STATE;\r
-      end if;\r
+      ce_ctr_t_q    <= '0';\r
+      ce_ctr_s_q    <= '0';\r
+    elsif( rising_edge(CLK_RXI) ) then\r
+      CURRENT_STATE <= NEXT_STATE;\r
+      ce_ctr_t_q    <= ce_ctr_t;\r
+      ce_ctr_s_q    <= ce_ctr_s;\r
     end if;\r
   end process THE_FSM_PROC;\r
 \r
@@ -152,8 +152,10 @@ begin
         STATE_OUT <= x"3";\r
         if   ( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE1) ) then\r
           NEXT_STATE <= D2FS;\r
+          ce_ctr_s   <= '1';\r
         elsif( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE0) ) then\r
           NEXT_STATE <= D2FT;\r
+          ce_ctr_t   <= '1';\r
         else\r
           NEXT_STATE <= IDLE;\r
         end if;\r
@@ -162,7 +164,6 @@ begin
         STATE_OUT <= x"4";\r
         if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then\r
           NEXT_STATE <= K1F;\r
-          ce_ctr_t <= '1';\r
         else\r
           NEXT_STATE <= IDLE;\r
         end if;\r
@@ -171,7 +172,6 @@ begin
         STATE_OUT <= x"5";\r
         if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then\r
           NEXT_STATE <= K1F;\r
-          ce_ctr_s <= '1';\r
         else\r
           NEXT_STATE <= IDLE;\r
         end if;\r

diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd
index 06bc1be8ab5b7ad07917ef5e0c90c6444ffc271e..dfce0cc20f18be42f7556b96b47e1f2d31892b8f 100644 (file)
--- a/media_interfaces/sync/rx_rsl.vhd
+++ b/media_interfaces/sync/rx_rsl.vhd
@@ -30,9 +30,9 @@ architecture rx_rsl_arc of rx_rsl is
 \r
   constant Tshort     : unsigned(31 downto 0) := x"0000000a";\r
 -- @200MHz 100ms\r
-  constant Tplol      : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
-  constant Tcdr       : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
-  constant Tviol      : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
+  constant Tplol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; \r
+  constant Tcdr       : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; \r
+  constant Tviol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; \r
 \r
   signal pll_lol_s    : std_logic;\r
   signal cdr_lol_s    : std_logic;\r

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index f6799d4b516b302f3df8526533bf578c80421920..607d80970beefae70e0d89e364b8ac66ca326f8e 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -260,9 +260,9 @@ begin
 -- TX control state machine\r
 ----------------------------------------------------------------------\r
 \r
-  THE_DATA_CONTROL_FSM : process(CLK_TXI, LINK_TX_READY_IN, RESET)\r
+  THE_DATA_CONTROL_FSM : process(CLK_TXI, link_tx_ready_qtx, RESET)\r
     begin\r
-      if( (LINK_TX_READY_IN = '0') or (RESET = '1') ) then\r
+      if( RESET = '1' ) then\r
         current_state <= IDLE;\r
         TX_K_OUT    <= '1';\r
         TX_DATA_OUT <= K_NULL;\r
@@ -275,6 +275,17 @@ begin
           debug_sending_dlm <= '0';\r
           debug_sending_rst <= '0';\r
           case current_state is\r
+            when IDLE =>\r
+              TX_K_OUT    <= '1';\r
+              TX_DATA_OUT <= K_NULL;\r
+              word_sync_i <= '0';\r
+              toggle_idle <= '1';\r
+              if( link_tx_ready_qtx = '1' ) then\r
+                current_state <= SEND_IDLE_L;\r
+              else\r
+                current_state <= IDLE;\r
+              end if;\r
+        \r
             when SEND_IDLE_L =>\r
               TX_DATA_OUT <= K_IDLE;\r
               TX_K_OUT    <= '1';\r
@@ -320,12 +331,6 @@ begin
               current_state     <= SEND_RST_H;\r
               debug_sending_rst <= '1';\r
 \r
-            when IDLE =>\r
-              TX_DATA_OUT   <= K_NULL;\r
-              TX_K_OUT      <= '1';\r
-              current_state <= SEND_IDLE_L;\r
-              -- used to get out of async reset\r
-\r
             when SEND_RST_H =>\r
               word_sync_i <= '1';\r
               TX_DATA_OUT <= send_rst_word_i;\r