DLM fixed

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index 632600b4cf8cb6d5c85a7a73cca0e131d73a7f1b..99d60329e6a0170c622f2ae927a9d9e28b3499c0 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -89,7 +89,7 @@ architecture arch of tx_control_RS is
   signal load_eop                : std_logic;\r
   signal send_steady_idle_int    : std_logic;\r
   signal word_sync_i             : std_logic;\r
-  \r
+\r
   signal link_tx_ready_qtx       : std_logic;\r
   signal link_rx_ready_qtx       : std_logic;\r
   signal link_half_done_qtx      : std_logic;\r
@@ -97,7 +97,10 @@ architecture arch of tx_control_RS is
   signal link_active_int         : std_logic;\r
   signal link_active_qtx         : std_logic;\r
   signal link_active_qsys        : std_logic;\r
-  \r
+\r
+  signal tx_k_i                  : std_logic;\r
+  signal tx_data_i               : std_logic_vector(7 downto 0);\r
+\r
 --  attribute syn_keep : boolean;\r
 --  attribute syn_preserve : boolean;  \r
 --  attribute syn_keep of word_sync_i          : signal is true;\r
@@ -262,21 +265,21 @@ begin
     begin\r
       if( RESET = '1' ) then\r
         current_state <= IDLE;\r
-        TX_K_OUT    <= '1';\r
-        TX_DATA_OUT <= K_NULL;\r
-        word_sync_i <= '0';\r
+        tx_k_i        <= '1';\r
+        tx_data_i     <= K_NULL;\r
+        word_sync_i   <= '0';\r
       else \r
         if( rising_edge(CLK_TXI) ) then\r
-          TX_K_OUT          <= '0';\r
+          tx_k_i            <= '0';\r
           word_sync_i       <= '0';\r
           debug_sending_dlm <= '0';\r
           debug_sending_rst <= '0';\r
           \r
           case current_state is\r
             when IDLE =>\r
-              TX_K_OUT    <= '1';\r
-              TX_DATA_OUT <= K_NULL;\r
-              word_sync_i <= '0';\r
+              tx_k_i      <= '1';\r
+              tx_data_i     <= K_NULL;\r
+--              word_sync_i <= '0';\r
               if( link_tx_ready_qtx = '1' ) then\r
                 current_state <= SEND_IDLE_L;\r
               else\r
@@ -284,8 +287,8 @@ begin
               end if;\r
         \r
             when SEND_IDLE_L =>\r
-              TX_DATA_OUT <= K_IDLE;\r
-              TX_K_OUT    <= '1';\r
+              tx_data_i   <= K_IDLE;\r
+              tx_k_i      <= '1';\r
               if( WORD_SYNC_IN = '1' )then\r
                 current_state <= SEND_IDLE_H;\r
               else\r
@@ -295,40 +298,40 @@ begin
             when SEND_IDLE_H =>\r
               word_sync_i <= '1';\r
               if( send_steady_idle_int = '1' ) then\r
-                TX_DATA_OUT <= D_IDLE1;\r
+                tx_data_i   <= D_IDLE1;\r
               else\r
-                TX_DATA_OUT <= D_IDLE0;\r
+                tx_data_i   <= D_IDLE0;\r
               end if;\r
 \r
             when SEND_DATA_L =>\r
-              TX_DATA_OUT   <= ram_dout(7 downto 0);\r
+              tx_data_i     <= ram_dout(7 downto 0);\r
               load_sop      <= ram_dout(16);\r
               load_eop      <= ram_dout(17);\r
               current_state <= SEND_DATA_H;\r
 \r
             when SEND_DATA_H =>\r
               word_sync_i <= '1';\r
-              TX_DATA_OUT <= ram_dout(15 downto 8);\r
+              tx_data_i   <= ram_dout(15 downto 8);\r
 \r
             when SEND_DLM_L =>\r
-              TX_DATA_OUT       <= K_DLM;\r
-              TX_K_OUT          <= '1';\r
+              tx_data_i         <= K_DLM;\r
+              tx_k_i            <= '1';\r
               current_state     <= SEND_DLM_H;\r
               debug_sending_dlm <= '1';\r
 \r
             when SEND_DLM_H =>\r
               word_sync_i <= '1';\r
-              TX_DATA_OUT <= send_dlm_word_i;\r
+              tx_data_i   <= send_dlm_word_i;\r
 \r
             when SEND_RST_L =>\r
-              TX_DATA_OUT       <= K_RST;\r
-              TX_K_OUT          <= '1';\r
+              tx_data_i         <= K_RST;\r
+              tx_k_i            <= '1';\r
               current_state     <= SEND_RST_H;\r
               debug_sending_rst <= '1';\r
 \r
             when SEND_RST_H =>\r
               word_sync_i <= '1';\r
-              TX_DATA_OUT <= send_rst_word_i;\r
+              tx_data_i   <= send_rst_word_i;\r
 \r
             when others =>\r
               current_state <= SEND_IDLE_L;\r
@@ -461,5 +464,8 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI);
                 x"F";\r
 \r
   WORD_SYNC_OUT <= word_sync_i;\r
-  \r
+\r
+  TX_K_OUT    <= tx_k_i    when rising_edge(CLK_TXI);\r
+  TX_DATA_OUT <= tx_data_i when rising_edge(CLK_TXI);\r
+\r
 end architecture;\r