transport the local bhoard address to the calibration to allow for special tratment...

diff --git a/src/cri_cbm_rich_calib.vhd b/src/cri_cbm_rich_calib.vhd
index 9f0cb10e90a4206d64c6b51c345a21c5a2640542..fb9f79cc25f71002fd4675eb82e69e55f3d61cbd 100644 (file)
--- a/src/cri_cbm_rich_calib.vhd
+++ b/src/cri_cbm_rich_calib.vhd
@@ -27,6 +27,8 @@ entity cbm_rich_calib is
       CRI_APL_DATAREADY_OUT  : out std_logic;
       CRI_CALIB_EOD_OUT      : out std_logic;
       
+      MY_ADDRESS_IN          : in  std_logic_vector(15 downto 0);
+      
       BUS_RX                 : in  CTRLBUS_RX;
       BUS_TX                 : out CTRLBUS_TX
    );
@@ -379,6 +381,7 @@ begin
        DIN_TYPE               => dtype,
        DIN_READY              => data_rdy,
        DIN_STAT               => (others => '0'),
+       MY_ADDRESS_IN          => MY_ADDRESS_IN,
        FPGA_in                => dirich_addr_i,
        TRIGG_TYPE             => trigger_code_i(11 downto 8),
        

diff --git a/src/cri_data_sender.vhd b/src/cri_data_sender.vhd
index a9723830c0ccb97851c42db08b5d44626f4f9592..a511271af3d781ee5920b5f1062892ccdb8908fd 100644 (file)
--- a/src/cri_data_sender.vhd
+++ b/src/cri_data_sender.vhd
@@ -756,6 +756,8 @@ begin
       CRI_APL_DATAREADY_OUT  => cri_apl_dataready_2api_q,
       CRI_CALIB_EOD_OUT      => calib_finished_q,
       
+      MY_ADDRESS_IN          => MY_ADDRESS_IN,
+      
       BUS_RX                 => BUS_CALIBRATON_RX,
       BUS_TX                 => BUS_CALIBRATON_TX
     );