\item A external clock can be fed in via the RJ-45 connector (left, pair 2) or from the backplane. The source is selected with a switch. At power-up the board searches for an external clock on the selected input. If none is found, the internal is used.
\item The system clock can be recovered from the SFP1 input signal. This is selected at compile-time.
\end{itemize*}
+The native frequency of the board are 240 MHz, logic running at 120 MHz. Nevertheless, running at 200/100 MHz will be used for compatibility with existing setups. Most logic should be able to run at the higher speed when selected during compilation.
+
\subsubsection{Trigger Input/Output}
\begin{itemize*}
\end{tabularx}
% \caption[Trb3sc Serdes Mapping]{Mapping of Serdes channels}
\end{center}
-
+The TrbNet uplink (either Sfp or backplane) is synchronous, i.e. no clock tolerance compensation is enabled. Hence, both boards connected with the link must share a common clock source. For low-accuracy applications, the clock can be recovered from the optical link. In this case, no additional clock distribution is needed. If running in a crate, clock recovery is available, but not necessary as the backplane distributes a clock signal to all boards connected.
\subsubsection{Modifications}
The following changes compared to the original schematics are to be made:
jspc29 / daqdocu.git / commitdiff